Fixes for functional path.
If the cpu needs to update any state when it gets a functional write (LSQ??) then that code needs to be written. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: CPU's can recieve functional accesses, they need to determine if they need to do anything with them. src/mem/bus.cc: src/mem/bus.hh: Make the fuctional path do the correct tye of snoop --HG-- extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
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@ -63,7 +63,7 @@ template<class Impl>
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void
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DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
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{
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panic("DefaultFetch doesn't expect recvFunctional callback!");
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warn("Default fetch doesn't update it's state from a functional call.");
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}
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template<class Impl>
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@ -46,7 +46,7 @@ template <class Impl>
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void
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LSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
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{
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panic("O3CPU doesn't expect recvFunctional callback!");
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warn("O3CPU doesn't update things on a recvFunctional.");
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}
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template <class Impl>
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@ -59,7 +59,7 @@ template<class Impl>
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void
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FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
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{
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panic("FrontEnd doesn't expect recvFunctional callback!");
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warn("FrontEnd doesn't update state from functional calls");
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}
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template<class Impl>
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@ -72,7 +72,7 @@ template <class Impl>
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void
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OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
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{
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panic("O3CPU doesn't expect recvFunctional callback!");
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warn("O3CPU doesn't update things on a recvFunctional");
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}
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template <class Impl>
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@ -94,7 +94,7 @@ AtomicSimpleCPU::init()
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bool
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AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
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{
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panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
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panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
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return true;
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}
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@ -108,7 +108,8 @@ AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
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void
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AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
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{
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panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
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//No internal storage to update, just return
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return;
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}
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void
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@ -74,7 +74,8 @@ TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
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void
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TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
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{
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panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
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//No internal storage to update, jusst return
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return;
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}
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void
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@ -200,6 +200,18 @@ Bus::atomicSnoop(Packet *pkt)
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}
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}
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void
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Bus::functionalSnoop(Packet *pkt)
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{
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std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
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while (!ports.empty())
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{
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interfaces[ports.back()]->sendFunctional(pkt);
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ports.pop_back();
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}
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}
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bool
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Bus::timingSnoop(Packet *pkt)
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{
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@ -236,7 +248,7 @@ Bus::recvFunctional(Packet *pkt)
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DPRINTF(Bus, "recvFunctional: packet src %d dest %d addr 0x%x cmd %s\n",
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pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
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assert(pkt->getDest() == Packet::Broadcast);
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atomicSnoop(pkt);
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functionalSnoop(pkt);
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findPort(pkt->getAddr(), pkt->getSrc())->sendFunctional(pkt);
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}
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@ -102,6 +102,9 @@ class Bus : public MemObject
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/** Snoop all relevant ports atomicly. */
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void atomicSnoop(Packet *pkt);
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/** Snoop all relevant ports functionally. */
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void functionalSnoop(Packet *pkt);
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/** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want
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* the snoop to happen
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* @return True if succeds.
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