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Use PacketPtr everywhere

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--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
This commit is contained in:
Nathan Binkert 2006-10-20 00:10:12 -07:00
parent 7245d4530d
commit a4c6f0d69e
101 changed files with 429 additions and 425 deletions
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8
src/arch/alpha/isa/main.isa
View file

@ -45,20 +45,22 @@ output header {{
#include <iostream>
#include <iomanip>
#include "arch/alpha/faults.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/static_inst.hh"
#include "arch/alpha/faults.hh"
#include "mem/request.hh" // some constructors use MemReq flags
#include "mem/packet.hh"
}};
output decoder {{
#include <cmath>
#include "base/cprintf.hh"
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include <math.h>
#include "mem/packet.hh"
using namespace AlphaISA;
}};

10
src/arch/alpha/isa/mem.isa
View file

@ -186,7 +186,7 @@ def template InitiateAccDeclare {{
def template CompleteAccDeclare {{
Fault completeAcc(Packet *, %(CPU_exec_context)s *,
Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
Trace::InstRecord *) const;
}};
@ -313,7 +313,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -437,7 +437,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -460,7 +460,7 @@ def template StoreCompleteAcc {{
def template StoreCondCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -535,7 +535,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{

10
src/arch/mips/isa/formats/mem.isa
View file

@ -162,7 +162,7 @@ def template InitiateAccDeclare {{
def template CompleteAccDeclare {{
Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
@ -288,7 +288,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -412,7 +412,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -434,7 +434,7 @@ def template StoreCompleteAcc {{
}};
def template StoreCondCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -509,7 +509,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{

22
src/arch/mips/isa/includes.isa
View file

@ -38,24 +38,26 @@ output header {{
#include <iostream>
#include <iomanip>
#include "cpu/static_inst.hh"
#include "arch/mips/isa_traits.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
}};
output decoder {{
#include "arch/mips/isa_traits.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/utility.hh"
#include <math.h>
#include <cmath>
#if defined(linux)
#include <fenv.h>
#endif
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/utility.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
using namespace MipsISA;
}};

4
src/cpu/checker/cpu.cc
View file

@ -169,7 +169,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
// translate to physical address
translateDataReadReq(memReq);
Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
pkt->dataStatic(&data);
@ -256,7 +256,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
T inst_data;
/*
// This code would work if the LSQ allowed for snooping.
Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
pkt.dataStatic(&inst_data);
dcachePort->sendFunctional(pkt);

2
src/cpu/checker/cpu_impl.hh
View file

@ -181,7 +181,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
}
if (fault == NoFault) {
Packet *pkt = new Packet(memReq, Packet::ReadReq,
PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
Packet::Broadcast);
pkt->dataStatic(&machInst);

14
src/cpu/memtest/memtest.cc
View file

@ -55,21 +55,21 @@ using namespace std;
int TESTER_ALLOCATOR=0;
bool
MemTest::CpuPort::recvTiming(Packet *pkt)
MemTest::CpuPort::recvTiming(PacketPtr pkt)
{
memtest->completeRequest(pkt);
return true;
}
Tick
MemTest::CpuPort::recvAtomic(Packet *pkt)
MemTest::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("MemTest doesn't expect recvAtomic callback!");
return curTick;
}
void
MemTest::CpuPort::recvFunctional(Packet *pkt)
MemTest::CpuPort::recvFunctional(PacketPtr pkt)
{
//Do nothing if we see one come through
// if (curTick != 0)//Supress warning durring initialization
@ -94,7 +94,7 @@ MemTest::CpuPort::recvRetry()
}
void
MemTest::sendPkt(Packet *pkt) {
MemTest::sendPkt(PacketPtr pkt) {
if (atomic) {
cachePort.sendAtomic(pkt);
pkt->makeAtomicResponse();
@ -204,7 +204,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
}
void
MemTest::completeRequest(Packet *pkt)
MemTest::completeRequest(PacketPtr pkt)
{
MemTestSenderState *state =
dynamic_cast<MemTestSenderState *>(pkt->senderState);
@ -381,7 +381,7 @@ MemTest::tick()
<< dec << curTick << endl;
}
Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
PacketPtr pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
@ -421,7 +421,7 @@ MemTest::tick()
<< dec << curTick << endl;
}
*/
Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
PacketPtr pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());

12
src/cpu/memtest/memtest.hh
View file

@ -102,11 +102,11 @@ class MemTest : public MemObject
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@ -133,7 +133,7 @@ class MemTest : public MemObject
};
// Request *dataReq;
Packet *retryPkt;
PacketPtr retryPkt;
// MemInterface *cacheInterface;
// PhysicalMemory *mainMem;
// PhysicalMemory *checkMem;
@ -184,9 +184,9 @@ class MemTest : public MemObject
Stats::Scalar<> numCopiesStat;
// called by MemCompleteEvent::process()
void completeRequest(Packet *pkt);
void completeRequest(PacketPtr pkt);
void sendPkt(Packet *pkt);
void sendPkt(PacketPtr pkt);
void doRetry();

2
src/cpu/o3/alpha/dyn_inst.hh
View file

@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
Fault initiateAcc();
/** Completes the access. Only valid for memory operations. */
Fault completeAcc(Packet *pkt);
Fault completeAcc(PacketPtr pkt);
private:
/** Initializes variables. */

2
src/cpu/o3/alpha/dyn_inst_impl.hh
View file

@ -100,7 +100,7 @@ AlphaDynInst<Impl>::initiateAcc()
template <class Impl>
Fault
AlphaDynInst<Impl>::completeAcc(Packet *pkt)
AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);

2
src/cpu/o3/fetch_impl.hh
View file

@ -78,7 +78,7 @@ DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
template<class Impl>
bool
DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
fetch->processCacheCompletion(pkt);

2
src/cpu/o3/lsq_unit.hh
View file

@ -219,7 +219,7 @@ class LSQUnit {
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
void storePostSend(Packet *pkt);
void storePostSend(PacketPtr pkt);
/** Completes the store at the specified index. */
void completeStore(int store_idx);

2
src/cpu/o3/lsq_unit_impl.hh
View file

@ -763,7 +763,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
template <class Impl>
void
LSQUnit<Impl>::storePostSend(Packet *pkt)
LSQUnit<Impl>::storePostSend(PacketPtr pkt)
{
if (isStalled() &&
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {

2
src/cpu/o3/mips/dyn_inst.hh
View file

@ -87,7 +87,7 @@ class MipsDynInst : public BaseDynInst<Impl>
Fault initiateAcc();
/** Completes the access. Only valid for memory operations. */
Fault completeAcc(Packet *pkt);
Fault completeAcc(PacketPtr pkt);
private:
/** Initializes variables. */

2
src/cpu/o3/mips/dyn_inst_impl.hh
View file

@ -100,7 +100,7 @@ MipsDynInst<Impl>::initiateAcc()
template <class Impl>
Fault
MipsDynInst<Impl>::completeAcc(Packet *pkt)
MipsDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);

2
src/cpu/ozone/dyn_inst.hh
View file

@ -133,7 +133,7 @@ class OzoneDynInst : public BaseDynInst<Impl>
Fault initiateAcc();
Fault completeAcc(Packet *pkt);
Fault completeAcc(PacketPtr pkt);
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural

2
src/cpu/ozone/dyn_inst_impl.hh
View file

@ -108,7 +108,7 @@ OzoneDynInst<Impl>::initiateAcc()
template <class Impl>
Fault
OzoneDynInst<Impl>::completeAcc(Packet *pkt)
OzoneDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);

2
src/cpu/ozone/front_end.hh
View file

@ -129,7 +129,7 @@ class FrontEnd
const bool is_branch = false, const bool branch_taken = false);
DynInstPtr getInst();
void processCacheCompletion(Packet *pkt);
void processCacheCompletion(PacketPtr pkt);
void addFreeRegs(int num_freed);

2
src/cpu/ozone/front_end_impl.hh
View file

@ -74,7 +74,7 @@ FrontEnd<Impl>::IcachePort::recvStatusChange(Status status)
template<class Impl>
bool
FrontEnd<Impl>::IcachePort::recvTiming(Packet *pkt)
FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
fe->processCacheCompletion(pkt);
return true;

2
src/cpu/ozone/lw_lsq.hh
View file

@ -222,7 +222,7 @@ class OzoneLWLSQ {
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
void storePostSend(Packet *pkt, DynInstPtr &inst);
void storePostSend(PacketPtr pkt, DynInstPtr &inst);
/** Completes the store at the specified index. */
void completeStore(DynInstPtr &inst);

2
src/cpu/ozone/lw_lsq_impl.hh
View file

@ -832,7 +832,7 @@ OzoneLWLSQ<Impl>::dumpInsts()
template <class Impl>
void
OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
{
if (isStalled() &&
inst->seqNum == stallingStoreIsn) {

10
src/cpu/simple/atomic.cc
View file

@ -93,21 +93,21 @@ AtomicSimpleCPU::init()
}
bool
AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
{
panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
return true;
}
Tick
AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
//Snooping a coherence request, just return
return curTick;
}
void
AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, just return
return;
@ -260,7 +260,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
// use the CPU's statically allocated read request and packet objects
Request *req = data_read_req;
Packet *pkt = data_read_pkt;
PacketPtr pkt = data_read_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
@ -342,7 +342,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
// use the CPU's statically allocated write request and packet objects
Request *req = data_write_req;
Packet *pkt = data_write_pkt;
PacketPtr pkt = data_write_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());

18
src/cpu/simple/atomic.hh
View file

@ -92,11 +92,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@ -110,12 +110,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
CpuPort icachePort;
CpuPort dcachePort;
Request *ifetch_req;
Packet *ifetch_pkt;
Request *data_read_req;
Packet *data_read_pkt;
Request *data_write_req;
Packet *data_write_pkt;
Request *ifetch_req;
PacketPtr ifetch_pkt;
Request *data_read_req;
PacketPtr data_read_pkt;
Request *data_write_req;
PacketPtr data_write_pkt;
bool dcache_access;
Tick dcache_latency;

20
src/cpu/simple/timing.cc
View file

@ -66,14 +66,14 @@ TimingSimpleCPU::init()
}
Tick
TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
return curTick;
}
void
TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, jusst return
return;
@ -90,7 +90,7 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
void
TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
{
pkt = _pkt;
Event::schedule(t);
@ -269,7 +269,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
Packet *pkt =
PacketPtr pkt =
new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamic<T>(new T);
@ -471,7 +471,7 @@ TimingSimpleCPU::advanceInst(Fault fault)
void
TimingSimpleCPU::completeIfetch(Packet *pkt)
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
// received a response from the icache: execute the received
// instruction
@ -527,7 +527,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
}
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
@ -555,7 +555,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
// waiting to transmit
assert(cpu->ifetch_pkt != NULL);
assert(cpu->_status == IcacheRetry);
Packet *tmp = cpu->ifetch_pkt;
PacketPtr tmp = cpu->ifetch_pkt;
if (sendTiming(tmp)) {
cpu->_status = IcacheWaitResponse;
cpu->ifetch_pkt = NULL;
@ -563,7 +563,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
}
void
TimingSimpleCPU::completeDataAccess(Packet *pkt)
TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
{
// received a response from the dcache: complete the load or store
// instruction
@ -605,7 +605,7 @@ TimingSimpleCPU::completeDrain()
}
bool
TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
@ -639,7 +639,7 @@ TimingSimpleCPU::DcachePort::recvRetry()
// waiting to transmit
assert(cpu->dcache_pkt != NULL);
assert(cpu->_status == DcacheRetry);
Packet *tmp = cpu->dcache_pkt;
PacketPtr tmp = cpu->dcache_pkt;
if (sendTiming(tmp)) {
cpu->_status = DcacheWaitResponse;
// memory system takes ownership of packet

20
src/cpu/simple/timing.hh
View file

@ -84,9 +84,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@ -96,13 +96,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
struct TickEvent : public Event
{
Packet *pkt;
PacketPtr pkt;
TimingSimpleCPU *cpu;
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
const char *description() { return "Timing CPU clock event"; }
void schedule(Packet *_pkt, Tick t);
void schedule(PacketPtr _pkt, Tick t);
};
};
@ -117,7 +117,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@ -144,7 +144,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@ -163,8 +163,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
IcachePort icachePort;
DcachePort dcachePort;
Packet *ifetch_pkt;
Packet *dcache_pkt;
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
int cpu_id;
Tick previousTick;
@ -192,8 +192,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
void fetch();
void completeIfetch(Packet *);
void completeDataAccess(Packet *);
void completeIfetch(PacketPtr );
void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
private:
void completeDrain();

4
src/dev/alpha_console.cc
View file

@ -94,7 +94,7 @@ AlphaConsole::startup()
}
Tick
AlphaConsole::read(Packet *pkt)
AlphaConsole::read(PacketPtr pkt)
{
/** XXX Do we want to push the addr munging to a bus brige or something? So
@ -195,7 +195,7 @@ AlphaConsole::read(Packet *pkt)
}
Tick
AlphaConsole::write(Packet *pkt)
AlphaConsole::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);

4
src/dev/alpha_console.hh
View file

@ -118,8 +118,8 @@ class AlphaConsole : public BasicPioDevice
/**
* memory mapped reads and writes
*/
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
/**
* standard serialization routines for checkpointing

4
src/dev/baddev.cc
View file

@ -53,13 +53,13 @@ BadDevice::BadDevice(Params *p)
}
Tick
BadDevice::read(Packet *pkt)
BadDevice::read(PacketPtr pkt)
{
panic("Device %s not imlpmented\n", devname);
}
Tick
BadDevice::write(Packet *pkt)
BadDevice::write(PacketPtr pkt)
{
panic("Device %s not imlpmented\n", devname);
}

4
src/dev/baddev.hh
View file

@ -67,8 +67,8 @@ class BadDevice : public BasicPioDevice
*/
BadDevice(Params *p);
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
};
#endif // __DEV_BADDEV_HH__

6
src/dev/i8254xGBe.cc
View file

@ -47,7 +47,7 @@ IGbE::IGbE(Params *p)
Tick
IGbE::writeConfig(Packet *pkt)
IGbE::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
@ -63,7 +63,7 @@ IGbE::writeConfig(Packet *pkt)
}
Tick
IGbE::read(Packet *pkt)
IGbE::read(PacketPtr pkt)
{
int bar;
Addr daddr;
@ -88,7 +88,7 @@ IGbE::read(Packet *pkt)
}
Tick
IGbE::write(Packet *pkt)
IGbE::write(PacketPtr pkt)
{
int bar;
Addr daddr;

6
src/dev/i8254xGBe.hh
View file

@ -59,10 +59,10 @@ class IGbE : public PciDev
IGbE(Params *params);
~IGbE() {;}
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
virtual Tick writeConfig(Packet *pkt);
virtual Tick writeConfig(PacketPtr pkt);
bool ethRxPkt(EthPacketPtr packet);
void ethTxDone();

8
src/dev/ide_ctrl.cc
View file

@ -229,7 +229,7 @@ IdeController::setDmaComplete(IdeDisk *disk)
////
Tick
IdeController::readConfig(Packet *pkt)
IdeController::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
@ -302,7 +302,7 @@ IdeController::readConfig(Packet *pkt)
Tick
IdeController::writeConfig(Packet *pkt)
IdeController::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC) {
@ -409,7 +409,7 @@ IdeController::writeConfig(Packet *pkt)
Tick
IdeController::read(Packet *pkt)
IdeController::read(PacketPtr pkt)
{
Addr offset;
IdeChannel channel;
@ -495,7 +495,7 @@ IdeController::read(Packet *pkt)
}
Tick
IdeController::write(Packet *pkt)
IdeController::write(PacketPtr pkt)
{
Addr offset;
IdeChannel channel;

8
src/dev/ide_ctrl.hh
View file

@ -204,8 +204,8 @@ class IdeController : public PciDev
IdeController(Params *p);
~IdeController();
virtual Tick writeConfig(Packet *pkt);
virtual Tick readConfig(Packet *pkt);
virtual Tick writeConfig(PacketPtr pkt);
virtual Tick readConfig(PacketPtr pkt);
void setDmaComplete(IdeDisk *disk);
@ -214,14 +214,14 @@ class IdeController : public PciDev
* @param pkt Packet describing what is to be read
* @return The amount of time to complete this request
*/
virtual Tick read(Packet *pkt);
virtual Tick read(PacketPtr pkt);
/**
* Write a done field for a given target.
* @param pkt Packet describing what is to be written
* @return The amount of time to complete this request
*/
virtual Tick write(Packet *pkt);
virtual Tick write(PacketPtr pkt);
/**
* Serialize this object to the given output stream.

10
src/dev/io_device.cc
View file

@ -42,7 +42,7 @@ PioPort::PioPort(PioDevice *dev, System *s, std::string pname)
Tick
PioPort::recvAtomic(Packet *pkt)
PioPort::recvAtomic(PacketPtr pkt)
{
return pkt->isRead() ? device->read(pkt) : device->write(pkt);
}
@ -97,7 +97,7 @@ DmaPort::DmaPort(DmaDevice *dev, System *s)
{ }
bool
DmaPort::recvTiming(Packet *pkt)
DmaPort::recvTiming(PacketPtr pkt)
{
@ -165,7 +165,7 @@ DmaPort::drain(Event *de)
void
DmaPort::recvRetry()
{
Packet* pkt = transmitList.front();
PacketPtr pkt = transmitList.front();
bool result = true;
while (result && transmitList.size()) {
DPRINTF(DMA, "Retry on Packet %#x with senderState: %#x\n",
@ -194,7 +194,7 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
for (ChunkGenerator gen(addr, size, peerBlockSize());
!gen.done(); gen.next()) {
Request *req = new Request(gen.addr(), gen.size(), 0);
Packet *pkt = new Packet(req, cmd, Packet::Broadcast);
PacketPtr pkt = new Packet(req, cmd, Packet::Broadcast);
// Increment the data pointer on a write
if (data)
@ -211,7 +211,7 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
void
DmaPort::sendDma(Packet *pkt, bool front)
DmaPort::sendDma(PacketPtr pkt, bool front)
{
// some kind of selction between access methods
// more work is going to have to be done to make

16
src/dev/io_device.hh
View file

@ -56,7 +56,7 @@ class PioPort : public SimpleTimingPort
/** The device that this port serves. */
PioDevice *device;
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop);
@ -91,7 +91,7 @@ class DmaPort : public Port
};
DmaDevice *device;
std::list<Packet*> transmitList;
std::list<PacketPtr> transmitList;
/** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
@ -107,10 +107,10 @@ class DmaPort : public Port
* here.*/
Event *drainEvent;
virtual bool recvTiming(Packet *pkt);
virtual Tick recvAtomic(Packet *pkt)
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt)
{ panic("dma port shouldn't be used for pio access."); }
virtual void recvFunctional(Packet *pkt)
virtual void recvFunctional(PacketPtr pkt)
{ panic("dma port shouldn't be used for pio access."); }
virtual void recvStatusChange(Status status)
@ -122,7 +122,7 @@ class DmaPort : public Port
AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
void sendDma(Packet *pkt, bool front = false);
void sendDma(PacketPtr pkt, bool front = false);
public:
DmaPort(DmaDevice *dev, System *s);
@ -163,14 +163,14 @@ class PioDevice : public MemObject
* @param pkt Packet describing this request
* @return number of ticks it took to complete
*/
virtual Tick read(Packet *pkt) = 0;
virtual Tick read(PacketPtr pkt) = 0;
/** Pure virtual function that the device must implement. Called when a
* write command is recieved by the port.
* @param pkt Packet describing this request
* @return number of ticks it took to complete
*/
virtual Tick write(Packet *pkt) = 0;
virtual Tick write(PacketPtr pkt) = 0;
public:
/** Params struct which is extended through each device based on

4
src/dev/isa_fake.cc
View file

@ -53,7 +53,7 @@ IsaFake::IsaFake(Params *p)
}
Tick
IsaFake::read(Packet *pkt)
IsaFake::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
@ -80,7 +80,7 @@ IsaFake::read(Packet *pkt)
}
Tick
IsaFake::write(Packet *pkt)
IsaFake::write(PacketPtr pkt)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
pkt->result = Packet::Success;

4
src/dev/isa_fake.hh
View file

@ -69,14 +69,14 @@ class IsaFake : public BasicPioDevice
* @param pkt The memory request.
* @param data Where to put the data.
*/
virtual Tick read(Packet *pkt);
virtual Tick read(PacketPtr pkt);
/**
* All writes are simply ignored.
* @param pkt The memory request.
* @param data the data to not write.
*/
virtual Tick write(Packet *pkt);
virtual Tick write(PacketPtr pkt);
};
#endif // __TSUNAMI_FAKE_HH__

6
src/dev/ns_gige.cc
View file

@ -467,7 +467,7 @@ NSGigE::regStats()
* This is to write to the PCI general configuration registers
*/
Tick
NSGigE::writeConfig(Packet *pkt)
NSGigE::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
@ -495,7 +495,7 @@ NSGigE::writeConfig(Packet *pkt)
* spec sheet
*/
Tick
NSGigE::read(Packet *pkt)
NSGigE::read(PacketPtr pkt)
{
assert(ioEnable);
@ -719,7 +719,7 @@ NSGigE::read(Packet *pkt)
}
Tick
NSGigE::write(Packet *pkt)
NSGigE::write(PacketPtr pkt)
{
assert(ioEnable);

6
src/dev/ns_gige.hh
View file

@ -375,10 +375,10 @@ class NSGigE : public PciDev
~NSGigE();
const Params *params() const { return (const Params *)_params; }
virtual Tick writeConfig(Packet *pkt);
virtual Tick writeConfig(PacketPtr pkt);
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }

4
src/dev/pciconfigall.cc
View file

@ -52,7 +52,7 @@ PciConfigAll::PciConfigAll(Params *p)
Tick
PciConfigAll::read(Packet *pkt)
PciConfigAll::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
@ -79,7 +79,7 @@ PciConfigAll::read(Packet *pkt)
}
Tick
PciConfigAll::write(Packet *pkt)
PciConfigAll::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
panic("Attempting to write to config space on non-existant device\n");

4
src/dev/pciconfigall.hh
View file

@ -73,7 +73,7 @@ class PciConfigAll : public PioDevice
* @param pkt Contains information about the read operation
* @return Amount of time to do the read
*/
virtual Tick read(Packet *pkt);
virtual Tick read(PacketPtr pkt);
/**
* Write to PCI config spcae. If the device does not exit the simulator
@ -83,7 +83,7 @@ class PciConfigAll : public PioDevice
* @return Amount of time to do the read
*/
virtual Tick write(Packet *pkt);
virtual Tick write(PacketPtr pkt);
void addressRanges(AddrRangeList &range_list);

6
src/dev/pcidev.cc
View file

@ -66,7 +66,7 @@ PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
Tick
PciDev::PciConfigPort::recvAtomic(Packet *pkt)
PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= configAddr &&
@ -123,7 +123,7 @@ PciDev::drain(Event *de)
}
Tick
PciDev::readConfig(Packet *pkt)
PciDev::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
@ -172,7 +172,7 @@ PciDev::addressRanges(AddrRangeList &range_list)
}
Tick
PciDev::writeConfig(Packet *pkt)
PciDev::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)

6
src/dev/pcidev.hh
View file

@ -84,7 +84,7 @@ class PciDev : public DmaDevice
protected:
PciDev *device;
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop);
@ -202,7 +202,7 @@ class PciDev : public DmaDevice
* for normal operations that it does not need to override.
* @param pkt packet containing the write the offset into config space
*/
virtual Tick writeConfig(Packet *pkt);
virtual Tick writeConfig(PacketPtr pkt);
/**
@ -211,7 +211,7 @@ class PciDev : public DmaDevice
* for normal operations that it does not need to override.
* @param pkt packet containing the write the offset into config space
*/
virtual Tick readConfig(Packet *pkt);
virtual Tick readConfig(PacketPtr pkt);
public:
Addr pciToDma(Addr pciAddr) const

4
src/dev/sinic.cc
View file

@ -314,7 +314,7 @@ Device::prepareWrite(int cpu, int index)
* I/O read of device register
*/
Tick
Device::read(Packet *pkt)
Device::read(PacketPtr pkt)
{
assert(config.command & PCI_CMD_MSE);
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
@ -401,7 +401,7 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
* I/O write of device register
*/
Tick
Device::write(Packet *pkt)
Device::write(PacketPtr pkt)
{
assert(config.command & PCI_CMD_MSE);
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);

4
src/dev/sinic.hh
View file

@ -264,8 +264,8 @@ class Device : public Base
* Memory Interface
*/
public:
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
virtual void resume();
void prepareIO(int cpu, int index);

4
src/dev/tsunami_cchip.cc
View file

@ -74,7 +74,7 @@ TsunamiCChip::TsunamiCChip(Params *p)
}
Tick
TsunamiCChip::read(Packet *pkt)
TsunamiCChip::read(PacketPtr pkt)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
@ -184,7 +184,7 @@ TsunamiCChip::read(Packet *pkt)
}
Tick
TsunamiCChip::write(Packet *pkt)
TsunamiCChip::write(PacketPtr pkt)
{
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;

4
src/dev/tsunami_cchip.hh
View file

@ -94,9 +94,9 @@ class TsunamiCChip : public BasicPioDevice
*/
TsunamiCChip(Params *p);
virtual Tick read(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(Packet *pkt);
virtual Tick write(PacketPtr pkt);
/**
* post an RTC interrupt to the CPU

4
src/dev/tsunami_io.cc
View file

@ -448,7 +448,7 @@ TsunamiIO::frequency() const
}
Tick
TsunamiIO::read(Packet *pkt)
TsunamiIO::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
@ -514,7 +514,7 @@ TsunamiIO::read(Packet *pkt)
}
Tick
TsunamiIO::write(Packet *pkt)
TsunamiIO::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);

4
src/dev/tsunami_io.hh
View file

@ -328,8 +328,8 @@ class TsunamiIO : public BasicPioDevice
*/
TsunamiIO(Params *p);
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
/**
* Post an PIC interrupt to the CPU via the CChip

4
src/dev/tsunami_pchip.cc
View file

@ -69,7 +69,7 @@ TsunamiPChip::TsunamiPChip(Params *p)
}
Tick
TsunamiPChip::read(Packet *pkt)
TsunamiPChip::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
@ -151,7 +151,7 @@ TsunamiPChip::read(Packet *pkt)
}
Tick
TsunamiPChip::write(Packet *pkt)
TsunamiPChip::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);

4
src/dev/tsunami_pchip.hh
View file

@ -85,8 +85,8 @@ class TsunamiPChip : public BasicPioDevice
Addr calcConfigAddr(int bus, int dev, int func);
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
/**
* Serialize this object to the given output stream.

4
src/dev/uart8250.cc
View file

@ -112,7 +112,7 @@ Uart8250::Uart8250(Params *p)
}
Tick
Uart8250::read(Packet *pkt)
Uart8250::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
@ -194,7 +194,7 @@ Uart8250::read(Packet *pkt)
}
Tick
Uart8250::write(Packet *pkt)
Uart8250::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);

4
src/dev/uart8250.hh
View file

@ -82,8 +82,8 @@ class Uart8250 : public Uart
public:
Uart8250(Params *p);
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
virtual void addressRanges(AddrRangeList &range_list);

10
src/mem/bridge.cc
View file

@ -89,7 +89,7 @@ Bridge::init()
/** Function called by the port when the bus is receiving a Timing
* transaction.*/
bool
Bridge::BridgePort::recvTiming(Packet *pkt)
Bridge::BridgePort::recvTiming(PacketPtr pkt)
{
DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n",
pkt->getSrc(), pkt->getDest(), pkt->getAddr());
@ -99,7 +99,7 @@ Bridge::BridgePort::recvTiming(Packet *pkt)
bool
Bridge::BridgePort::queueForSendTiming(Packet *pkt)
Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
{
if (queueFull())
return false;
@ -148,7 +148,7 @@ Bridge::BridgePort::trySend()
assert(buf->ready <= curTick);
Packet *pkt = buf->pkt;
PacketPtr pkt = buf->pkt;
DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
buf->origSrc, pkt->getDest(), pkt->getAddr());
@ -198,7 +198,7 @@ Bridge::BridgePort::recvRetry()
/** Function called by the port when the bus is receiving a Atomic
* transaction.*/
Tick
Bridge::BridgePort::recvAtomic(Packet *pkt)
Bridge::BridgePort::recvAtomic(PacketPtr pkt)
{
return otherPort->sendAtomic(pkt) + delay;
}
@ -206,7 +206,7 @@ Bridge::BridgePort::recvAtomic(Packet *pkt)
/** Function called by the port when the bus is receiving a Functional
* transaction.*/
void
Bridge::BridgePort::recvFunctional(Packet *pkt)
Bridge::BridgePort::recvFunctional(PacketPtr pkt)
{
std::list<PacketBuffer*>::iterator i;
bool pktContinue = true;

14
src/mem/bridge.hh
View file

@ -70,12 +70,12 @@ class Bridge : public MemObject
public:
Tick ready;
Packet *pkt;
PacketPtr pkt;
Packet::SenderState *origSenderState;
short origSrc;
bool expectResponse;
PacketBuffer(Packet *_pkt, Tick t)
PacketBuffer(PacketPtr _pkt, Tick t)
: ready(t), pkt(_pkt),
origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()),
expectResponse(_pkt->needsResponse())
@ -84,7 +84,7 @@ class Bridge : public MemObject
pkt->senderState = this;
}
void fixResponse(Packet *pkt)
void fixResponse(PacketPtr pkt)
{
assert(pkt->senderState == this);
pkt->setDest(origSrc);
@ -109,7 +109,7 @@ class Bridge : public MemObject
*/
bool queueFull() { return (sendQueue.size() == queueLimit); }
bool queueForSendTiming(Packet *pkt);
bool queueForSendTiming(PacketPtr pkt);
void finishSend(PacketBuffer *buf);
@ -146,7 +146,7 @@ class Bridge : public MemObject
/** When receiving a timing request from the peer port,
pass it to the bridge. */
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
/** When receiving a retry request from the peer port,
pass it to the bridge. */
@ -154,11 +154,11 @@ class Bridge : public MemObject
/** When receiving a Atomic requestfrom the peer port,
pass it to the bridge. */
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
/** When receiving a Functional request from the peer port,
pass it to the bridge. */
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
/** When receiving a status changefrom the peer port,
pass it to the bridge. */

12
src/mem/bus.cc
View file

@ -138,7 +138,7 @@ void Bus::occupyBus(PacketPtr pkt)
/** Function called by the port when the bus is receiving a Timing
* transaction.*/
bool
Bus::recvTiming(Packet *pkt)
Bus::recvTiming(PacketPtr pkt)
{
Port *port;
DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
@ -301,7 +301,7 @@ Bus::findSnoopPorts(Addr addr, int id)
}
Tick
Bus::atomicSnoop(Packet *pkt)
Bus::atomicSnoop(PacketPtr pkt)
{
std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
Tick response_time = 0;
@ -319,7 +319,7 @@ Bus::atomicSnoop(Packet *pkt)
}
void
Bus::functionalSnoop(Packet *pkt)
Bus::functionalSnoop(PacketPtr pkt)
{
std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
@ -331,7 +331,7 @@ Bus::functionalSnoop(Packet *pkt)
}
bool
Bus::timingSnoop(Packet *pkt)
Bus::timingSnoop(PacketPtr pkt)
{
std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
bool success = true;
@ -349,7 +349,7 @@ Bus::timingSnoop(Packet *pkt)
/** Function called by the port when the bus is receiving a Atomic
* transaction.*/
Tick
Bus::recvAtomic(Packet *pkt)
Bus::recvAtomic(PacketPtr pkt)
{
DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n",
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
@ -364,7 +364,7 @@ Bus::recvAtomic(Packet *pkt)
/** Function called by the port when the bus is receiving a Functional
* transaction.*/
void
Bus::recvFunctional(Packet *pkt)
Bus::recvFunctional(PacketPtr pkt)
{
DPRINTF(Bus, "recvFunctional: packet src %d dest %d addr 0x%x cmd %s\n",
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());

18
src/mem/bus.hh
View file

@ -71,15 +71,15 @@ class Bus : public MemObject
/** Function called by the port when the bus is recieving a Timing
transaction.*/
bool recvTiming(Packet *pkt);
bool recvTiming(PacketPtr pkt);
/** Function called by the port when the bus is recieving a Atomic
transaction.*/
Tick recvAtomic(Packet *pkt);
Tick recvAtomic(PacketPtr pkt);
/** Function called by the port when the bus is recieving a Functional
transaction.*/
void recvFunctional(Packet *pkt);
void recvFunctional(PacketPtr pkt);
/** Timing function called by port when it is once again able to process
* requests. */
@ -107,16 +107,16 @@ class Bus : public MemObject
std::vector<int> findSnoopPorts(Addr addr, int id);
/** Snoop all relevant ports atomicly. */
Tick atomicSnoop(Packet *pkt);
Tick atomicSnoop(PacketPtr pkt);
/** Snoop all relevant ports functionally. */
void functionalSnoop(Packet *pkt);
void functionalSnoop(PacketPtr pkt);
/** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want
* the snoop to happen
* @return True if succeds.
*/
bool timingSnoop(Packet *pkt);
bool timingSnoop(PacketPtr pkt);
/** Process address range request.
* @param resp addresses that we can respond to
@ -157,17 +157,17 @@ class Bus : public MemObject
/** When reciving a timing request from the peer port (at id),
pass it to the bus. */
virtual bool recvTiming(Packet *pkt)
virtual bool recvTiming(PacketPtr pkt)
{ pkt->setSrc(id); return bus->recvTiming(pkt); }
/** When reciving a Atomic requestfrom the peer port (at id),
pass it to the bus. */
virtual Tick recvAtomic(Packet *pkt)
virtual Tick recvAtomic(PacketPtr pkt)
{ pkt->setSrc(id); return bus->recvAtomic(pkt); }
/** When reciving a Functional requestfrom the peer port (at id),
pass it to the bus. */
virtual void recvFunctional(Packet *pkt)
virtual void recvFunctional(PacketPtr pkt)
{ pkt->setSrc(id); bus->recvFunctional(pkt); }
/** When reciving a status changefrom the peer port (at id),

20
src/mem/cache/base_cache.cc vendored
View file

@ -71,7 +71,7 @@ BaseCache::CachePort::deviceBlockSize()
}
bool
BaseCache::CachePort::recvTiming(Packet *pkt)
BaseCache::CachePort::recvTiming(PacketPtr pkt)
{
if (isCpuSide
&& !pkt->req->isUncacheable()
@ -99,19 +99,19 @@ BaseCache::CachePort::recvTiming(Packet *pkt)
}
Tick
BaseCache::CachePort::recvAtomic(Packet *pkt)
BaseCache::CachePort::recvAtomic(PacketPtr pkt)
{
return cache->doAtomicAccess(pkt, isCpuSide);
}
void
BaseCache::CachePort::recvFunctional(Packet *pkt)
BaseCache::CachePort::recvFunctional(PacketPtr pkt)
{
//Check storage here first
list<Packet *>::iterator i = drainList.begin();
list<Packet *>::iterator end = drainList.end();
list<PacketPtr>::iterator i = drainList.begin();
list<PacketPtr>::iterator end = drainList.end();
for (; i != end; ++i) {
Packet * target = *i;
PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt)) {
@ -149,7 +149,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt)
void
BaseCache::CachePort::recvRetry()
{
Packet *pkt;
PacketPtr pkt;
assert(waitingOnRetry);
if (!drainList.empty()) {
DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
@ -181,7 +181,7 @@ BaseCache::CachePort::recvRetry()
pkt = cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
//Copy the packet, it may be modified/destroyed elsewhere
Packet * copyPkt = new Packet(*pkt);
PacketPtr copyPkt = new Packet(*pkt);
copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
mshr->pkt = copyPkt;
@ -257,7 +257,7 @@ BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
pkt = NULL;
}
BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, PacketPtr _pkt)
: Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
{
this->setFlags(AutoDelete);
@ -301,7 +301,7 @@ BaseCache::CacheEvent::process()
pkt = cachePort->cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
//Copy the packet, it may be modified/destroyed elsewhere
Packet * copyPkt = new Packet(*pkt);
PacketPtr copyPkt = new Packet(*pkt);
copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
mshr->pkt = copyPkt;

32
src/mem/cache/base_cache.hh vendored
View file

@ -85,11 +85,11 @@ class BaseCache : public MemObject
CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
protected:
virtual bool recvTiming(Packet *pkt);
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@ -113,17 +113,17 @@ class BaseCache : public MemObject
bool waitingOnRetry;
std::list<Packet *> drainList;
std::list<PacketPtr> drainList;
};
struct CacheEvent : public Event
{
CachePort *cachePort;
Packet *pkt;
PacketPtr pkt;
CacheEvent(CachePort *_cachePort);
CacheEvent(CachePort *_cachePort, Packet *_pkt);
CacheEvent(CachePort *_cachePort, PacketPtr _pkt);
void process();
const char *description();
};
@ -141,17 +141,17 @@ class BaseCache : public MemObject
private:
//To be defined in cache_impl.hh not in base class
virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
{
fatal("No implementation");
}
virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide)
{
fatal("No implementation");
}
virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
{
fatal("No implementation");
}
@ -172,23 +172,23 @@ class BaseCache : public MemObject
}
}
virtual Packet *getPacket()
virtual PacketPtr getPacket()
{
fatal("No implementation");
}
virtual Packet *getCoherencePacket()
virtual PacketPtr getCoherencePacket()
{
fatal("No implementation");
}
virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
{
fatal("No implementation");
}
virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success)
virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* mshr, bool success)
{
fatal("No implementation");
@ -519,7 +519,7 @@ class BaseCache : public MemObject
* @param pkt The request being responded to.
* @param time The time the response is ready.
*/
void respond(Packet *pkt, Tick time)
void respond(PacketPtr pkt, Tick time)
{
if (pkt->needsResponse()) {
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
@ -539,7 +539,7 @@ class BaseCache : public MemObject
* @param pkt The request to respond to.
* @param time The time the response is ready.
*/
void respondToMiss(Packet *pkt, Tick time)
void respondToMiss(PacketPtr pkt, Tick time)
{
if (!pkt->req->isUncacheable()) {
missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
@ -561,7 +561,7 @@ class BaseCache : public MemObject
* Suppliess the data if cache to cache transfers are enabled.
* @param pkt The bus transaction to fulfill.
*/
void respondToSnoop(Packet *pkt, Tick time)
void respondToSnoop(PacketPtr pkt, Tick time)
{
assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);

28
src/mem/cache/cache.hh vendored
View file

@ -96,7 +96,7 @@ class Cache : public BaseCache
* A permanent mem req to always be used to cause invalidations.
* Used to append to target list, to cause an invalidation.
*/
Packet * invalidatePkt;
PacketPtr invalidatePkt;
Request *invalidateReq;
public:
@ -127,12 +127,12 @@ class Cache : public BaseCache
/** Instantiates a basic cache object. */
Cache(const std::string &_name, Params &params);
virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
bool isCpuSide);
virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
virtual void recvStatusChange(Port::Status status, bool isCpuSide);
@ -143,47 +143,47 @@ class Cache : public BaseCache
* @param pkt The request to perform.
* @return The result of the access.
*/
bool access(Packet * &pkt);
bool access(PacketPtr &pkt);
/**
* Selects a request to send on the bus.
* @return The memory request to service.
*/
virtual Packet * getPacket();
virtual PacketPtr getPacket();
/**
* Was the request was sent successfully?
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
/**
* Was the CSHR request was sent successfully?
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The request being responded to.
*/
void handleResponse(Packet * &pkt);
void handleResponse(PacketPtr &pkt);
/**
* Selects a coherence message to forward to lower levels of the hierarchy.
* @return The coherence message to forward.
*/
virtual Packet * getCoherencePacket();
virtual PacketPtr getCoherencePacket();
/**
* Snoops bus transactions to maintain coherence.
* @param pkt The current bus transaction.
*/
void snoop(Packet * &pkt);
void snoop(PacketPtr &pkt);
void snoopResponse(Packet * &pkt);
void snoopResponse(PacketPtr &pkt);
/**
* Invalidates the block containing address if found.
@ -224,7 +224,7 @@ class Cache : public BaseCache
* request.
* @return The estimated completion time.
*/
Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
/**
* Snoop for the provided request in the cache and return the estimated
@ -235,7 +235,7 @@ class Cache : public BaseCache
* request.
* @return The estimated completion time.
*/
Tick snoopProbe(Packet * &pkt);
Tick snoopProbe(PacketPtr &pkt);
};
#endif // __CACHE_HH__

30
src/mem/cache/cache_impl.hh vendored
View file

@ -56,7 +56,7 @@
template<class TagStore, class Buffering, class Coherence>
bool
Cache<TagStore,Buffering,Coherence>::
doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
{
if (isCpuSide)
{
@ -82,7 +82,7 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
template<class TagStore, class Buffering, class Coherence>
Tick
Cache<TagStore,Buffering,Coherence>::
doAtomicAccess(Packet *pkt, bool isCpuSide)
doAtomicAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
{
@ -104,7 +104,7 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::
doFunctionalAccess(Packet *pkt, bool isCpuSide)
doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
{
@ -238,11 +238,11 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
template<class TagStore, class Buffering, class Coherence>
Packet *
PacketPtr
Cache<TagStore,Buffering,Coherence>::getPacket()
{
assert(missQueue->havePending());
Packet * pkt = missQueue->getPacket();
PacketPtr pkt = missQueue->getPacket();
if (pkt) {
if (!pkt->req->isUncacheable()) {
if (pkt->cmd == Packet::HardPFReq)
@ -306,7 +306,7 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
{
BlkType *blk = NULL;
if (pkt->senderState) {
@ -348,7 +348,7 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
}
template<class TagStore, class Buffering, class Coherence>
Packet *
PacketPtr
Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
{
return coherence->getPacket();
@ -356,7 +356,7 @@ Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
MSHR *cshr,
bool success)
{
@ -366,7 +366,7 @@ Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
{
if (pkt->req->isUncacheable()) {
//Can't get a hit on an uncacheable address
@ -485,7 +485,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
{
//Need to handle the response, if NACKED
if (pkt->flags & NACKED_LINE) {
@ -515,7 +515,7 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
*/
template<class TagStore, class Buffering, class Coherence>
Tick
Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
CachePort* otherSidePort)
{
// MemDebug::cacheProbe(pkt);
@ -565,7 +565,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
MSHR::TargetList::iterator i = targets->begin();
MSHR::TargetList::iterator end = targets->end();
for (; i != end; ++i) {
Packet * target = *i;
PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->isWrite() && target->intersect(pkt)) {
@ -601,7 +601,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
}
}
for (int i = 0; i < writes.size(); ++i) {
Packet * write = writes[i]->pkt;
PacketPtr write = writes[i]->pkt;
if (write->intersect(pkt)) {
warn("Found outstanding write on an non-update probe");
uint8_t* pkt_data;
@ -654,7 +654,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
(blk)? blk->status : 0);
Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
busPkt->allocate();
@ -700,7 +700,7 @@ return 0;
// Handle writebacks if needed
while (!writebacks.empty()){
Packet *wbPkt = writebacks.front();
PacketPtr wbPkt = writebacks.front();
memSidePort->sendAtomic(wbPkt);
writebacks.pop_front();
delete wbPkt;

20
src/mem/cache/coherence/coherence_protocol.cc vendored
View file

@ -192,7 +192,7 @@ CoherenceProtocol::regStats()
bool
CoherenceProtocol::invalidateTrans(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::invalidateTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk, MSHR *mshr,
CacheBlk::State & new_state)
{
@ -203,7 +203,7 @@ CoherenceProtocol::invalidateTrans(BaseCache *cache, Packet * &pkt,
bool
CoherenceProtocol::supplyTrans(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::supplyTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state
@ -214,7 +214,7 @@ CoherenceProtocol::supplyTrans(BaseCache *cache, Packet * &pkt,
bool
CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
@ -226,7 +226,7 @@ CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, Packet * &pkt,
bool
CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
@ -238,7 +238,7 @@ CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, Packet * &pkt,
bool
CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
@ -248,7 +248,7 @@ CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, Packet * &pkt,
}
bool
CoherenceProtocol::assertShared(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::assertShared(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
@ -463,7 +463,7 @@ CoherenceProtocol::getBusCmd(Packet::Command cmdIn, CacheBlk::State state,
CacheBlk::State
CoherenceProtocol::getNewState(Packet * &pkt, CacheBlk::State oldState)
CoherenceProtocol::getNewState(PacketPtr &pkt, CacheBlk::State oldState)
{
CacheBlk::State state = oldState & stateMask;
int cmd_idx = pkt->cmdToIndex();
@ -488,7 +488,7 @@ CoherenceProtocol::getNewState(Packet * &pkt, CacheBlk::State oldState)
bool
CoherenceProtocol::handleBusRequest(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::handleBusRequest(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
@ -518,7 +518,7 @@ CoherenceProtocol::handleBusRequest(BaseCache *cache, Packet * &pkt,
}
bool
CoherenceProtocol::nullTransition(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::nullTransition(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk, MSHR *mshr,
CacheBlk::State & new_state)
{
@ -530,7 +530,7 @@ CoherenceProtocol::nullTransition(BaseCache *cache, Packet * &pkt,
bool
CoherenceProtocol::invalidTransition(BaseCache *cache, Packet * &pkt,
CoherenceProtocol::invalidTransition(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk, MSHR *mshr,
CacheBlk::State & new_state)
{

22
src/mem/cache/coherence/coherence_protocol.hh vendored
View file

@ -89,7 +89,7 @@ class CoherenceProtocol : public SimObject
* @param oldState The current block state.
* @return The new state.
*/
CacheBlk::State getNewState(Packet * &pkt,
CacheBlk::State getNewState(PacketPtr &pkt,
CacheBlk::State oldState);
/**
@ -101,12 +101,12 @@ class CoherenceProtocol : public SimObject
* @param new_state The new coherence state of the block.
* @return True if the request should be satisfied locally.
*/
bool handleBusRequest(BaseCache *cache, Packet * &pkt, CacheBlk *blk,
bool handleBusRequest(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk,
MSHR *mshr, CacheBlk::State &new_state);
protected:
/** Snoop function type. */
typedef bool (*SnoopFuncType)(BaseCache *, Packet *&, CacheBlk *,
typedef bool (*SnoopFuncType)(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
//
@ -116,49 +116,49 @@ class CoherenceProtocol : public SimObject
/**
* Do nothing transition.
*/
static bool nullTransition(BaseCache *, Packet *&, CacheBlk *,
static bool nullTransition(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Invalid transition, basically panic.
*/
static bool invalidTransition(BaseCache *, Packet *&, CacheBlk *,
static bool invalidTransition(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Invalidate block, move to Invalid state.
*/
static bool invalidateTrans(BaseCache *, Packet *&, CacheBlk *,
static bool invalidateTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Supply data, no state transition.
*/
static bool supplyTrans(BaseCache *, Packet *&, CacheBlk *,
static bool supplyTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Supply data and go to Shared state.
*/
static bool supplyAndGotoSharedTrans(BaseCache *, Packet *&, CacheBlk *,
static bool supplyAndGotoSharedTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Supply data and go to Owned state.
*/
static bool supplyAndGotoOwnedTrans(BaseCache *, Packet *&, CacheBlk *,
static bool supplyAndGotoOwnedTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Invalidate block, supply data, and go to Invalid state.
*/
static bool supplyAndInvalidateTrans(BaseCache *, Packet *&, CacheBlk *,
static bool supplyAndInvalidateTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Assert the shared line for a block that is shared/exclusive.
*/
static bool assertShared(BaseCache *, Packet *&, CacheBlk *,
static bool assertShared(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**

10
src/mem/cache/coherence/simple_coherence.hh vendored
View file

@ -89,7 +89,7 @@ class SimpleCoherence
* This policy does not forward invalidates, return NULL.
* @return NULL.
*/
Packet * getPacket()
PacketPtr getPacket()
{
return NULL;
}
@ -99,7 +99,7 @@ class SimpleCoherence
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
void sendResult(Packet * &pkt, MSHR* cshr, bool success)
void sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
{
//Don't do coherence
return;
@ -112,7 +112,7 @@ class SimpleCoherence
* @param current The current block state.
* @return The new state.
*/
CacheBlk::State getNewState(Packet * &pkt, CacheBlk::State current)
CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State current)
{
return protocol->getNewState(pkt, current);
}
@ -124,7 +124,7 @@ class SimpleCoherence
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state Return the new state for the block.
*/
bool handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
bool handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
CacheBlk::State &new_state)
{
// assert(mshr == NULL);
@ -161,7 +161,7 @@ class SimpleCoherence
bool hasProtocol() { return true; }
void propogateInvalidate(Packet *pkt, bool isTiming)
void propogateInvalidate(PacketPtr pkt, bool isTiming)
{
//For now we do nothing, asssumes simple coherence is top level of cache
return;

14
src/mem/cache/coherence/uni_coherence.cc vendored
View file

@ -40,15 +40,15 @@ UniCoherence::UniCoherence()
{
}
Packet *
PacketPtr
UniCoherence::getPacket()
{
Packet* pkt = cshrs.getReq();
PacketPtr pkt = cshrs.getReq();
return pkt;
}
void
UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success)
UniCoherence::sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
{
if (success)
{
@ -71,7 +71,7 @@ UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success)
* @todo add support for returning slave requests, not doing them here.
*/
bool
UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
CacheBlk::State &new_state)
{
new_state = 0;
@ -86,19 +86,19 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
}
void
UniCoherence::propogateInvalidate(Packet *pkt, bool isTiming)
UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
{
if (pkt->isInvalidate()) {
if (isTiming) {
// Forward to other caches
Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
cshrs.allocate(tmp);
cache->setSlaveRequest(Request_Coherence, curTick);
if (cshrs.isFull())
cache->setBlockedForSnoop(Blocked_Coherence);
}
else {
Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
cache->cpuSidePort->sendAtomic(tmp);
delete tmp;
}

10
src/mem/cache/coherence/uni_coherence.hh vendored
View file

@ -92,7 +92,7 @@ class UniCoherence
* @param current The current block state.
* @return The new state.
*/
CacheBlk::State getNewState(Packet * &pkt, CacheBlk::State current)
CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State current)
{
if (pkt->senderState) //Blocking Buffers don't get mshrs
{
@ -113,14 +113,14 @@ class UniCoherence
* Return outstanding invalidate to forward.
* @return The next invalidate to forward to lower levels of cache.
*/
Packet * getPacket();
PacketPtr getPacket();
/**
* Was the CSHR request was sent successfully?
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
void sendResult(Packet * &pkt, MSHR* cshr, bool success);
void sendResult(PacketPtr &pkt, MSHR* cshr, bool success);
/**
* Handle snooped bus requests.
@ -130,7 +130,7 @@ class UniCoherence
* @param new_state The new coherence state of the block.
* @return True if the request should be satisfied locally.
*/
bool handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
bool handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
CacheBlk::State &new_state);
/**
@ -140,7 +140,7 @@ class UniCoherence
bool hasProtocol() { return false; }
void propogateInvalidate(Packet *pkt, bool isTiming);
void propogateInvalidate(PacketPtr pkt, bool isTiming);
};
#endif //__UNI_COHERENCE_HH__

20
src/mem/cache/miss/blocking_buffer.cc vendored
View file

@ -68,7 +68,7 @@ BlockingBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
prefetcher = _prefetcher;
}
void
BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time)
{
Addr blk_addr = pkt->getAddr() & ~(Addr)(blk_size - 1);
if (pkt->isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
@ -98,7 +98,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
cache->setMasterRequest(Request_MSHR, time);
}
Packet *
PacketPtr
BlockingBuffer::getPacket()
{
if (miss.pkt && !miss.inService) {
@ -108,7 +108,7 @@ BlockingBuffer::getPacket()
}
void
BlockingBuffer::setBusCmd(Packet * &pkt, Packet::Command cmd)
BlockingBuffer::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
{
MSHR *mshr = (MSHR*) pkt->senderState;
mshr->originalCmd = pkt->cmd;
@ -117,13 +117,13 @@ BlockingBuffer::setBusCmd(Packet * &pkt, Packet::Command cmd)
}
void
BlockingBuffer::restoreOrigCmd(Packet * &pkt)
BlockingBuffer::restoreOrigCmd(PacketPtr &pkt)
{
pkt->cmdOverride(((MSHR*)(pkt->senderState))->originalCmd);
}
void
BlockingBuffer::markInService(Packet * &pkt, MSHR* mshr)
BlockingBuffer::markInService(PacketPtr &pkt, MSHR* mshr)
{
if (!pkt->isCacheFill() && pkt->isWrite()) {
// Forwarding a write/ writeback, don't need to change
@ -152,7 +152,7 @@ BlockingBuffer::markInService(Packet * &pkt, MSHR* mshr)
}
void
BlockingBuffer::handleResponse(Packet * &pkt, Tick time)
BlockingBuffer::handleResponse(PacketPtr &pkt, Tick time)
{
if (pkt->isCacheFill()) {
// targets were handled in the cache tags
@ -163,7 +163,7 @@ BlockingBuffer::handleResponse(Packet * &pkt, Tick time)
if (((MSHR*)(pkt->senderState))->hasTargets()) {
// Should only have 1 target if we had any
assert(((MSHR*)(pkt->senderState))->getNumTargets() == 1);
Packet * target = ((MSHR*)(pkt->senderState))->getTarget();
PacketPtr target = ((MSHR*)(pkt->senderState))->getTarget();
((MSHR*)(pkt->senderState))->popTarget();
if (pkt->isRead()) {
memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), target->getSize());
@ -187,7 +187,7 @@ void
BlockingBuffer::squash(int threadNum)
{
if (miss.threadNum == threadNum) {
Packet * target = miss.getTarget();
PacketPtr target = miss.getTarget();
miss.popTarget();
assert(0/*target->req->getThreadNum()*/ == threadNum);
target = NULL;
@ -207,7 +207,7 @@ BlockingBuffer::doWriteback(Addr addr,
{
// Generate request
Request * req = new Request(addr, size, 0);
Packet * pkt = new Packet(req, Packet::Writeback, -1);
PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
pkt->allocate();
if (data) {
memcpy(pkt->getPtr<uint8_t>(), data, size);
@ -228,7 +228,7 @@ BlockingBuffer::doWriteback(Addr addr,
void
BlockingBuffer::doWriteback(Packet * &pkt)
BlockingBuffer::doWriteback(PacketPtr &pkt)
{
writebacks[0/*pkt->req->getThreadNum()*/]++;

18
src/mem/cache/miss/blocking_buffer.hh vendored
View file

@ -111,7 +111,7 @@ public:
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
void handleMiss(Packet * &pkt, int blk_size, Tick time);
void handleMiss(PacketPtr &pkt, int blk_size, Tick time);
/**
* Fetch the block for the given address and buffer the given target.
@ -122,7 +122,7 @@ public:
* @param target The target for the fetch.
*/
MSHR* fetchBlock(Addr addr, int blk_size, Tick time,
Packet * &target)
PacketPtr &target)
{
fatal("Unimplemented");
}
@ -131,20 +131,20 @@ public:
* Selects a outstanding pktuest to service.
* @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
PacketPtr getPacket();
/**
* Set the command to the given bus command.
* @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
* @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
void restoreOrigCmd(PacketPtr &pkt);
/**
* Marks a pktuest as in service (sent on the bus). This can have side
@ -152,14 +152,14 @@ public:
* are successfully sent.
* @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt, MSHR* mshr);
void markInService(PacketPtr &pkt, MSHR* mshr);
/**
* Frees the resources of the pktuest and unblock the cache.
* @param pkt The request that has been satisfied.
* @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
void handleResponse(PacketPtr &pkt, Tick time);
/**
* Removes all outstanding pktuests for a given thread number. If a request
@ -223,7 +223,7 @@ public:
* Perform a writeback pktuest.
* @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
void doWriteback(PacketPtr &pkt);
/**
* Returns true if there are outstanding pktuests.
@ -239,7 +239,7 @@ public:
* @param mshr The mshr to add a target to.
* @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
void addTarget(MSHR *mshr, PacketPtr &pkt)
{
fatal("Shouldn't call this on a blocking buffer.");
}

28
src/mem/cache/miss/miss_queue.cc vendored
View file

@ -350,7 +350,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
}
MSHR*
MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time)
{
MSHR* mshr = mq.allocate(pkt, size);
mshr->order = order++;
@ -370,7 +370,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
MSHR*
MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
MissQueue::allocateWrite(PacketPtr &pkt, int size, Tick time)
{
MSHR* mshr = wb.allocate(pkt,size);
mshr->order = order++;
@ -401,7 +401,7 @@ MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
* @todo Remove SW prefetches on mshr hits.
*/
void
MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
MissQueue::handleMiss(PacketPtr &pkt, int blkSize, Tick time)
{
// if (!cache->isTopLevel())
if (prefetchMiss) prefetcher->handleMiss(pkt, time);
@ -455,7 +455,7 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
MSHR*
MissQueue::fetchBlock(Addr addr, int blk_size, Tick time,
Packet * &target)
PacketPtr &target)
{
Addr blkAddr = addr & ~(Addr)(blk_size - 1);
assert(mq.findMatch(addr) == NULL);
@ -469,10 +469,10 @@ MissQueue::fetchBlock(Addr addr, int blk_size, Tick time,
return mshr;
}
Packet *
PacketPtr
MissQueue::getPacket()
{
Packet * pkt = mq.getReq();
PacketPtr pkt = mq.getReq();
if (((wb.isFull() && wb.inServiceMSHRs == 0) || !pkt ||
pkt->time > curTick) && wb.havePending()) {
pkt = wb.getReq();
@ -510,7 +510,7 @@ MissQueue::getPacket()
}
void
MissQueue::setBusCmd(Packet * &pkt, Packet::Command cmd)
MissQueue::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
{
assert(pkt->senderState != 0);
MSHR * mshr = (MSHR*)pkt->senderState;
@ -528,13 +528,13 @@ MissQueue::setBusCmd(Packet * &pkt, Packet::Command cmd)
}
void
MissQueue::restoreOrigCmd(Packet * &pkt)
MissQueue::restoreOrigCmd(PacketPtr &pkt)
{
pkt->cmd = ((MSHR*)(pkt->senderState))->originalCmd;
}
void
MissQueue::markInService(Packet * &pkt, MSHR* mshr)
MissQueue::markInService(PacketPtr &pkt, MSHR* mshr)
{
bool unblock = false;
BlockedCause cause = NUM_BLOCKED_CAUSES;
@ -583,7 +583,7 @@ MissQueue::markInService(Packet * &pkt, MSHR* mshr)
void
MissQueue::handleResponse(Packet * &pkt, Tick time)
MissQueue::handleResponse(PacketPtr &pkt, Tick time)
{
MSHR* mshr = (MSHR*)pkt->senderState;
if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
@ -632,7 +632,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
if (mshr->hasTargets() && pkt->req->isUncacheable()) {
// Should only have 1 target if we had any
assert(num_targets == 1);
Packet * target = mshr->getTarget();
PacketPtr target = mshr->getTarget();
mshr->popTarget();
if (pkt->isRead()) {
memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(),
@ -645,7 +645,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
//Must be a no_allocate with possibly more than one target
assert(mshr->pkt->isNoAllocate());
while (mshr->hasTargets()) {
Packet * target = mshr->getTarget();
PacketPtr target = mshr->getTarget();
mshr->popTarget();
if (pkt->isRead()) {
memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(),
@ -721,7 +721,7 @@ MissQueue::doWriteback(Addr addr,
{
// Generate request
Request * req = new Request(addr, size, 0);
Packet * pkt = new Packet(req, Packet::Writeback, -1);
PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
pkt->allocate();
if (data) {
memcpy(pkt->getPtr<uint8_t>(), data, size);
@ -739,7 +739,7 @@ MissQueue::doWriteback(Addr addr,
void
MissQueue::doWriteback(Packet * &pkt)
MissQueue::doWriteback(PacketPtr &pkt)
{
writebacks[0/*pkt->req->getThreadNum()*/]++;
allocateWrite(pkt, 0, curTick);

22
src/mem/cache/miss/miss_queue.hh vendored
View file

@ -169,7 +169,7 @@ class MissQueue
* @param time The time the miss occurs.
* @return A pointer to the new MSHR.
*/
MSHR* allocateMiss(Packet * &pkt, int size, Tick time);
MSHR* allocateMiss(PacketPtr &pkt, int size, Tick time);
/**
* Allocate a new WriteBuffer to handle the provided write.
@ -178,7 +178,7 @@ class MissQueue
* @param time The time the write occurs.
* @return A pointer to the new write buffer.
*/
MSHR* allocateWrite(Packet * &pkt, int size, Tick time);
MSHR* allocateWrite(PacketPtr &pkt, int size, Tick time);
public:
/**
@ -218,7 +218,7 @@ class MissQueue
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
void handleMiss(Packet * &pkt, int blk_size, Tick time);
void handleMiss(PacketPtr &pkt, int blk_size, Tick time);
/**
* Fetch the block for the given address and buffer the given target.
@ -229,26 +229,26 @@ class MissQueue
* @param target The target for the fetch.
*/
MSHR* fetchBlock(Addr addr, int blk_size, Tick time,
Packet * &target);
PacketPtr &target);
/**
* Selects a outstanding pktuest to service.
* @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
PacketPtr getPacket();
/**
* Set the command to the given bus command.
* @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
* @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
void restoreOrigCmd(PacketPtr &pkt);
/**
* Marks a pktuest as in service (sent on the bus). This can have side
@ -256,14 +256,14 @@ class MissQueue
* are successfully sent.
* @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt, MSHR* mshr);
void markInService(PacketPtr &pkt, MSHR* mshr);
/**
* Collect statistics and free resources of a satisfied pktuest.
* @param pkt The request that has been satisfied.
* @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
void handleResponse(PacketPtr &pkt, Tick time);
/**
* Removes all outstanding pktuests for a given thread number. If a request
@ -316,7 +316,7 @@ class MissQueue
* Perform the given writeback pktuest.
* @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
void doWriteback(PacketPtr &pkt);
/**
* Returns true if there are outstanding pktuests.
@ -329,7 +329,7 @@ class MissQueue
* @param mshr The mshr to add a target to.
* @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
void addTarget(MSHR *mshr, PacketPtr &pkt)
{
mq.allocateTarget(mshr, pkt);
}

8
src/mem/cache/miss/mshr.cc vendored
View file

@ -55,7 +55,7 @@ MSHR::MSHR()
void
MSHR::allocate(Packet::Command cmd, Addr _addr, int size,
Packet * &target)
PacketPtr &target)
{
addr = _addr;
if (target)
@ -85,7 +85,7 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int size,
* @todo When we have a "global" data flag, might want to copy data here.
*/
void
MSHR::allocateAsBuffer(Packet * &target)
MSHR::allocateAsBuffer(PacketPtr &target)
{
addr = target->getAddr();
threadNum = 0/*target->req->getThreadNum()*/;
@ -111,13 +111,13 @@ MSHR::deallocate()
* Adds a target to an MSHR
*/
void
MSHR::allocateTarget(Packet * &target)
MSHR::allocateTarget(PacketPtr &target)
{
//If we append an invalidate and we issued a read to the bus,
//but now have some pending writes, we need to move
//the invalidate to before the first non-read
if (inService && pkt->isRead() && target->isInvalidate()) {
std::list<Packet *> temp;
std::list<PacketPtr> temp;
while (!targets.empty()) {
if (!targets.front()->isRead()) break;

14
src/mem/cache/miss/mshr.hh vendored
View file

@ -49,9 +49,9 @@ class MSHR;
class MSHR {
public:
/** Defines the Data structure of the MSHR targetlist. */
typedef std::list<Packet *> TargetList;
typedef std::list<PacketPtr> TargetList;
/** Target list iterator. */
typedef std::list<Packet *>::iterator TargetListIterator;
typedef std::list<PacketPtr>::iterator TargetListIterator;
/** A list of MSHRs. */
typedef std::list<MSHR *> List;
/** MSHR list iterator. */
@ -68,7 +68,7 @@ class MSHR {
/** Thread number of the miss. */
int threadNum;
/** The pktuest that is forwarded to the next level of the hierarchy. */
Packet * pkt;
PacketPtr pkt;
/** The number of currently allocated targets. */
short ntargets;
/** The original pktuesting command. */
@ -101,13 +101,13 @@ public:
* @param pkt The original miss.
*/
void allocate(Packet::Command cmd, Addr addr, int size,
Packet * &pkt);
PacketPtr &pkt);
/**
* Allocate this MSHR as a buffer for the given pktuest.
* @param target The memory pktuest to buffer.
*/
void allocateAsBuffer(Packet * &target);
void allocateAsBuffer(PacketPtr &target);
/**
* Mark this MSHR as free.
@ -118,7 +118,7 @@ public:
* Add a pktuest to the list of targets.
* @param target The target.
*/
void allocateTarget(Packet * &target);
void allocateTarget(PacketPtr &target);
/** A simple constructor. */
MSHR();
@ -147,7 +147,7 @@ public:
* Returns a reference to the first target.
* @return A pointer to the first target.
*/
Packet * getTarget()
PacketPtr getTarget()
{
return targets.front();
}

10
src/mem/cache/miss/mshr_queue.cc vendored
View file

@ -88,7 +88,7 @@ MSHRQueue::findMatches(Addr addr, vector<MSHR*>& matches) const
}
MSHR*
MSHRQueue::findPending(Packet * &pkt) const
MSHRQueue::findPending(PacketPtr &pkt) const
{
MSHR::ConstIterator i = pendingList.begin();
MSHR::ConstIterator end = pendingList.end();
@ -108,7 +108,7 @@ MSHRQueue::findPending(Packet * &pkt) const
}
MSHR*
MSHRQueue::allocate(Packet * &pkt, int size)
MSHRQueue::allocate(PacketPtr &pkt, int size)
{
Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1);
assert(!freeList.empty());
@ -131,7 +131,7 @@ MSHRQueue::allocate(Packet * &pkt, int size)
}
MSHR*
MSHRQueue::allocateFetch(Addr addr, int size, Packet * &target)
MSHRQueue::allocateFetch(Addr addr, int size, PacketPtr &target)
{
MSHR *mshr = freeList.front();
assert(mshr->getNumTargets() == 0);
@ -150,7 +150,7 @@ MSHRQueue::allocateTargetList(Addr addr, int size)
MSHR *mshr = freeList.front();
assert(mshr->getNumTargets() == 0);
freeList.pop_front();
Packet * dummy;
PacketPtr dummy;
mshr->allocate(Packet::ReadReq, addr, size, dummy);
mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
mshr->inService = true;
@ -237,7 +237,7 @@ MSHRQueue::squash(int threadNum)
MSHR *mshr = *i;
if (mshr->threadNum == threadNum) {
while (mshr->hasTargets()) {
Packet * target = mshr->getTarget();
PacketPtr target = mshr->getTarget();
mshr->popTarget();
assert(0/*target->req->getThreadNum()*/ == threadNum);

10
src/mem/cache/miss/mshr_queue.hh vendored
View file

@ -107,7 +107,7 @@ class MSHRQueue {
* @param pkt The request to find.
* @return A pointer to the earliest matching MSHR.
*/
MSHR* findPending(Packet * &pkt) const;
MSHR* findPending(PacketPtr &pkt) const;
/**
* Allocates a new MSHR for the pktuest and size. This places the request
@ -118,7 +118,7 @@ class MSHRQueue {
*
* @pre There are free MSHRs.
*/
MSHR* allocate(Packet * &pkt, int size = 0);
MSHR* allocate(PacketPtr &pkt, int size = 0);
/**
* Allocate a read pktuest for the given address, and places the given
@ -129,7 +129,7 @@ class MSHRQueue {
* @param target The first target for the pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateFetch(Addr addr, int size, Packet * &target);
MSHR* allocateFetch(Addr addr, int size, PacketPtr &target);
/**
* Allocate a target list for the given address.
@ -153,7 +153,7 @@ class MSHRQueue {
* @param mshr The MSHR to allocate the target to.
* @param pkt The target request.
*/
void allocateTarget(MSHR* mshr, Packet * &pkt)
void allocateTarget(MSHR* mshr, PacketPtr &pkt)
{
mshr->allocateTarget(pkt);
allocatedTargets += 1;
@ -216,7 +216,7 @@ class MSHRQueue {
* Returns the pktuest at the head of the pendingList.
* @return The next pktuest to service.
*/
Packet * getReq() const
PacketPtr getReq() const
{
if (pendingList.empty()) {
return NULL;

14
src/mem/cache/prefetch/base_prefetcher.cc vendored
View file

@ -102,7 +102,7 @@ BasePrefetcher::regStats(const std::string &name)
;
}
Packet *
PacketPtr
BasePrefetcher::getPacket()
{
DPRINTF(HWPrefetch, "%s:Requesting a hw_pf to issue\n", cache->name());
@ -112,7 +112,7 @@ BasePrefetcher::getPacket()
return NULL;
}
Packet * pkt;
PacketPtr pkt;
bool keepTrying = false;
do {
pkt = *pf.begin();
@ -131,7 +131,7 @@ BasePrefetcher::getPacket()
}
void
BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time)
{
if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && only_data))
{
@ -139,7 +139,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
//Check if miss is in pfq, if so remove it
std::list<Packet *>::iterator iter = inPrefetch(blkAddr);
std::list<PacketPtr>::iterator iter = inPrefetch(blkAddr);
if (iter != pf.end()) {
DPRINTF(HWPrefetch, "%s:Saw a miss to a queued prefetch, removing it\n", cache->name());
pfRemovedMSHR++;
@ -179,7 +179,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
pfIdentified++;
//create a prefetch memreq
Request * prefetchReq = new Request(*addr, blkSize, 0);
Packet * prefetch;
PacketPtr prefetch;
prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
prefetch->allocate();
prefetch->req->setThreadContext(pkt->req->getCpuNum(),
@ -233,11 +233,11 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
}
}
std::list<Packet *>::iterator
std::list<PacketPtr>::iterator
BasePrefetcher::inPrefetch(Addr address)
{
//Guaranteed to only be one match, we always check before inserting
std::list<Packet *>::iterator iter;
std::list<PacketPtr>::iterator iter;
for (iter=pf.begin(); iter != pf.end(); iter++) {
if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) {
return iter;

12
src/mem/cache/prefetch/base_prefetcher.hh vendored
View file

@ -45,7 +45,7 @@ class BasePrefetcher
protected:
/** The Prefetch Queue. */
std::list<Packet *> pf;
std::list<PacketPtr> pf;
// PARAMETERS
@ -93,24 +93,24 @@ class BasePrefetcher
void setCache(BaseCache *_cache);
void handleMiss(Packet * &pkt, Tick time);
void handleMiss(PacketPtr &pkt, Tick time);
Packet * getPacket();
PacketPtr getPacket();
bool havePending()
{
return !pf.empty();
}
virtual void calculatePrefetch(Packet * &pkt,
virtual void calculatePrefetch(PacketPtr &pkt,
std::list<Addr> &addresses,
std::list<Tick> &delays) = 0;
virtual bool inCache(Packet * &pkt) = 0;
virtual bool inCache(PacketPtr &pkt) = 0;
virtual bool inMissQueue(Addr address) = 0;
std::list<Packet *>::iterator inPrefetch(Addr address);
std::list<PacketPtr>::iterator inPrefetch(Addr address);
};

2
src/mem/cache/prefetch/ghb_prefetcher.hh vendored
View file

@ -75,7 +75,7 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
~GHBPrefetcher() {}
void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses,
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);

2
src/mem/cache/prefetch/stride_prefetcher.hh vendored
View file

@ -92,7 +92,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering>
~StridePrefetcher() {}
void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses,
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);

2
src/mem/cache/prefetch/tagged_prefetcher.hh vendored
View file

@ -64,7 +64,7 @@ class TaggedPrefetcher : public Prefetcher<TagStore, Buffering>
~TaggedPrefetcher() {}
void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses,
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays);
};

2
src/mem/cache/prefetch/tagged_prefetcher_impl.hh vendored
View file

@ -50,7 +50,7 @@ TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
template <class TagStore, class Buffering>
void
TaggedPrefetcher<TagStore, Buffering>::
calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses,
calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);

4
src/mem/cache/tags/fa_lru.cc vendored
View file

@ -203,7 +203,7 @@ FALRU::findBlock(Addr addr, int &lat, int *inCache)
}
FALRUBlk*
FALRU::findBlock(Packet * &pkt, int &lat, int *inCache)
FALRU::findBlock(PacketPtr &pkt, int &lat, int *inCache)
{
Addr addr = pkt->getAddr();
@ -256,7 +256,7 @@ FALRU::findBlock(Addr addr) const
}
FALRUBlk*
FALRU::findReplacement(Packet * &pkt, PacketList &writebacks,
FALRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
FALRUBlk * blk = tail;

4
src/mem/cache/tags/fa_lru.hh vendored
View file

@ -198,7 +198,7 @@ public:
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
*/
FALRUBlk* findBlock(Packet * &pkt, int &lat, int *inCache = 0);
FALRUBlk* findBlock(PacketPtr &pkt, int &lat, int *inCache = 0);
/**
* Find the block in the cache, do not update the replacement data.
@ -215,7 +215,7 @@ public:
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
FALRUBlk* findReplacement(Packet * &pkt, PacketList & writebacks,
FALRUBlk* findReplacement(PacketPtr &pkt, PacketList & writebacks,
BlkList &compress_blocks);
/**

8
src/mem/cache/tags/iic.cc vendored
View file

@ -285,7 +285,7 @@ IIC::findBlock(Addr addr, int &lat)
}
IICTag*
IIC::findBlock(Packet * &pkt, int &lat)
IIC::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
@ -362,7 +362,7 @@ IIC::findBlock(Addr addr) const
IICTag*
IIC::findReplacement(Packet * &pkt, PacketList &writebacks,
IIC::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
DPRINTF(IIC, "Finding Replacement for %x\n", pkt->getAddr());
@ -423,7 +423,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
tag_ptr->refCount = 0;
if (tag_ptr->isModified()) {
/* Packet * writeback =
/* PacketPtr writeback =
buildWritebackReq(regenerateBlkAddr(tag_ptr->tag, 0),
tag_ptr->req->asid, tag_ptr->xc, blkSize,
tag_ptr->data,
@ -431,7 +431,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
*/
Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
blkSize, 0);
Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1);
writeback->allocate();
memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);

4
src/mem/cache/tags/iic.hh vendored
View file

@ -458,7 +458,7 @@ class IIC : public BaseTags
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
IICTag* findBlock(Packet * &pkt, int &lat);
IICTag* findBlock(PacketPtr &pkt, int &lat);
/**
* Find the block, do not update the replacement data.
@ -475,7 +475,7 @@ class IIC : public BaseTags
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
IICTag* findReplacement(Packet * &pkt, PacketList &writebacks,
IICTag* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**

4
src/mem/cache/tags/lru.cc vendored
View file

@ -184,7 +184,7 @@ LRU::findBlock(Addr addr, int &lat)
}
LRUBlk*
LRU::findBlock(Packet * &pkt, int &lat)
LRU::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
@ -215,7 +215,7 @@ LRU::findBlock(Addr addr) const
}
LRUBlk*
LRU::findReplacement(Packet * &pkt, PacketList &writebacks,
LRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
unsigned set = extractSet(pkt->getAddr());

4
src/mem/cache/tags/lru.hh vendored
View file

@ -174,7 +174,7 @@ public:
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
LRUBlk* findBlock(Packet * &pkt, int &lat);
LRUBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache and update replacement data.
@ -201,7 +201,7 @@ public:
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
LRUBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
LRUBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**

4
src/mem/cache/tags/split.cc vendored
View file

@ -267,7 +267,7 @@ Split::probe(Addr addr) const
}
SplitBlk*
Split::findBlock(Packet * &pkt, int &lat)
Split::findBlock(PacketPtr &pkt, int &lat)
{
Addr aligned = blkAlign(pkt->getAddr());
@ -350,7 +350,7 @@ Split::findBlock(Addr addr) const
}
SplitBlk*
Split::findReplacement(Packet * &pkt, PacketList &writebacks,
Split::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
SplitBlk *blk;

4
src/mem/cache/tags/split.hh vendored
View file

@ -207,7 +207,7 @@ class Split : public BaseTags
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
SplitBlk* findBlock(Packet * &pkt, int &lat);
SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
@ -224,7 +224,7 @@ class Split : public BaseTags
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);

4
src/mem/cache/tags/split_lifo.cc vendored
View file

@ -255,7 +255,7 @@ SplitLIFO::findBlock(Addr addr, int &lat)
}
SplitBlk*
SplitLIFO::findBlock(Packet * &pkt, int &lat)
SplitLIFO::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
@ -291,7 +291,7 @@ SplitLIFO::findBlock(Addr addr) const
}
SplitBlk*
SplitLIFO::findReplacement(Packet * &pkt, PacketList &writebacks,
SplitLIFO::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
unsigned set = extractSet(pkt->getAddr());

4
src/mem/cache/tags/split_lifo.hh vendored
View file

@ -207,7 +207,7 @@ public:
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
SplitBlk* findBlock(Packet * &pkt, int &lat);
SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
@ -224,7 +224,7 @@ public:
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**

4
src/mem/cache/tags/split_lru.cc vendored
View file

@ -203,7 +203,7 @@ SplitLRU::findBlock(Addr addr, int &lat)
}
SplitBlk*
SplitLRU::findBlock(Packet * &pkt, int &lat)
SplitLRU::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
@ -234,7 +234,7 @@ SplitLRU::findBlock(Addr addr) const
}
SplitBlk*
SplitLRU::findReplacement(Packet * &pkt, PacketList &writebacks,
SplitLRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
unsigned set = extractSet(pkt->getAddr());

4
src/mem/cache/tags/split_lru.hh vendored
View file

@ -190,7 +190,7 @@ public:
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
SplitBlk* findBlock(Packet * &pkt, int &lat);
SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
@ -207,7 +207,7 @@ public:
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**

2
src/mem/dram.cc
View file

@ -359,7 +359,7 @@ DRAMMemory::regStats()
static char *mem_access_output=NULL;
/* latency of access [CPU cycles]*/
Tick
DRAMMemory::calculateLatency(Packet *pkt)
DRAMMemory::calculateLatency(PacketPtr pkt)
{
bool cmdIsRead = pkt->isRead();

2
src/mem/dram.hh
View file

@ -140,7 +140,7 @@ class DRAMMemory : public PhysicalMemory
protected:
Tick calculateLatency(Packet *pkt);
Tick calculateLatency(PacketPtr pkt);
int prechargeBanksAround(int bank);
public:

4
src/mem/packet.cc
View file

@ -133,7 +133,7 @@ Packet::allocate()
/** Do the packet modify the same addresses. */
bool
Packet::intersect(Packet *p)
Packet::intersect(PacketPtr p)
{
Addr s1 = getAddr();
Addr e1 = getAddr() + getSize() - 1;
@ -144,7 +144,7 @@ Packet::intersect(Packet *p)
}
bool
fixPacket(Packet *func, Packet *timing)
fixPacket(PacketPtr func, PacketPtr timing)
{
Addr funcStart = func->getAddr();
Addr funcEnd = func->getAddr() + func->getSize() - 1;

8
src/mem/packet.hh
View file

@ -46,7 +46,7 @@
#include "sim/root.hh"
struct Packet;
typedef Packet* PacketPtr;
typedef Packet *PacketPtr;
typedef uint8_t* PacketDataPtr;
typedef std::list<PacketPtr> PacketList;
@ -103,7 +103,7 @@ class Packet
/** Device address (e.g., bus ID) of the source of the
* transaction. The source is not responsible for setting this
* field; it is set implicitly by the interconnect when the
* packet * is first sent. */
* packet is first sent. */
short src;
/** Device address (e.g., bus ID) of the destination of the
@ -444,7 +444,7 @@ class Packet
void allocate();
/** Do the packet modify the same addresses. */
bool intersect(Packet *p);
bool intersect(PacketPtr p);
};
@ -453,7 +453,7 @@ class Packet
* in the timing packet. It returns if the functional packet should continue to
* traverse the memory hierarchy or not.
*/
bool fixPacket(Packet *func, Packet *timing);
bool fixPacket(PacketPtr func, PacketPtr timing);
std::ostream & operator<<(std::ostream &o, const Packet &p);

8
src/mem/physical.cc
View file

@ -101,7 +101,7 @@ PhysicalMemory::deviceBlockSize()
}
Tick
PhysicalMemory::calculateLatency(Packet *pkt)
PhysicalMemory::calculateLatency(PacketPtr pkt)
{
return lat;
}
@ -189,7 +189,7 @@ PhysicalMemory::checkLockedAddrList(Request *req)
}
void
PhysicalMemory::doFunctionalAccess(Packet *pkt)
PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
{
assert(pkt->getAddr() + pkt->getSize() <= params()->addrRange.size());
@ -277,14 +277,14 @@ PhysicalMemory::MemoryPort::deviceBlockSize()
}
Tick
PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt)
PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt)
{
memory->doFunctionalAccess(pkt);
return memory->calculateLatency(pkt);
}
void
PhysicalMemory::MemoryPort::recvFunctional(Packet *pkt)
PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt)
{
// Default implementation of SimpleTimingPort::recvFunctional()
// calls recvAtomic() and throws away the latency; we can save a

8
src/mem/physical.hh
View file

@ -57,9 +57,9 @@ class PhysicalMemory : public MemObject
protected:
virtual Tick recvAtomic(Packet *pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@ -172,8 +172,8 @@ class PhysicalMemory : public MemObject
unsigned int drain(Event *de);
protected:
void doFunctionalAccess(Packet *pkt);
virtual Tick calculateLatency(Packet *pkt);
void doFunctionalAccess(PacketPtr pkt);
virtual Tick calculateLatency(PacketPtr pkt);
void recvStatusChange(Port::Status status);
public:

18
src/mem/port.hh
View file

@ -128,13 +128,13 @@ class Port
* called by a peer port, never directly by any outside object. */
/** Called to recive a timing call from the peer port. */
virtual bool recvTiming(Packet *pkt) = 0;
virtual bool recvTiming(PacketPtr pkt) = 0;
/** Called to recive a atomic call from the peer port. */
virtual Tick recvAtomic(Packet *pkt) = 0;
virtual Tick recvAtomic(PacketPtr pkt) = 0;
/** Called to recive a functional call from the peer port. */
virtual void recvFunctional(Packet *pkt) = 0;
virtual void recvFunctional(PacketPtr pkt) = 0;
/** Called to recieve a status change from the peer port. */
virtual void recvStatusChange(Status status) = 0;
@ -172,14 +172,14 @@ class Port
case a cache has a higher priority request come in while waiting for
the bus to arbitrate.
*/
bool sendTiming(Packet *pkt) { return peer->recvTiming(pkt); }
bool sendTiming(PacketPtr pkt) { return peer->recvTiming(pkt); }
/** Function called by the associated device to send an atomic
* access, an access in which the data is moved and the state is
* updated in one cycle, without interleaving with other memory
* accesses. Returns estimated latency of access.
*/
Tick sendAtomic(Packet *pkt)
Tick sendAtomic(PacketPtr pkt)
{ return peer->recvAtomic(pkt); }
/** Function called by the associated device to send a functional access,
@ -187,7 +187,7 @@ class Port
memory system, without affecting the current state of any block or
moving the block.
*/
void sendFunctional(Packet *pkt)
void sendFunctional(PacketPtr pkt)
{ return peer->recvFunctional(pkt); }
/** Called by the associated device to send a status change to the device
@ -252,9 +252,9 @@ class FunctionalPort : public Port
{}
protected:
virtual bool recvTiming(Packet *pkt) { panic("FuncPort is UniDir"); }
virtual Tick recvAtomic(Packet *pkt) { panic("FuncPort is UniDir"); }
virtual void recvFunctional(Packet *pkt) { panic("FuncPort is UniDir"); }
virtual bool recvTiming(PacketPtr pkt) { panic("FuncPort is UniDir"); }
virtual Tick recvAtomic(PacketPtr pkt) { panic("FuncPort is UniDir"); }
virtual void recvFunctional(PacketPtr pkt) { panic("FuncPort is UniDir"); }
virtual void recvStatusChange(Status status) {}
public:

10
src/mem/tport.cc
View file

@ -31,15 +31,15 @@
#include "mem/tport.hh"
void
SimpleTimingPort::recvFunctional(Packet *pkt)
SimpleTimingPort::recvFunctional(PacketPtr pkt)
{
//First check queued events
std::list<Packet *>::iterator i = transmitList.begin();
std::list<Packet *>::iterator end = transmitList.end();
std::list<PacketPtr>::iterator i = transmitList.begin();
std::list<PacketPtr>::iterator end = transmitList.end();
bool cont = true;
while (i != end && cont) {
Packet * target = *i;
PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt))
@ -52,7 +52,7 @@ SimpleTimingPort::recvFunctional(Packet *pkt)
}
bool
SimpleTimingPort::recvTiming(Packet *pkt)
SimpleTimingPort::recvTiming(PacketPtr pkt)
{
// If the device is only a slave, it should only be sending
// responses, which should never get nacked. There used to be

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