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Author SHA1 Message Date
Gabe Black e157b1f52a ARM: Implement the swp and swpb instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 1884ed65bd ARM: Decode MRS and MSR for thumb. 2010-06-02 12:58:05 -05:00
Gabe Black ff3b21bc2b ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones. 2010-06-02 12:58:05 -05:00
Gabe Black f0811eb208 ARM: Define versions of MSR and MRS outside the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black f61bb9adb9 ARM: Hook up the push/pop versions of stm/ldm in thumb. 2010-06-02 12:58:05 -05:00
Gabe Black a76ab8e040 ARM: Hook SVC into the thumb decoder. 2010-06-02 12:58:05 -05:00
Gabe Black cbdebf852e ARM: Implement SVC (was SWI) outside of the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black 34032f97d6 ARM: Trigger system calls from the SupervisorCall invoke method. 
This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.
 2010-06-02 12:58:05 -05:00
Gabe Black 52460938cb ARM: Fix multiply operations. 
These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
 2010-06-02 12:58:05 -05:00
Gabe Black 4fb6fcd82d ARM: Decode the scalar saturating add/subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 30dd622622 ARM: Decode the parallel add and subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 62e8487d57 ARM: Implement signed saturating add and/or subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black a1253ec644 ARM: Implemented prefetch instructions/decoding (pli, pld, pldw). 2010-06-02 12:58:05 -05:00
Gabe Black 61b00d3224 ARM: Decode unconditional ARM instructions. 2010-06-02 12:58:04 -05:00
Gabe Black b6e2f5d33f ARM: Make sure ldm exception return writes back its base in the right mode. 
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
 2010-06-02 12:58:04 -05:00
Gabe Black 89060f1fd8 ARM: Rework how unrecognized/unimplemented instructions are handled. 
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
 2010-06-02 12:58:04 -05:00
Gabe Black aa45fafb2e ARM: Add support for "SUBS PC, LR and related instructions". 2010-06-02 12:58:04 -05:00
Gabe Black 2419903dc0 ARM: Make ldrs into the PC and ldm exception return do interworking branches. 2010-06-02 12:58:04 -05:00
Gabe Black 28227440a7 ARM: Align the PC when using it as the base for a load. 2010-06-02 12:58:04 -05:00
Gabe Black d63f748b53 ARM: Implement ADR as separate from ADD. 2010-06-02 12:58:04 -05:00
Gabe Black e92dc21fde ARM: Add support for interworking branch ALU instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 11c3361be4 ARM: Fix when the flag bits are updated for thumb. 2010-06-02 12:58:04 -05:00
Gabe Black 14d25fbad0 ARM: Don't rely on undefined behavior to get arithmetic right shift. 
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
 2010-06-02 12:58:04 -05:00
Gabe Black 05d880f7a1 ARM: Restrict the shift amount from a register to 8 bits. 
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
 2010-06-02 12:58:04 -05:00
Gabe Black 9ebaf8ecd5 ARM: Define the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 3f83094af2 ARM: Decode the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 647edea970 ARM: Fix the constant describing the number of floating point registers. 2010-06-02 12:58:04 -05:00
Gabe Black 2f3102f1ef ARM: Add templates for VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 739f23c64c ARM: Add base classes for VFP load/store multiple. 2010-06-02 12:58:04 -05:00
Gabe Black cb631d87c3 ARM: Add floating point load/store microops. 2010-06-02 12:58:04 -05:00
Gabe Black 3a11412c99 ARM: Add an fp version of one of the microop indexed registers. 2010-06-02 12:58:04 -05:00
Gabe Black d5aee75efe ARM: Move the mmap region to where Linux actually has it. 2010-06-02 12:58:04 -05:00
Gabe Black a8eb9d521c ARM: Eliminate the unused rhi and rlo operands. 2010-06-02 12:58:03 -05:00
Gabe Black b02c7f1bcd ARM: Move the macro mem constructor out of the isa desc. 
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
 2010-06-02 12:58:03 -05:00
Gabe Black 7b62e9ad71 ARM: Make macroops panic if executed directly. 
The macroop should never be executed, only it's microops will.
 2010-06-02 12:58:03 -05:00
Ali Saidi 8fadf2691d ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs. 2010-06-02 12:58:03 -05:00
Gabe Black f18040a205 ARM: Split out the "basic" templates and format. 
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
 2010-06-02 12:58:03 -05:00
Gabe Black c175f1b993 ARM: Remove unnecessary cruft from includes.isa. 2010-06-02 12:58:03 -05:00
Gabe Black e29ec7d2ed ARM: Move the inst2string function out of the isa_desc. 
Delete the now empty formats/util.isa.
 2010-06-02 12:58:03 -05:00
Gabe Black ae135228fc ARM: Get rid of the unused ArmGenericCodeSubs. 2010-06-02 12:58:03 -05:00
Gabe Black 8c012e9571 ARM: Make the predecoder print out the ExtMachInst it gathered when traced. 2010-06-02 12:58:03 -05:00
Gabe Black 458bd025d4 ARM: Remove special naming for the new version of multiply. 2010-06-02 12:58:03 -05:00
Gabe Black 2196f75a25 ARM: Hook the new multiply instructions into all the decoders. 2010-06-02 12:58:03 -05:00
Gabe Black 33da368e99 ARM: Implement all integer multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 50229be27f ARM: Add templates for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 3430b34cff ARM: Add base classes for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black c7d2f43641 ARM: Decode plain binary immediate thumb data processing instructions. 2010-06-02 12:58:03 -05:00
Gabe Black dcf218155d ARM: Define a new "movt" data processing instruction. 2010-06-02 12:58:03 -05:00
Gabe Black b615ed1470 ARM: Hook the new branch instructions into the 32 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black 274badd201 ARM: Hook the new branch instructions into the 16 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black b6b2f8891a ARM: Eliminate the old style branch instructions. 2010-06-02 12:58:03 -05:00
Gabe Black d082705b01 ARM: Hook the new branch instructions into the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black 9869343636 ARM: Implement branch instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black a6c1c8debb ARM: Add new templates for branch instructions. 2010-06-02 12:58:02 -05:00
Gabe Black ef3972eaae ARM: Implement new base classes for branches. 2010-06-02 12:58:02 -05:00
Gabe Black 769f3406fe ARM: Replace the interworking branch base class with a special operand. 2010-06-02 12:58:02 -05:00
Gabe Black b6e7029dd5 ARM: Fix PC operand handling. 2010-06-02 12:58:02 -05:00
Gabe Black 7eb3ea2798 ARM: Remove the special naming from the new version of data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 4f08b52af2 ARM: Get rid of unnecessary flag calculating functions. 2010-06-02 12:58:02 -05:00
Gabe Black bf903ec9a1 ARM: Get rid of the unused Jump format. 2010-06-02 12:58:02 -05:00
Gabe Black 36ca0658a4 ARM: Get rid of obsoleted predicated inst formats, etc. 2010-06-02 12:58:02 -05:00
Gabe Black 7939b48265 ARM: Implement disassembly for the new data processing classes. 2010-06-02 12:58:02 -05:00
Gabe Black b66e3aec43 ARM: Hook the external data processing instructions into the Thumb decoder. 2010-06-02 12:58:02 -05:00
Gabe Black beb759912b ARM: Move the modified_imm function from all ARM instructions to just data processing ones. 2010-06-02 12:58:02 -05:00
Gabe Black 8136cb3605 ARM: Hook the new external data processing instructions to the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black bf45d44cbe ARM: Implement data processing instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black c02f9cdddf ARM: Add new base classes for data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 1e7b317a98 ARM: Hook up 32 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 64d6b6ebfd ARM: Hook up 16 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 51bde086d5 ARM: Reimplement load/store multiple external to the decoder. 
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
 2010-06-02 12:58:02 -05:00
Gabe Black 93a3714816 ARM: Move the templates for predicated instructions into a separate file. 
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.

--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 04300e33d4 ARM: Remove the special naming for the new memory instructions. 
These are the only memory instructions now.
 2010-06-02 12:58:01 -05:00
Gabe Black deb6e8f805 ARM: Eliminate the old memory formats which are no longer used. 2010-06-02 12:58:01 -05:00
Gabe Black 1905024766 ARM: Eliminate decoding for the very deprecated FPA instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 55465844dc ARM: Make the addressing mode 3 loads/stores use the externally defined instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 36b6ca2ce3 ARM: Pull double memory instructions out of the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 79b288f7b5 ARM: Force the condition code for 16 bit thumb instructions to be unconditional. 
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
 2010-06-02 12:58:01 -05:00
Gabe Black a86491fbf2 ARM: Decode 16 bit thumb PC relative memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black dc8af1b211 ARM: Decode 16 bit thumb immediate addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 4bbd73649d ARM: Decode 16 bit thumb register addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 462cf6f49b ARM: Make single stores decode to the new external store instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b0f3b1ee2 ARM: Add a .w to the disassembly of 32 bit thumb instructions. 
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
 2010-06-02 12:58:01 -05:00
Gabe Black fde3c8f41d ARM: Make 32 bit thumb use the new, external load instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b93015304 ARM: Define the store instructions from outside the decoder. 
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 81fdced83f ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 321d3a6e8c ARM: Implement a new set of base classes for non macro memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 8933857af7 ARM: Create a "decoder" directory for the files implementing the decoder. 
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 4ebd44dc4f ARM: Flesh out the 32 bit thumb store single instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 386424ccb5 ARM: Implement the 32 bit thumb load word instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 292b8a3c91 ARM: Add an operand for accessing the current PC. 2010-06-02 12:58:00 -05:00
Gabe Black 003346077f ARM: Flesh out 32 bit thumb load word decoding. 2010-06-02 12:58:00 -05:00
Gabe Black 0d4c4cacab ARM: Implement some 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bd8812cf99 ARM: Replace the "never" condition with the "unconditional" condition. 2010-06-02 12:58:00 -05:00
Gabe Black af91d27271 ARM: Add a base class for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bfe1a194dd ARM: Add a function to decode 32 bit thumb immediate values. 2010-06-02 12:58:00 -05:00
Gabe Black 0116655674 ARM: Expand the decoding for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black cef2e8ecee ARM: Stub out the 32 bit Thumb portion of the decoder. 2010-06-02 12:58:00 -05:00
Gabe Black 659f8d021f ARM: Add bitfields for 32 bit thumb. 2010-06-02 12:58:00 -05:00
Gabe Black bc6ae010c9 ARM: Decode VFP instructions. 2010-06-02 12:58:00 -05:00
Gabe Black 7b8525287d ARM: Stub out the 16 bit thumb decoder. 2010-06-02 12:58:00 -05:00
Gabe Black aaa619ea23 ARM: Add thumb bitfields to the ExtMachInst and the isa definition. 2010-06-02 12:58:00 -05:00
Gabe Black a1838f2c79 ARM: Make the decoder handle thumb instructions separately. 
--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa
 2010-06-02 12:58:00 -05:00
Gabe Black 0dffd8ce79 ARM: Add a thumb bit bitfield. 2010-06-02 12:58:00 -05:00
Gabe Black 96be7e16c1 ARM: Make the predecoder handle Thumb instructions. 2010-06-02 12:58:00 -05:00
Gabe Black f49cdb4f5d ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. 2010-06-02 12:58:00 -05:00
Gabe Black 330d9d4dbc ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst. 2010-06-02 12:58:00 -05:00
Gabe Black a59d219989 ARM: Add a bit to the ExtMachInst to select thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black 4ddeceba96 ARM: Allow ARM processes to start in Thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black ebb273bb7b ARM: Add a new base class for instructions that can do an interworking branch. 2010-06-02 12:57:59 -05:00
Gabe Black 9ef82c0bc4 ARM: Track the current ISA mode using the PC. 2010-06-02 12:57:59 -05:00
Gabe Black 4b87bc887a ARM: Remove IsControl from operands that don't imply control transfers. 
Also remove IsInteger from CondCodes.
 2010-06-02 12:57:59 -05:00
Steve Reinhardt 4d77ea7a57 cpu: fix exec tracing memory corruption bug 
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical.  Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition.  It also moves those calls above
the translation calls to eliminate the crashes.
 2010-03-23 08:50:57 -07:00
Timothy M. Jones 29e8bcead5 O3PCU: Split loads and stores that cross cache line boundaries. 
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.

This modifies the LSQSenderState class to record both packets in a split
load or store.

Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
 2010-02-12 19:53:20 +00:00
Ali Saidi 422f0d9f10 ARM: Begin implementing CP15 2009-11-17 18:02:09 -06:00
Ali Saidi 0916c376a9 ARM: Differentiate between LDM exception return and LDM user regs. 2009-11-17 18:02:08 -06:00
Ali Saidi 1470dae8e9 ARM: Boilerplate full-system code. 
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
 2009-11-17 18:02:08 -06:00
Ali Saidi 171e7f7b24 imported patch isa_fixes2.diff 2009-11-16 11:37:03 -06:00
Gabe Black 9127ee5ac8 ARM: Make the exception return form of ldm restore CPSR. 2009-11-15 00:23:14 -08:00
Gabe Black 903fb8c73d ARM: Create a new type of load uop that restores spsr into cpsr. 2009-11-15 00:15:42 -08:00
Gabe Black b41725f723 ARM: Check in the actual change from the last commit. 
The last commit was somehow empty. This was what was supposed to go in it.
 2009-11-14 21:03:10 -08:00
Gabe Black c4042985d7 ARM: Fix up the implmentation of the msr instruction. 2009-11-14 19:22:30 -08:00
Gabe Black e2ab64543b ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. 2009-11-14 19:22:30 -08:00
Gabe Black 425ebf6bd7 ARM: Add a bitfield to indicate if an immediate should be used. 2009-11-14 19:22:30 -08:00
Gabe Black e543f16247 ARM: Write some functions to write to the CPSR and SPSR for instructions. 2009-11-14 19:22:30 -08:00
Gabe Black 812e390693 ARM: Fix up the implmentation of the mrs instruction. 2009-11-14 19:22:29 -08:00
Gabe Black 1df0025e28 ARM: More accurately describe the effects of using the control operands. 2009-11-14 19:22:29 -08:00
Gabe Black 50b9149c75 ARM: Hook up the moded versions of the SPSR. 
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
 2009-11-14 19:22:29 -08:00
Ali Saidi 48bc573f5f ARM: Move around decoder to properly decode CP15 2009-11-14 11:25:00 -06:00
Gabe Black 5524af83ef ARM: Fix some bugs in the ISA desc and fill out some instructions. 2009-11-10 23:44:05 -08:00
Gabe Black 2e28da5583 ARM: Implement fault classes. 
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
 2009-11-10 20:34:38 -08:00
Gabe Black 4779020e13 ARM: Fix the integer register indexes. 
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
 2009-11-10 20:19:55 -08:00
Gabe Black 8a4af3668d ARM: Support forcing load/store multiple to use user registers. 2009-11-08 15:49:03 -08:00
Gabe Black bb903b6514 ARM: Simplify the load/store multiple generation code. 
Specifically, get rid of the big switch statement so more cases can be
handled. Enumerating all the possible settings doesn't scale well. Also do
some minor style clean up.
 2009-11-08 15:16:59 -08:00
Gabe Black 48525f581c ARM: Split the condition codes out of the CPSR. 
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
 2009-11-08 02:08:40 -08:00
Gabe Black d188821d37 ARM: Add in more bits for the mon mode. 2009-11-08 02:01:02 -08:00
Gabe Black 3a3e846151 ARM: Get rid of NumInternalProcRegs. 
That constant is a carry over from Alpha and doesn't do anything in ARM.
 2009-11-08 02:00:55 -08:00
Gabe Black 78bd8fe44f ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR. 2009-11-08 01:59:20 -08:00
Gabe Black f63c260d89 ARM: Get rid of the Raddr operand. 2009-11-08 01:57:34 -08:00
Gabe Black 43e9209c21 ARM: Initialize processes in user mode. 
I accidentally left in a change to test using int registers in system mode.
This change reverts that.
 2009-11-08 00:54:32 -08:00
Gabe Black a2b76516c4 ARM: Implement the shadow registers using register flattening. 2009-11-08 00:07:49 -08:00
Gabe Black 4a454c4f47 ARM: Set up an intregs.hh for ARM. 
Add constants for all the modes and registers, maps for aliasing, functions
that use the maps and range check, and use a named constant instead of a magic
number for the microcode register.
 2009-11-08 00:07:35 -08:00
Gabe Black 18b21c1eca ARM: Get rid of some unneeded register indexes. 2009-11-07 22:34:33 -08:00
Nathan Binkert 2c5fe6f95e build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
Gabe Black 3f722b991f Syscalls: Make system calls access arguments like a stack, not an array. 
When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
 2009-10-30 00:44:55 -07:00
Timothy M. Jones 1b2d75d6d2 syscall: Addition of an ioctl command code for Power. 2009-10-24 10:53:59 -07:00
Gabe Black 010b13c937 ISA: Fix compilation. 2009-10-17 01:13:41 -07:00
Nathan Binkert d9f39c8ce7 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
Vince Weaver 9b8e61beb3 Syscalls: Implement sysinfo() syscall. 2009-09-15 22:36:47 -07:00
Steve Reinhardt 1c28004654 Clean up some inconsistencies with Request flags. 2009-08-01 22:50:13 -07:00
Gabe Black 4971331b4f ARM: Mul and mla ignore the c and v flags, but we were setting them to 1. 2009-07-29 22:24:00 -07:00
Gabe Black b066e717f4 ARM: Fix an instruction in the cmpxchg kernel provided routine. 
The instruction was encoded as a load instead of the intended store.
 2009-07-29 00:18:26 -07:00
Gabe Black c2da5bae17 ARM: Get rid of a stray line in the set_tls handler. 2009-07-29 00:17:20 -07:00
Gabe Black 1e04b6281d ARM: Make the ARM native tracer stop M5 if control diverges. 
If the control flow of M5's executable and statetrace's target process get out
of sync even a little, there will be a LOT of output, very little of which
will be useful. There's also almost no hope for recovery. In those cases, we
might as well give up and not generate a huge, mostly worthless trace file.
 2009-07-29 00:17:11 -07:00
Gabe Black 873112ea99 ARM: Make sure the target process doesn't run away from statetrace. 2009-07-29 00:14:43 -07:00
Ali Saidi 0a9eb59e6f ARM: Ignore the "times" system call. 2009-07-29 00:09:46 -07:00
Ali Saidi 19a4fb0ff3 ARM: Fix an ioctl constant. 2009-07-29 00:09:44 -07:00
Ali Saidi daf8718da9 ARM: Update some syscall constants and delete others that are Alpha only. 2009-07-27 00:54:55 -07:00
Gabe Black d3f2992e39 ARM: Decode fstmx and fldmx instructions. We can ignore them for now. 2009-07-27 00:54:50 -07:00
Gabe Black 52b4a7c36f ARM: Only send information that changed between statetrace and M5. 2009-07-27 00:54:30 -07:00
Gabe Black 90d3d3535b imported patch nativetracestreamline.patch 2009-07-27 00:54:24 -07:00
Gabe Black 8ec235c7b1 ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
Gabe Black c18d6cb1a7 ARM: Implement a basic version of the fmxr instruction. 2009-07-27 00:53:29 -07:00
Gabe Black 2828fa459d ARM: Implement a basic version of the fmrx instruction. 2009-07-27 00:53:24 -07:00
Gabe Black 4079792f2b ARM: Add in spots for the VFP control registers. 2009-07-27 00:53:10 -07:00
Gabe Black b560acfe17 ARM: Fix the CLZ instruction. 2009-07-27 00:52:59 -07:00
Gabe Black dc0df3f396 ARM: Initialize the CPSR so that we're in user mode. 2009-07-27 00:52:48 -07:00
Gabe Black b8bf34be05 ARM: Set up the initial stack frame to match a recent Linux. 2009-07-27 00:52:31 -07:00
Gabe Black a41e132007 ARM: Make native trace only print when registers are changing value. 
When registers have incorrect values but aren't actively changing, it's likely
they're not being modified at all. The fact that they're still wrong isn't
very important.
 2009-07-27 00:52:01 -07:00
Gabe Black 519ace4dfd ARM: Add a native tracer. 
--HG--
rename : src/arch/sparc/SparcNativeTrace.py => src/arch/arm/ArmNativeTrace.py
rename : src/arch/sparc/nativetrace.cc => src/arch/arm/nativetrace.cc
rename : src/arch/sparc/nativetrace.hh => src/arch/arm/nativetrace.hh
 2009-07-27 00:51:35 -07:00
Ali Saidi e7640227ca ARM: Fix fstat/fstat64 structs to match EABI definitions. 2009-07-27 00:51:20 -07:00
Ali Saidi 99831ed938 ARM: Handle register indexed system calls. 2009-07-27 00:51:01 -07:00
Jack Whitham fce4412d76 ARM: Fix the "open" flag constants. 2009-07-14 21:03:33 -07:00
Gabe Black e14c408b62 ARM: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:27 -07:00
Gabe Black b398b8ff1b Registers: Add a registers.hh file as an ISA switched header. 
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
 2009-07-08 23:02:21 -07:00
Gabe Black 997f36c711 Registers: Collapse ARM and MIPS regfile directories. 
--HG--
rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh
rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc
rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc
rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
 2009-07-08 23:02:21 -07:00
Gabe Black 5c37d10624 Registers: Eliminate the ISA defined RegFile class. 2009-07-08 23:02:21 -07:00
Gabe Black 43345bff6c Registers: Move the PCs out of the ISAs and into the CPUs. 2009-07-08 23:02:21 -07:00
Gabe Black 1b29f1621d ARM, Simple CPU: Fix an index and add assert checks. 2009-07-08 23:02:21 -07:00
Gabe Black 27b6148f47 ARM: Flush out the ARM's int_regfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black a480ba00b9 Registers: Eliminate the ISA defined integer register file. 2009-07-08 23:02:20 -07:00
Gabe Black 0cb180ea0d Registers: Eliminate the ISA defined floating point register file. 2009-07-08 23:02:20 -07:00
Gabe Black 25884a8773 Registers: Get rid of the float register width parameter. 2009-07-08 23:02:20 -07:00
Gabe Black 32daf6fc3f Registers: Add an ISA object which replaces the MiscRegFile. 
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
 2009-07-08 23:02:20 -07:00
Gabe Black 3e2cad8370 ARM: Use custom read/write code to alias R15 with the PC. 2009-07-08 23:02:20 -07:00
Gabe Black 95392d3fb8 ARM: Move the remaining microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black 1d4f338b39 ARM: Move the memory microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black 70a75ceb84 ARM: Move the integer microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black 4eb18cc07a ARM: Improve memory instruction disassembly. 2009-07-08 23:02:19 -07:00
Gabe Black 2fb8d481ab ARM: Tune up predicated instruction decoding. 2009-07-08 23:02:19 -07:00
Gabe Black ddcf084f16 ARM: Get rid of the MemAcc and EAComp static insts. 2009-07-08 23:02:19 -07:00
Gabe Black cae870eded ARM: Get rid of end_addr in the ArmMacroStore constructor. 2009-07-08 23:02:19 -07:00
Gabe Black 311f77f33d ARM: Add an AddrMode2 format for memory instructions that use address mode 2. 2009-07-08 23:02:19 -07:00
Gabe Black 826a3582ea ARM: Don't always update CPSR. 2009-07-08 23:02:19 -07:00
Gabe Black 17f0943398 ARM: Add an AddrMode3 format for memory instructions that use address mode 3. 2009-07-08 23:02:19 -07:00
Gabe Black dac0cb5c7e ARM: Add load/store double instructions. 2009-07-08 23:02:10 -07:00
Gabe Black 1ca0688c4c ARM: Add operands for the load/store double instructions. 2009-07-08 23:02:01 -07:00
Jack Whitham a223a065e6 ARM: Fix how address mode bits are handled. 2009-07-02 23:23:06 -07:00
Jack Whitham a738006397 ARM: Fix the code snippet for mla. 2009-07-02 23:22:58 -07:00
Gabe Black 26c70ce2cb ARM: Make DataOps select from a set of ways to set the c and v flags. 2009-07-01 22:17:06 -07:00
Gabe Black 148c265cf3 ARM: Get rid of some bitfields that aren't used. A few may need to be readded. 2009-07-01 22:16:51 -07:00
Gabe Black 7172e26cc4 ARM: Add a findLsbSet function and use it to implement clz. 2009-07-01 22:16:36 -07:00
Gabe Black f5141c23fd ARM: Add defaults for DataOp flag code. 2009-07-01 22:16:19 -07:00
Gabe Black 22a1ac22f4 ARM: Get rid of the val2 variable. 2009-07-01 22:16:05 -07:00
Gabe Black ce9cb1ecb5 ARM: Centralize the declaration of resTemp. 2009-07-01 22:15:39 -07:00
Gabe Black 776a06fd39 ARM: Add a DataImmOp format similar to DataOp. 2009-07-01 22:12:10 -07:00
Gabe Black 4f98171479 ARM: Decode some media instructions. These are untested. 2009-07-01 22:11:54 -07:00
Gabe Black b8f064c88c ARM: Use the new DataOp format to simplify the decoder. 2009-07-01 22:11:39 -07:00
Gabe Black f409d7819d ARM: Add in some new artificial fields that make decoding a little easier. 2009-07-01 22:11:27 -07:00
Gabe Black 1f0c0a6688 ARM: Recognize the IntRegs trace flag. 2009-07-01 22:11:12 -07:00
Gabe Black 065cb59427 ARM: Add a DataOp format so data op definitions can be aggregated. 2009-07-01 22:10:58 -07:00
Gabe Black 1ea14b8fac ARM: Show more information when disassembling data processing intstructions. 
This will need more work, but it should be a lot closer.
 2009-06-27 00:30:23 -07:00
Gabe Black 56f1845471 ARM: Show branch targets relative to the nearest symbol. 2009-06-27 00:29:30 -07:00
Gabe Black a4ac3fad7a ARM: Write a function for printing mnemonics and predicates. 2009-06-27 00:29:12 -07:00
Gabe Black 38d8bc64ba ARM: Fill out the printReg function. 2009-06-26 22:01:34 -07:00
Jack Whitman 7b5386d390 ARM: Fix signed multiply long and add some unimplemented loads. 2009-06-24 21:22:52 -07:00
Jack Whitman 853a0858f3 ARM: Link register is trashed by non-executed branch and link operations. 2009-06-24 21:22:46 -07:00
Jack Whitman 6dd4272804 ARM: Added unimplemented load/store multiple instructions. 2009-06-23 23:23:25 -07:00
Gabe Black d744525273 ARM: Simplify some utility functions. 2009-06-21 22:51:13 -07:00
Gabe Black 5c2a362cb7 ARM: Move util functions out of the isa desc. 2009-06-21 22:50:33 -07:00
Gabe Black d4a03f1900 ARM: Simplify the ISA desc by pulling some classes out of it. 2009-06-21 17:21:25 -07:00
Gabe Black 2a39570b78 ARM: Remove the currently unecessary FPAOp class. 2009-06-21 17:14:51 -07:00
Gabe Black d1d733f636 ARM: Make inst bitfields accessible outside of the isa desc. 2009-06-21 16:41:21 -07:00
Gabe Black 47e71d674a ARM: Don't downconvert ExtMachInsts to MachInsts. 2009-06-21 16:41:07 -07:00
Gabe Black 7e4f132369 ARM: Get rid of a few more unused operands. 2009-06-21 09:48:51 -07:00
Gabe Black 4415e2dcd6 ARM: Get rid of unnecessary Re operand. 2009-06-21 09:48:44 -07:00
Gabe Black 7d4ef8a398 ARM: Clear out some inherited hangers on in util.isa and utility.hh. 2009-06-21 09:43:55 -07:00
Gabe Black 5bc1373050 ARM: Get rid of unnecessary fp_enable_checks. 2009-06-21 09:41:04 -07:00
Gabe Black 3964709711 ARM: Adjust simplify rotate_imm slightly. 2009-06-21 09:38:54 -07:00
Gabe Black c20ce20e4c ARM: Make the isa parser aware that CPSR is being used. 2009-06-21 09:37:41 -07:00
Gabe Black 71e0d1ded2 ARM: Pull some static code out of the isa desc and create miscregs.hh. 2009-06-21 09:21:07 -07:00
Gabe Black 19a1966079 ARM: Get rid of unused postacc_code. 2009-06-21 09:16:55 -07:00
Gabe Black b394242240 ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params. 2009-06-09 23:41:45 -07:00
Gabe Black c913c64be2 ARM: Add a memory_barrier function to the "comm page". 
This function doesn't actually provide a memory barrier (I don't think they're
implemented) and instead just returns.
 2009-06-09 23:41:35 -07:00
Gabe Black 3ff1e922c2 ARM: Add a cmpxchg implementation to the "comm page". 
This implementation does what it's supposed to (I think), but it's not atomic
and doesn't have memory barriers like the kernel's version.
 2009-06-09 23:41:03 -07:00
Gabe Black 37ac2871d5 ARM: Implement TLS. This is not tested. 2009-06-09 23:39:07 -07:00
Gabe Black 5daeefc505 ARM: Make ArmLinuxProcess understand "ARM private" system calls. 2009-06-09 23:38:50 -07:00
Gabe Black fbf4dc9da2 ARM: Update the kernel version M5 reports to 2.6.16.19 2009-06-09 23:37:41 -07:00
Nathan Binkert 8d2e51c7f5 includes: sort includes again 2009-05-17 14:34:52 -07:00
Nathan Binkert eef3a2e142 types: Move stuff for global types into src/base/types.hh 
--HG--
rename : src/sim/host.hh => src/base/types.hh
 2009-05-17 14:34:50 -07:00
Nathan Binkert 82c9e6a5fc gcc: work around a bogus gcc error 2009-05-12 22:33:05 -07:00
Nathan Binkert 43c7698f49 arm: include missing file for arm 2009-04-21 15:40:26 -07:00
Nathan Binkert 50f1570352 arm: Unify the ARM tlb. We forgot about this when we did the rest. 
This code compiles, but there are no tests still
 2009-04-21 15:40:25 -07:00
Gabe Black d080581db1 Merge ARM into the head. ARM will compile but may not actually work. 2009-04-06 10:19:36 -07:00
Stephen Hines 7a7c4c5fca arm: add ARM support to M5 2009-04-05 18:53:15 -07:00