Gabe Black
e2e0ae576a
X86: Make sure immediate values are truncated properly.
...
Register values will be "picked" which will assure they don't have junk beyond
the part we're using. Immediate values don't go through a similar process, so
we should truncate them explicitly.
2009-08-05 03:06:01 -07:00
Gabe Black
ef3896d851
X86: Use the new forced folding mechanism for the SAHF and LAHF instructions.
2009-08-05 03:04:17 -07:00
Gabe Black
664d50b439
X86: Fix the indexing for ah in byte division instructions.
2009-08-05 03:03:41 -07:00
Gabe Black
abe8fb3844
X86: Fix the indexing for ah in byte multiply instructions.
2009-08-05 03:03:28 -07:00
Gabe Black
df1abc4412
X86: Let microops force folding an index into the high byte of a register.
2009-08-05 03:03:07 -07:00
Gabe Black
c4140d7d60
X86: Handle rotate left with carry instructions that go all the way around or more.
2009-08-05 03:02:28 -07:00
Gabe Black
3990445354
X86: Set the flags on rotate left with carry instructions.
2009-08-05 03:02:05 -07:00
Gabe Black
d265f7683e
X86: Handle rotate right with carry instructions that go all the way around or more.
2009-08-05 03:01:49 -07:00
Gabe Black
77dc6b33ee
X86: Fix the overflow bit for rotate right with carry.
2009-08-05 03:01:23 -07:00
Gabe Black
c8b1a4583e
X86: Fix the computation of the bottom part of rotate right with carry.
2009-08-05 03:01:07 -07:00
Gabe Black
bab4597fc5
X86: Fix the computation of the upper part of rotate right with carry.
2009-08-05 03:00:43 -07:00
Gabe Black
4e4adcaaa8
X86: Set the flags for rotate right with carry instructions.
2009-08-05 03:00:23 -07:00
Gabe Black
64d7948692
X86: Handle rotating right all the way around or more.
2009-08-05 03:00:03 -07:00
Gabe Black
88041f75c4
X86: Set the flags on a rotate right instruction.
2009-08-05 02:59:39 -07:00
Gabe Black
029d360db2
X86: Make shifts/rotations that write to 32 bits of a register zero extend.
2009-08-05 02:59:25 -07:00
Gabe Black
7f9a3af250
X86: Handle left rotations that go all the way around or more.
2009-08-05 02:58:54 -07:00
Gabe Black
99adfd9dae
X86: Actually set the flags on a rotate left instruction.
2009-08-05 02:58:20 -07:00
Gabe Black
c087b60af3
X86: Fix the sar carry flag.
2009-08-05 02:58:03 -07:00
Gabe Black
860f0f8350
X86: Fix sign extension when doing an arithmetic shift right by 0.
2009-08-05 02:57:47 -07:00
Gabe Black
a238959c34
X86: Fix the carry flag for shr.
2009-08-05 02:56:49 -07:00
Gabe Black
22a5f66820
X86: Fix the carry flag for shl.
2009-08-05 02:56:38 -07:00
Gabe Black
df2c862a07
X86: Fix how the parity flag is computed.
...
It's only for the lowest order byte, and I had the polarity wrong.
2009-08-05 02:56:12 -07:00
Derek Hower
7f012ef8da
ruby: made mapAddressToRange based off a bit count
2009-08-04 23:05:37 -05:00
Derek Hower
33b28fde7a
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers
...
This changeset contains a lot of different changes that are too
mingled to separate. They are:
1. Added MOESI_CMP_directory
I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.
2. DMA Sequencer uses a generic SequencerMsg
I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.
3. Parameterized Controllers
SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.
2009-08-04 12:52:52 -05:00
Derek Hower
c1e0bd1df4
slicc: generate html by default
2009-08-04 12:42:45 -05:00
Nathan Binkert
bd7af84d5e
slicc: better error messages when the python parser fails
2009-08-04 09:37:27 -07:00
Gabe Black
f5c21eaa1a
Merged with head.
2009-08-03 11:06:19 -07:00
Gabe Black
676dc6d292
X86: Fix segment override prefixes on instructions that use rbp/rsp and a displacement.
2009-08-03 11:01:40 -07:00
Derek Hower
ac15e42c17
Automated merge with ssh://hg@m5sim.org/m5
2009-08-03 11:39:08 -05:00
Gabe Black
38c2af17a5
X86: Set up the IDE device correctly, ie. with and using legacy ports.
2009-08-02 18:01:13 -07:00
Gabe Black
80aa771dbc
IDE: Configure the IDE control to reflect the initial value of the command register.
2009-08-02 18:01:09 -07:00
Gabe Black
aff57202b4
X86: Fix the high result of mul1s, and removed undefined shifts from the mult microops.
2009-08-02 08:39:29 -07:00
Steve Reinhardt
a13a706a20
Fix setting of INST_FETCH flag for O3 CPU.
...
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
2009-08-01 22:50:14 -07:00
Steve Reinhardt
1c28004654
Clean up some inconsistencies with Request flags.
2009-08-01 22:50:13 -07:00
Steve Reinhardt
c0755e6085
Rename internal Request fields to start with '_'.
...
The inconsistency was causing a subtle bug with some of the
constructors where the params had the same name as the fields.
This is also a first step to switching the accessors over to
our new "standard", e.g., getVaddr() -> vaddr().
2009-08-01 22:50:10 -07:00
Korey Sewell
aa75b9a7a7
merge mips fix and statetrace changes
2009-07-31 10:40:42 -04:00
Korey Sewell
60063cc700
mips: fix ll/sc pairs working incorrectly because of accidental clobber of LLFLAG
2009-07-31 09:34:29 -04:00
Nathan Binkert
3dd3de5feb
compile: fix accidental conversion of == into =
2009-07-30 17:42:57 -07:00
Gabe Black
4971331b4f
ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
2009-07-29 22:24:00 -07:00
Derek Hower
d9ff3021ba
ruby: fixed clearStats
2009-07-29 13:46:58 -05:00
Gabe Black
b066e717f4
ARM: Fix an instruction in the cmpxchg kernel provided routine.
...
The instruction was encoded as a load instead of the intended store.
2009-07-29 00:18:26 -07:00
Gabe Black
c2da5bae17
ARM: Get rid of a stray line in the set_tls handler.
2009-07-29 00:17:20 -07:00
Gabe Black
1e04b6281d
ARM: Make the ARM native tracer stop M5 if control diverges.
...
If the control flow of M5's executable and statetrace's target process get out
of sync even a little, there will be a LOT of output, very little of which
will be useful. There's also almost no hope for recovery. In those cases, we
might as well give up and not generate a huge, mostly worthless trace file.
2009-07-29 00:17:11 -07:00
Gabe Black
2871a13ab3
Simple CPU: Make the simple CPU handle the IntRegs trace flag.
2009-07-29 00:15:26 -07:00
Gabe Black
873112ea99
ARM: Make sure the target process doesn't run away from statetrace.
2009-07-29 00:14:43 -07:00
Ali Saidi
0a9eb59e6f
ARM: Ignore the "times" system call.
2009-07-29 00:09:46 -07:00
Ali Saidi
19a4fb0ff3
ARM: Fix an ioctl constant.
2009-07-29 00:09:44 -07:00
Derek Hower
469256d823
ruby: removed unused/incorrect profiler state
2009-07-27 21:43:43 -05:00
Ali Saidi
daf8718da9
ARM: Update some syscall constants and delete others that are Alpha only.
2009-07-27 00:54:55 -07:00
Gabe Black
d3f2992e39
ARM: Decode fstmx and fldmx instructions. We can ignore them for now.
2009-07-27 00:54:50 -07:00
Gabe Black
52b4a7c36f
ARM: Only send information that changed between statetrace and M5.
2009-07-27 00:54:30 -07:00
Gabe Black
90d3d3535b
imported patch nativetracestreamline.patch
2009-07-27 00:54:24 -07:00
Gabe Black
8ec235c7b1
ARM: Make native trace print out what instruction caused an error.
2009-07-27 00:54:09 -07:00
Gabe Black
c18d6cb1a7
ARM: Implement a basic version of the fmxr instruction.
2009-07-27 00:53:29 -07:00
Gabe Black
2828fa459d
ARM: Implement a basic version of the fmrx instruction.
2009-07-27 00:53:24 -07:00
Gabe Black
4079792f2b
ARM: Add in spots for the VFP control registers.
2009-07-27 00:53:10 -07:00
Gabe Black
b560acfe17
ARM: Fix the CLZ instruction.
2009-07-27 00:52:59 -07:00
Gabe Black
dc0df3f396
ARM: Initialize the CPSR so that we're in user mode.
2009-07-27 00:52:48 -07:00
Gabe Black
b8bf34be05
ARM: Set up the initial stack frame to match a recent Linux.
2009-07-27 00:52:31 -07:00
Gabe Black
ebc2897673
Elf: Add in some new aux vector type constants.
2009-07-27 00:52:19 -07:00
Gabe Black
a41e132007
ARM: Make native trace only print when registers are changing value.
...
When registers have incorrect values but aren't actively changing, it's likely
they're not being modified at all. The fact that they're still wrong isn't
very important.
2009-07-27 00:52:01 -07:00
Gabe Black
519ace4dfd
ARM: Add a native tracer.
...
--HG--
rename : src/arch/sparc/SparcNativeTrace.py => src/arch/arm/ArmNativeTrace.py
rename : src/arch/sparc/nativetrace.cc => src/arch/arm/nativetrace.cc
rename : src/arch/sparc/nativetrace.hh => src/arch/arm/nativetrace.hh
2009-07-27 00:51:35 -07:00
Ali Saidi
e7640227ca
ARM: Fix fstat/fstat64 structs to match EABI definitions.
2009-07-27 00:51:20 -07:00
Ali Saidi
99831ed938
ARM: Handle register indexed system calls.
2009-07-27 00:51:01 -07:00
Ali Saidi
0a18bc0d6c
ARM: Detect OABI binaries and complain that they're no-longer supported.
2009-07-27 00:50:55 -07:00
Gabe Black
ef4e8b04a6
SPARC: Fix a minor compile bug in native trace on gcc > 4.1.
2009-07-25 15:14:00 -07:00
Korey Sewell
44f80e7ca5
o3-smt: enforce numThreads parameter for SMT SE mode
2009-07-25 00:50:27 -04:00
Polina Dudnik
e7a3bda497
Fixed the licences plus minor fixes for compilation
2009-07-22 20:28:32 -05:00
Gabe Black
9ba2ed8532
MIPS: Small fix I forgot to qrefresh into my last change.
2009-07-22 01:57:55 -07:00
Gabe Black
7f0c07bf03
MIPS: Style/formatting sweep of the decoder itself.
2009-07-22 01:51:10 -07:00
Gabe Black
c874bfae3f
MIPS: Format the register index constants like the other ISAs.
...
Also a few more style fixes.
2009-07-21 23:38:26 -07:00
Derek Hower
c635d04642
Automated merge with ssh://m5sim.org//repo/m5
2009-07-21 21:27:54 -05:00
Derek Hower
7f34ee36ec
ruby: fixed sequencer RMW data bug
2009-07-21 19:42:09 -05:00
Derek Hower
80544cda8a
ruby: libruby_init now takes parsed Ruby-lang config text
...
libruby_init now expects to get a file that contains the output of
running a ruby-lang configuration, opposed to the ruby-lang
configuration itself.
2009-07-21 18:33:05 -05:00
Gabe Black
74584d79b6
MIPS: Get MIPS_FS to compile, more style fixes.
...
Some breakage was from my BitUnion change, some was much older.
2009-07-21 01:09:05 -07:00
Gabe Black
7548082d3b
MIPS: Many style fixes.
...
White space, commented out code, some other minor fixes.
2009-07-21 01:08:53 -07:00
Gabe Black
dc0a017ed0
isa_parser: Get rid of the now unused ControlBitfieldOperand.
2009-07-20 20:20:17 -07:00
Gabe Black
5161bc19d9
MIPS: Use BitUnions instead of bits() functions and constants.
...
Also fix style issues in regions around these changes.
2009-07-20 20:14:15 -07:00
Derek Hower
225de2eaff
merge
2009-07-20 09:41:28 -05:00
Derek Hower
e59d0e3e89
ruby: moved cache stats from Profiler to CacheMemory
...
Caches are now responsible for their own statistic gathering. This
requires a direct callback from the protocol on misses, and so all
future protocols need to take this into account.
2009-07-20 09:40:43 -05:00
Gabe Black
3e8e813218
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
...
--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-19 23:54:56 -07:00
Gabe Black
a3a795769a
Tracing: Add accessors so tracers can get at data in trace records.
2009-07-19 23:54:31 -07:00
Gabe Black
f0cb698a87
X86: Move a displaced comment back to where it goes.
2009-07-19 23:51:47 -07:00
Gabe Black
563654275f
X86: Add some misc registers for FP control state.
2009-07-19 23:51:41 -07:00
Derek Hower
308419b947
scons: removed RubyConfig from scons
2009-07-19 12:34:11 -05:00
Derek Hower
7cd2d8f687
ruby: removed all refs to old RubyConfig
2009-07-18 18:20:03 -05:00
Derek Hower
4bd7fe4c53
ruby: removed dead files
2009-07-18 18:18:37 -05:00
Derek Hower
f3d8d29342
ruby: removed dead files
2009-07-18 18:17:48 -05:00
Derek Hower
926ab6e6db
merge
2009-07-18 17:40:20 -05:00
Derek Hower
4b7ea4cb51
ruby: fixed dma sequencer bug
...
The DMASequencer was still using a parameter from the old RubyConfig,
causing an offset error when the requested data wasn't block aligned.
This changeset also includes a fix to MI_example for a similar bug.
2009-07-18 17:03:51 -05:00
Derek Hower
340845b139
ruby: better debug print for DataBlock
2009-07-18 16:58:33 -05:00
Derek Hower
7433029cd5
slicc: made coherence profilers per-controller
2009-07-18 16:54:45 -05:00
Gabe Black
d85cd08113
X86: Set up a named constant for the "fold bit" for int register indices.
2009-07-17 18:49:22 -07:00
Gabe Black
7b6587fc9c
X86: Tame the wilds of def operands.
2009-07-17 00:29:56 -07:00
Gabe Black
df378285f8
X86: Shift some register flattening work into the decoder.
2009-07-17 00:29:42 -07:00
Polina Dudnik
e557b4beb5
merge
2009-07-16 15:40:48 -05:00
Gabe Black
e9eccf7225
X86: Add range checks for miscreg indexing utility functions.
2009-07-16 09:30:14 -07:00
Gabe Black
ba6b8389ee
X86: Take limitted advantage of the compilers type checking for microop operands.
2009-07-16 09:29:29 -07:00
Gabe Black
80c834ccac
X86: Fix a number of places where the wrong form of a microop was used.
2009-07-16 09:27:56 -07:00
Gabe Black
3f9b0cc5ca
X86: Fix x87 stack register indexing.
2009-07-16 09:26:38 -07:00
Polina Dudnik
23a405f5d8
Tester update
2009-07-15 10:46:22 -05:00
Gabe Black
6262b31515
Merge with head.
2009-07-14 18:06:30 -07:00
Jack Whitham
fce4412d76
ARM: Fix the "open" flag constants.
2009-07-14 21:03:33 -07:00
Polina Dudnik
289cd00326
Changed the state machine to generate code such that multiple processors can make atomic requests at once
2009-07-13 18:39:32 -05:00
Polina Dudnik
5f551d9ca2
1. Got rid of unused functions in DirectoryMemory
...
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue
Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once
2009-07-13 17:22:29 -05:00
Derek Hower
100da6b326
merge
2009-07-13 14:49:51 -05:00
Derek Hower
d51445490d
regression: updated memtest-ruby stats
...
This also includes a change to the default Ruby random seed, which was
previously set using the wall clock. It is now set to 1234 so that
the stat files don't change for the regression tester.
2009-07-13 14:45:15 -05:00
Polina Dudnik
9a675a0391
Changes to add tracing and replaying command-line options
...
Trace is automatically ended upon a manual checkpoint
2009-07-13 12:50:10 -05:00
Polina Dudnik
b28058917c
Locked requests should actually be converted to ST rather than ATOMIC, because ATOMIC is for RMW.
2009-07-13 12:11:17 -05:00
Polina Dudnik
7a6bf67e47
Added atomics implementation which would work for MI_example
2009-07-13 12:06:23 -05:00
Polina Dudnik
c66af9f474
Minor fixes for compiling
2009-07-13 11:59:13 -05:00
Polina Dudnik
7606c71ea5
Replaced RMW with Locked. RMW will be used for the coherence-aided atomics other than LLSC
2009-07-13 11:37:56 -05:00
Polina Dudnik
faf823f947
Moved the lock check and clearing the lock into makeRequest
2009-07-13 11:34:38 -05:00
Polina Dudnik
86ce60e5cd
Forgot to replace one of the RubyRequest_RMW
2009-07-13 11:25:23 -05:00
Polina Dudnik
226981b2a6
Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure
2009-07-13 11:13:29 -05:00
Gabe Black
60577eb4ca
ISAs: Get rid of the IControl operand type.
...
A separate operand type is not necessary to use two bitfields to generate the
index.
2009-07-10 01:21:04 -07:00
Gabe Black
64fe7af51a
SPARC: Set up a lookup table for integer register flattening.
...
Using a look up table changed the run time of the SPARC_FS solaris boot
regression from:
real 14m45.951s
user 13m57.528s
sys 0m3.452s
to:
real 12m19.777s
user 12m2.685s
sys 0m2.420s
2009-07-10 01:01:47 -07:00
Gabe Black
9993ca8280
X86: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:29:02 -07:00
Gabe Black
60d47aa5f9
SPARC: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:50 -07:00
Gabe Black
de7f462219
MIPS: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:39 -07:00
Gabe Black
e14c408b62
ARM: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:27 -07:00
Gabe Black
5643a222e3
Alpha: Missed a file in an earlier changeset.
2009-07-09 00:20:41 -07:00
Gabe Black
c9a27d85b9
Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
2009-07-08 23:02:22 -07:00
Gabe Black
3d39b62132
Alpha: Pull the MiscRegFile fully into the ISA object.
2009-07-08 23:02:22 -07:00
Gabe Black
b398b8ff1b
Registers: Add a registers.hh file as an ISA switched header.
...
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08 23:02:21 -07:00
Gabe Black
997f36c711
Registers: Collapse ARM and MIPS regfile directories.
...
--HG--
rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh
rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc
rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc
rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08 23:02:21 -07:00
Gabe Black
aa031e1c11
Alpha: Move reg_redir into its own files, and move some constants into regfile.hh.
2009-07-08 23:02:21 -07:00
Gabe Black
5c37d10624
Registers: Eliminate the ISA defined RegFile class.
2009-07-08 23:02:21 -07:00
Gabe Black
9bf22992ee
Alpha: Get rid of function prototypes with no implementations.
2009-07-08 23:02:21 -07:00
Gabe Black
43345bff6c
Registers: Move the PCs out of the ISAs and into the CPUs.
2009-07-08 23:02:21 -07:00
Gabe Black
1b29f1621d
ARM, Simple CPU: Fix an index and add assert checks.
2009-07-08 23:02:21 -07:00
Gabe Black
0338c83c9d
MIPS: Get rid of an orphaned MIPS .cc file.
2009-07-08 23:02:21 -07:00
Gabe Black
6ebce9d65a
Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
2009-07-08 23:02:21 -07:00
Gabe Black
faa6ebebe1
SPARC: Phase out SPARC's intregfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
ecde884404
X86: Phase out x86's intregfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
301df68c73
MIPS: Phase out MIPS's int_regfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
27b6148f47
ARM: Flush out the ARM's int_regfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
a480ba00b9
Registers: Eliminate the ISA defined integer register file.
2009-07-08 23:02:20 -07:00
Gabe Black
0cb180ea0d
Registers: Eliminate the ISA defined floating point register file.
2009-07-08 23:02:20 -07:00
Gabe Black
25884a8773
Registers: Get rid of the float register width parameter.
2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f
Registers: Add an ISA object which replaces the MiscRegFile.
...
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
2009-07-08 23:02:20 -07:00
Gabe Black
3e2cad8370
ARM: Use custom read/write code to alias R15 with the PC.
2009-07-08 23:02:20 -07:00
Gabe Black
b8b7c7314a
ISA parser: Allow alternative read/write code for operands.
2009-07-08 23:02:19 -07:00
Gabe Black
95392d3fb8
ARM: Move the remaining microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
1d4f338b39
ARM: Move the memory microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
70a75ceb84
ARM: Move the integer microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
4eb18cc07a
ARM: Improve memory instruction disassembly.
2009-07-08 23:02:19 -07:00
Gabe Black
2fb8d481ab
ARM: Tune up predicated instruction decoding.
2009-07-08 23:02:19 -07:00
Gabe Black
ddcf084f16
ARM: Get rid of the MemAcc and EAComp static insts.
2009-07-08 23:02:19 -07:00
Gabe Black
cae870eded
ARM: Get rid of end_addr in the ArmMacroStore constructor.
2009-07-08 23:02:19 -07:00
Gabe Black
311f77f33d
ARM: Add an AddrMode2 format for memory instructions that use address mode 2.
2009-07-08 23:02:19 -07:00
Gabe Black
826a3582ea
ARM: Don't always update CPSR.
2009-07-08 23:02:19 -07:00
Gabe Black
17f0943398
ARM: Add an AddrMode3 format for memory instructions that use address mode 3.
2009-07-08 23:02:19 -07:00
Gabe Black
dac0cb5c7e
ARM: Add load/store double instructions.
2009-07-08 23:02:10 -07:00
Gabe Black
1ca0688c4c
ARM: Add operands for the load/store double instructions.
2009-07-08 23:02:01 -07:00
Gabe Black
d029110fa1
X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended.
2009-07-08 23:01:54 -07:00
Derek Hower
15afc87f7c
slicc: fixed MI_example bug. The directory wasn't deallocating the TBE, leading to a leak. Also increased the default max TBE size to 256 to allow memtest to pass the regression.
2009-07-08 08:40:32 -05:00
Derek Hower
6a83bd5a03
ruby: set the default values of the debug object so that nothing is printed
2009-07-08 00:34:40 -05:00
Derek Hower
2f9d8bff5b
slicc: Fixed MI_example bug. The directory was not writing data to DRAM after a PUTX.
2009-07-08 00:31:33 -05:00
Derek Hower
96c36afea9
removed stray debug print
2009-07-07 23:01:35 -05:00
Nathan Binkert
7ffb8e5914
automerge
2009-07-06 15:54:18 -07:00
Nathan Binkert
da704f52e5
ruby: Fix RubyMemory to work with the newer ruby.
2009-07-06 15:49:47 -07:00
Nathan Binkert
a7904e2cf3
ruby: apply some fixes that were overwritten by the recent ruby import.
2009-07-06 15:49:47 -07:00
Nathan Binkert
5b080ae046
slicc: update parser.py for changes in slicc language.
2009-07-06 15:49:47 -07:00
Nathan Binkert
1f6933503d
scons: update SCons files for changes in ruby.
2009-07-06 15:49:47 -07:00
Nathan Binkert
92de70b69a
ruby: Import the latest ruby changes from gems.
...
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
2009-07-06 15:49:47 -07:00
Nathan Binkert
05f6a4a6b9
ruby: replace strings that were missed in original ruby import.
2009-07-06 15:49:47 -07:00
Gabe Black
240e214236
SPARC: Fix the parenthesis in inUserMode.
2009-07-05 16:07:09 -07:00
Jack Whitham
a223a065e6
ARM: Fix how address mode bits are handled.
2009-07-02 23:23:06 -07:00
Jack Whitham
a738006397
ARM: Fix the code snippet for mla.
2009-07-02 23:22:58 -07:00
Nathan Binkert
7daed385bf
typo: correct spelling
2009-07-02 16:48:22 -07:00
Nathan Binkert
6fd3987b3f
attrdict: correct delattr
2009-07-02 16:48:22 -07:00
Gabe Black
26c70ce2cb
ARM: Make DataOps select from a set of ways to set the c and v flags.
2009-07-01 22:17:06 -07:00
Gabe Black
148c265cf3
ARM: Get rid of some bitfields that aren't used. A few may need to be readded.
2009-07-01 22:16:51 -07:00
Gabe Black
7172e26cc4
ARM: Add a findLsbSet function and use it to implement clz.
2009-07-01 22:16:36 -07:00
Gabe Black
f5141c23fd
ARM: Add defaults for DataOp flag code.
2009-07-01 22:16:19 -07:00
Gabe Black
22a1ac22f4
ARM: Get rid of the val2 variable.
2009-07-01 22:16:05 -07:00
Gabe Black
ce9cb1ecb5
ARM: Centralize the declaration of resTemp.
2009-07-01 22:15:39 -07:00
Gabe Black
776a06fd39
ARM: Add a DataImmOp format similar to DataOp.
2009-07-01 22:12:10 -07:00
Gabe Black
4f98171479
ARM: Decode some media instructions. These are untested.
2009-07-01 22:11:54 -07:00
Gabe Black
b8f064c88c
ARM: Use the new DataOp format to simplify the decoder.
2009-07-01 22:11:39 -07:00
Gabe Black
f409d7819d
ARM: Add in some new artificial fields that make decoding a little easier.
2009-07-01 22:11:27 -07:00
Gabe Black
1f0c0a6688
ARM: Recognize the IntRegs trace flag.
2009-07-01 22:11:12 -07:00
Gabe Black
065cb59427
ARM: Add a DataOp format so data op definitions can be aggregated.
2009-07-01 22:10:58 -07:00
Gabe Black
1ea14b8fac
ARM: Show more information when disassembling data processing intstructions.
...
This will need more work, but it should be a lot closer.
2009-06-27 00:30:23 -07:00
Gabe Black
56f1845471
ARM: Show branch targets relative to the nearest symbol.
2009-06-27 00:29:30 -07:00
Gabe Black
a4ac3fad7a
ARM: Write a function for printing mnemonics and predicates.
2009-06-27 00:29:12 -07:00
Gabe Black
38d8bc64ba
ARM: Fill out the printReg function.
2009-06-26 22:01:34 -07:00
Jack Whitman
7b5386d390
ARM: Fix signed multiply long and add some unimplemented loads.
2009-06-24 21:22:52 -07:00
Jack Whitman
853a0858f3
ARM: Link register is trashed by non-executed branch and link operations.
2009-06-24 21:22:46 -07:00
Jack Whitman
6dd4272804
ARM: Added unimplemented load/store multiple instructions.
2009-06-23 23:23:25 -07:00
Gabe Black
d744525273
ARM: Simplify some utility functions.
2009-06-21 22:51:13 -07:00
Gabe Black
5c2a362cb7
ARM: Move util functions out of the isa desc.
2009-06-21 22:50:33 -07:00
Gabe Black
d4a03f1900
ARM: Simplify the ISA desc by pulling some classes out of it.
2009-06-21 17:21:25 -07:00
Gabe Black
2a39570b78
ARM: Remove the currently unecessary FPAOp class.
2009-06-21 17:14:51 -07:00
Gabe Black
d1d733f636
ARM: Make inst bitfields accessible outside of the isa desc.
2009-06-21 16:41:21 -07:00
Gabe Black
47e71d674a
ARM: Don't downconvert ExtMachInsts to MachInsts.
2009-06-21 16:41:07 -07:00
Gabe Black
f1657a890e
BitUnion: Add more constiness.
2009-06-21 16:40:33 -07:00
Gabe Black
7e4f132369
ARM: Get rid of a few more unused operands.
2009-06-21 09:48:51 -07:00
Gabe Black
4415e2dcd6
ARM: Get rid of unnecessary Re operand.
2009-06-21 09:48:44 -07:00
Gabe Black
7d4ef8a398
ARM: Clear out some inherited hangers on in util.isa and utility.hh.
2009-06-21 09:43:55 -07:00
Gabe Black
5bc1373050
ARM: Get rid of unnecessary fp_enable_checks.
2009-06-21 09:41:04 -07:00
Gabe Black
3964709711
ARM: Adjust simplify rotate_imm slightly.
2009-06-21 09:38:54 -07:00
Gabe Black
c20ce20e4c
ARM: Make the isa parser aware that CPSR is being used.
2009-06-21 09:37:41 -07:00
Gabe Black
71e0d1ded2
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 09:21:07 -07:00
Gabe Black
19a1966079
ARM: Get rid of unused postacc_code.
2009-06-21 09:16:55 -07:00
Nathan Binkert
e1eacc8d92
scons: Make shared library builds work again
...
Compile gzstream as position independent code
use the PIC version of date for shared libs...oops
2009-06-12 21:19:16 -07:00
Nathan Binkert
d3d8a5a83b
copyright: I missed some copyrights during ruby integration
2009-06-10 00:41:56 -07:00
Gabe Black
b394242240
ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params.
2009-06-09 23:41:45 -07:00
Gabe Black
c913c64be2
ARM: Add a memory_barrier function to the "comm page".
...
This function doesn't actually provide a memory barrier (I don't think they're
implemented) and instead just returns.
2009-06-09 23:41:35 -07:00
Gabe Black
3ff1e922c2
ARM: Add a cmpxchg implementation to the "comm page".
...
This implementation does what it's supposed to (I think), but it's not atomic
and doesn't have memory barriers like the kernel's version.
2009-06-09 23:41:03 -07:00
Gabe Black
37ac2871d5
ARM: Implement TLS. This is not tested.
2009-06-09 23:39:07 -07:00
Gabe Black
5daeefc505
ARM: Make ArmLinuxProcess understand "ARM private" system calls.
2009-06-09 23:38:50 -07:00
Gabe Black
fbf4dc9da2
ARM: Update the kernel version M5 reports to 2.6.16.19
2009-06-09 23:37:41 -07:00
Nathan Binkert
baa0d695b2
cleanup: Make use of types properly and make the loop a little more clear.
2009-06-05 17:01:19 -07:00
Nathan Binkert
c76a8b1c15
scons: Make it so that the processing of trace flags does not depend on order
2009-06-05 15:20:09 -07:00
Nathan Binkert
a01437ab03
types: need typename keyword to get the type.
2009-06-05 11:40:02 -07:00
Nathan Binkert
6faf377b53
types: clean up types, especially signed vs unsigned
2009-06-04 23:21:12 -07:00
Nathan Binkert
4e34266245
move: put predictor includes and cc files into the same place
...
--HG--
rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc
rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh
rename : src/cpu/btb.cc => src/cpu/pred/btb.cc
rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh
rename : src/cpu/ras.cc => src/cpu/pred/ras.cc
rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh
rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc
rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
2009-06-04 21:50:20 -07:00
Nathan Binkert
e30c62ad99
style: cleanup style
2009-06-04 21:41:46 -07:00
Nathan Binkert
b08c361911
swig: %include Event before PythonEvent so python gets the subclass correct.
...
Before this change, some versions of swig would cause PythonEvent to be
derived from object instead of Event
2009-06-01 16:38:57 -07:00
Nathan Binkert
a0104b6ff6
request: add accessor and constructor for setting time other than curTick
2009-05-29 15:30:16 -07:00
Gabe Black
7f50ea05ac
X86: Keep track of more descriptor state to accomodate KVM.
2009-05-28 23:27:56 -07:00
Nathan Binkert
47877cf2db
types: add a type for thread IDs and try to use it everywhere
2009-05-26 09:23:13 -07:00
Gabe Black
d93392df28
X86: Really set up the GDT and various hidden/visible segment registers.
2009-05-26 02:23:08 -07:00
Steve Reinhardt
b3d0a01eb3
igbe: Fix descriptor cache bug.
2009-05-20 21:52:32 -07:00
Nathan Binkert
8d2e51c7f5
includes: sort includes again
2009-05-17 14:34:52 -07:00
Nathan Binkert
709d859530
includes: use base/types.hh not inttypes.h or stdint.h
2009-05-17 14:34:51 -07:00
Nathan Binkert
eef3a2e142
types: Move stuff for global types into src/base/types.hh
...
--HG--
rename : src/sim/host.hh => src/base/types.hh
2009-05-17 14:34:50 -07:00
Nathan Binkert
cbf237897f
stats: tidy up the Distribution type a little bit
2009-05-13 07:18:03 -07:00
Nathan Binkert
cfa9c78100
stats: fancy is a bad name
2009-05-13 07:18:02 -07:00
Nathan Binkert
74c595d739
stats: clean up the code for printing stats
2009-05-13 07:18:01 -07:00
Korey Sewell
97a04b16eb
mips-merge: merge hello world regress for inorder cpu
...
w/latest changes
2009-05-13 02:02:05 -04:00
Nathan Binkert
5207586b26
ruby: deal with printf warnings and convert some to cprintf
2009-05-12 22:33:05 -07:00
Nathan Binkert
016d472c46
ruby: remove random uint typedef and use unsigned
2009-05-12 22:33:05 -07:00
Nathan Binkert
7389dc63b2
ruby: Make ruby's Map use hashmap.hh to simplify things.
2009-05-12 22:33:05 -07:00
Nathan Binkert
82c9e6a5fc
gcc: work around a bogus gcc error
2009-05-12 22:33:05 -07:00
Nathan Binkert
0c2b9cf90d
slicc: work around improper initialization of a global in slicc.
2009-05-12 22:33:05 -07:00
Nathan Binkert
d923ce0f8c
slicc: clean up the slicc environment so things build properly on mac.
2009-05-12 22:33:04 -07:00
Korey Sewell
1f4c954590
inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp
...
Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change
to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU
2009-05-13 01:26:46 -04:00
Korey Sewell
bc69e7947c
arch-mips: add regWidth constant to float regfile
2009-05-13 01:26:38 -04:00
Korey Sewell
a032d91016
cpus: add InOrderCPU to default build
...
regressions need this so they build the model
2009-05-12 20:55:21 -04:00
Korey Sewell
5d810c30e6
alpha-isa: add mt.hh so it can compile with inorder
2009-05-12 20:18:34 -04:00
Korey Sewell
6c88730540
inorder-resources: delete events
...
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
2009-05-12 15:01:16 -04:00
Korey Sewell
db2b721380
inorder-tlb-cunit: merge the TLB as implicit to any memory access
...
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
2009-05-12 15:01:16 -04:00
Korey Sewell
3a057bdbb1
inorder-tlb: squash insts in TLB correctly
...
TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly
* * *
2009-05-12 15:01:16 -04:00
Korey Sewell
f1c97e830b
inorder-faults: ignore unalign translation faults for prefetches
2009-05-12 15:01:16 -04:00
Korey Sewell
fe4cd9847d
inorder-stc: update interface to handle store conditionals
2009-05-12 15:01:15 -04:00
Korey Sewell
6211fe5d2e
inorder-float: Fix storage of FP results
...
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access
because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from
the actual floating point register file, the model can figure out what it needs to store
2009-05-12 15:01:15 -04:00
Korey Sewell
3603dd25ef
inorder-fetch: update model to use predecoder
2009-05-12 15:01:15 -04:00
Korey Sewell
c9a03f549b
inorder-mem: clean up allocation/deletion of requests/packets
...
* * *
2009-05-12 15:01:15 -04:00
Korey Sewell
1c7e988272
inorder-mem: skeleton support for prefetch/writehints
2009-05-12 15:01:15 -04:00
Korey Sewell
f41df0ee08
inorder-o3: allow both to compile together
...
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
2009-05-12 15:01:14 -04:00
Korey Sewell
5127ea226a
inorder-unified-tlb: use unified TLB instead of old TLB model
2009-05-12 15:01:14 -04:00
Korey Sewell
98b1452058
inorder-miscregs: Fix indexing for misc. reg operands and update result-types for better tracing of these types of values
2009-05-12 15:01:14 -04:00
Korey Sewell
2012202b06
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
...
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
2009-05-12 15:01:14 -04:00
Korey Sewell
b569f8f0ed
inorder-bpred: edits to handle non-delay-slot ISAs
...
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
2009-05-12 15:01:14 -04:00
Korey Sewell
1c8dfd9254
inorder-alpha-port: initial inorder support of ALPHA
...
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
2009-05-12 15:01:13 -04:00
Korey Sewell
63db33c4b1
isa-parser: made a few changes, but not author-worthy
2009-05-12 15:01:13 -04:00
Nathan Binkert
f21e80ec72
ruby: assert(false) should be panic.
...
This also fixes some compiler warnings
2009-05-11 16:32:32 -07:00
Nathan Binkert
c2c68c66b7
stats: remove a few compat leftovers
2009-05-11 11:18:09 -07:00
Nathan Binkert
20f1da8b96
python: pull out common code from main that processes arguments
2009-05-11 11:18:09 -07:00
Nathan Binkert
5de3b2b6f0
stats: forgot an include for the mysql stuff
2009-05-11 11:18:09 -07:00
Nathan Binkert
5b752c1e31
scons: add include guards to info.hh
2009-05-11 11:18:09 -07:00
Nathan Binkert
cf6b4ef734
ruby: add RUBY sticky option that must be set to add ruby to the build
...
Default is false
2009-05-11 10:38:46 -07:00
Daniel Sanchez
93f2f69657
ruby: Working M5 interface and updated Ruby interface.
...
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>
RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-11 10:38:46 -07:00
Steve Reinhardt
ebf2f5aadd
ruby: Check stderr and not stdin before hanging on an assert.
2009-05-11 10:38:46 -07:00
Polina Dudnik
7769cc9092
ruby: decommission code
...
1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory
2009-05-11 10:38:46 -07:00
Derek Hower
0ccf8f35a5
ruby: removed dead functions from the sequencer
2009-05-11 10:38:46 -07:00
Polina Dudnik
29f82f265a
ruby: Removed g_SIMULATING flag
...
1. removed checks from tester files
2. removed else clause in Sequencer and DirectoryMemory else clause is
needed by the tester, it is up to Derek to revive it elsewhere when he
gets to it
Also:
1. Changed m_entries in DirectoryMemory to a map
2. And replaced SIMICS_read_physical_memory with a call to now-dummy
Derek's-to-be readPhysMem function
2009-05-11 10:38:46 -07:00
Polina Dudnik
b271090923
ruby: Remove transactional access types (e.g. LD_XACT) from CacheRequestType
...
1. Modified enumeration
2. Also modified profiler
3. Remove transactions from Tester
4. Edited XACT_MEM out of Synthetic Driver
2009-05-11 10:38:46 -07:00
Polina Dudnik
9f34659c52
ruby: reordered Debug and RubyConfig::init to fix segfault
...
due to uninitialized output file pointer.
2009-05-11 10:38:46 -07:00
Dan Gibson
8cbf8df5b7
ruby: Disabled RubyEventQueue's deletion of its home-grown priority heap.
...
Temporarily to fix unusual memory problem.
2009-05-11 10:38:46 -07:00
Nathan Binkert
7311fd7182
ruby: Migrate all of ruby and slicc to SCons.
...
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.
2009-05-11 10:38:46 -07:00
Nathan Binkert
e40b8e34c8
ruby: clean up a few warnings
2009-05-11 10:38:45 -07:00
Dan Gibson
8b9f70b9e4
ruby: Fixed some unresolved references.
2009-05-11 10:38:45 -07:00
Nathan Binkert
24da30e317
ruby: Make ruby #includes use full paths to the files they're including.
...
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
2009-05-11 10:38:45 -07:00
Dan Gibson
d8c592a05d
ruby: remove unnecessary code.
...
1) Removing files from the ruby build left some unresovled
symbols. Those have been fixed.
2) Most of the dependencies on Simics data types and the simics
interface files have been removed.
3) Almost all mention of opal is gone.
4) Huge chunks of LogTM are now gone.
5) Handling 1-4 left ~hundreds of unresolved references, which were
fixed, yielding a snowball effect (and the massive size of this
delta).
2009-05-11 10:38:45 -07:00
Derek Hower
6ceaffd724
ruby: Cleaned up sequencer. Removed LogTM specific code.
2009-05-11 10:38:45 -07:00
Derek Hower
3d2acc547c
ruby: added Packet interface to makeRequest and isReady.
...
Also pushed Packet usage into the Sequencer
2009-05-11 10:38:45 -07:00
Nathan Binkert
e1915f16d1
ruby: fold the debugging options into Debug.cc
2009-05-11 10:38:45 -07:00
Derek Hower
6e8373fad6
ruby: Renamed Ruby's EventQueue to RubyEventQueue
...
--HG--
rename : src/mem/ruby/eventqueue/EventQueue.cc => src/mem/ruby/eventqueue/RubyEventQueue.cc
rename : src/mem/ruby/eventqueue/EventQueue.hh => src/mem/ruby/eventqueue/RubyEventQueue.hh
rename : src/mem/ruby/eventqueue/EventQueueNode.cc => src/mem/ruby/eventqueue/RubyEventQueueNode.cc
rename : src/mem/ruby/eventqueue/EventQueueNode.hh => src/mem/ruby/eventqueue/RubyEventQueueNode.hh
2009-05-11 10:38:45 -07:00
Daniel Sanchez
ab5e4a22b3
ruby: Removed System name clash by renaming ruby's System to RubySystem
2009-05-11 10:38:44 -07:00
Nathan Binkert
84a18e7fdc
ruby: rename config.include to config.hh and clean up the macro stuff.
...
I did the macro cleanup because I was worried that the SCons scanner
would get confused. This code will hopefully go away soon anyway.
--HG--
rename : src/mem/ruby/config/config.include => src/mem/ruby/config/config.hh
2009-05-11 10:38:44 -07:00
Nathan Binkert
b05da09cd6
ruby: strip out some unused defines
2009-05-11 10:38:44 -07:00
Nathan Binkert
2f30950143
ruby: Import ruby and slicc from GEMS
...
We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
2009-05-11 10:38:43 -07:00
Korey Sewell
c70241810d
cpus: fix cpu progress event
...
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-05-05 02:51:31 -04:00
Nathan Binkert
dc35d2f125
scons: re-work the *Source functions to take more information.
...
Start by turning all of the *Source functions into classes
so we can do more calculations and more easily collect the data we need.
Add parameters to the new classes for indicating what sorts of flags the
objects should be compiled with so we can allow certain files to be compiled
without Werror for example.
2009-05-04 16:58:24 -07:00
Gabe Black
7146eb79f1
X86: Precompute the default and alternate address and operand size and the stack size.
2009-04-26 16:49:24 -07:00
Gabe Black
b6bfe8af26
X86: Split out the internal memory space from the regular translate() and precompute mode.
2009-04-26 16:48:44 -07:00
Gabe Black
4ee34dfb4e
X86: Centralize updates to the handy M5 reg.
2009-04-26 16:47:48 -07:00
Gabe Black
06b3e3c303
X86: Implement lowest priority interrupts more correctly.
...
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
2009-04-26 02:09:54 -07:00
Gabe Black
2f34a7eaeb
X86: Tell the function that sends int messages who to send to instead of figuring it out itself.
2009-04-26 02:09:27 -07:00
Gabe Black
88ab4bb257
X86: Make the local APICs register themselves with the IO APIC.
...
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
2009-04-26 02:09:13 -07:00
Gabe Black
c5e2cf841d
X86: Record the initial APIC ID which identifies an APIC in M5.
...
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
2009-04-26 02:06:21 -07:00
Gabe Black
8d84f81e70
X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.
2009-04-26 02:04:32 -07:00
Gabe Black
9d0fa27d09
SPARC: Tighten up the clone system call and SPARCs copyRegs.
2009-04-24 23:11:21 -07:00
Steve Reinhardt
7c056e44e5
request: reorganize flags to group related flags together.
2009-04-23 06:44:32 -07:00
Gabe Black
ee7055c289
X86: Put the StoreCheck flag with the others, and don't collide with other flags.
2009-04-23 01:43:00 -07:00
Nathan Binkert
b4816037ba
stats: expose statistics to python
2009-04-22 13:38:01 -07:00
Nathan Binkert
aa9b4e6a68
stats: Move flags into info.hh and use base/flags.hh to manage the flags
2009-04-22 13:38:01 -07:00
Nathan Binkert
8c3eb1a192
stats: Shuffle around info stuff so it can be accessed separately
2009-04-22 13:38:00 -07:00
Nathan Binkert
4d9f25b75c
stats: Rename the info classes to hopefully make things a bit clearer
...
FooInfoBase became FooInfo
FooInfo became FooInfoProxy
2009-04-22 13:38:00 -07:00
Nathan Binkert
ca3d82b38a
stats: remove simplescalar compatibility for printing
2009-04-22 10:25:14 -07:00
Nathan Binkert
61a68371be
stats: fix initialization bug in distribution text output
2009-04-22 06:44:29 -07:00
Steve Reinhardt
e7fa4f2f8e
i8254xGBe: major style overhaul.
...
Moved DescCache template functions from .hh to .cc file.
Also fixed lots of line-wrapping problems, and some irregular indentation.
2009-04-22 01:58:53 -04:00
Steve Reinhardt
6629d9b2bc
mem: use single BadAddr responder per system.
...
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Nathan Binkert
4d001e43da
Automated merge with ssh://m5sim.org//repo/m5
2009-04-21 16:04:55 -07:00
Nathan Binkert
fcc142463d
pseudo: only include kernel stats if FULL_SYSTEM.
2009-04-21 15:40:26 -07:00
Nathan Binkert
43c7698f49
arm: include missing file for arm
2009-04-21 15:40:26 -07:00
Nathan Binkert
50f1570352
arm: Unify the ARM tlb. We forgot about this when we did the rest.
...
This code compiles, but there are no tests still
2009-04-21 15:40:25 -07:00
Steve Reinhardt
03b3925e58
syscall_emul: style fixes (mostly wrapping overly long lines)
2009-04-21 08:17:36 -07:00
Steve Reinhardt
52b6764f31
syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.
2009-04-21 08:17:36 -07:00
Daniel Sanchez
b0e9654f86
Commit m5threads package.
...
This patch adds limited multithreading support in syscall-emulation
mode, by using the clone system call. The clone system call works
for Alpha, SPARC and x86, and multithreaded applications run
correctly in Alpha and SPARC.
2009-04-21 08:17:36 -07:00
Nathan Binkert
b0489d18ed
SCons: Export export_vars so SConsopts files can add to them
2009-04-21 08:17:36 -07:00
Steve Reinhardt
97b6947eb7
Minor tweaks for future Ruby compatibility.
2009-04-21 08:17:36 -07:00
Steve Reinhardt
eb3b6935d3
request: add PREFETCH flag.
2009-04-21 08:17:10 -07:00
Steve Reinhardt
3083268d60
request: rename INST_READ to INST_FETCH.
2009-04-20 18:54:02 -07:00
Steve Reinhardt
7f8ea68a30
request: split public and private flags into separate fields.
...
This frees up needed space for more public flags. Also:
- remove unused Request accessor methods
- make Packet use public Request accessors, so it need not be a friend
2009-04-20 18:40:00 -07:00
Gabe Black
9e9a34fed1
Mem: Fill out the comment that describes the LOCKED request flag.
2009-04-19 22:00:24 -07:00
Gabe Black
bd6f2bb538
Mem: Change isLlsc to isLLSC.
2009-04-19 21:44:15 -07:00
Gabe Black
089b384086
X86: Fix the functions that manipulate large bit arrays in the local APIC.
2009-04-19 13:47:15 -07:00
Gabe Black
eee74ba427
X86: Fix up a copyright.
2009-04-19 13:17:35 -07:00
Gabe Black
6910baa015
X86: Fix how the TLB handles the storecheck flag.
2009-04-19 04:57:51 -07:00
Gabe Black
0a6ff60caa
X86: Recognize and handle the lock legacy prefix.
2009-04-19 04:57:28 -07:00
Gabe Black
61edc9ba66
X86: Implement a locking version of XADD.
2009-04-19 04:56:49 -07:00
Gabe Black
209cfc89fd
X86: Implement a locking version of BTC.
2009-04-19 04:56:45 -07:00
Gabe Black
e475cf85f0
X86: Implement a locking version of BTR.
2009-04-19 04:56:43 -07:00
Gabe Black
43f58927d6
X86: Implement a locking version of CMPXCHG.
2009-04-19 04:56:40 -07:00
Gabe Black
b493906eb9
X86: Implement a locking version of BTS.
2009-04-19 04:56:36 -07:00
Gabe Black
985d959ea6
X86: Implement a locking version of DEC.
2009-04-19 04:56:34 -07:00
Gabe Black
4f2d4f466a
X86: Implement a locking version of INC.
2009-04-19 04:56:31 -07:00
Gabe Black
2394f73f90
X86: Implement a locking version of NEG.
2009-04-19 04:56:28 -07:00
Gabe Black
9b9b7a412c
X86: Implement a locking version of NOT.
2009-04-19 04:56:25 -07:00
Gabe Black
b8f81c62a2
X86: Implement a locking version of XCHG.
2009-04-19 04:56:22 -07:00
Gabe Black
750f5a0a67
X86: Implement a locking version of XOR.
2009-04-19 04:56:20 -07:00
Gabe Black
cfb289ebeb
X86: Implement a locking version of SUB.
2009-04-19 04:56:16 -07:00
Gabe Black
789b3191b9
X86: Implement a locking version of AND.
2009-04-19 04:56:14 -07:00
Gabe Black
e742cad6f4
X86: Implement a locking version of SBB.
2009-04-19 04:56:11 -07:00
Gabe Black
193265c6e5
X86: Implement a locking version of ADC.
2009-04-19 04:56:08 -07:00
Gabe Black
2f607b882c
X86: Implement a locking version of OR.
2009-04-19 04:56:06 -07:00
Gabe Black
a7f79c9049
X86: Implement a locking version of ADD.
2009-04-19 04:56:02 -07:00
Gabe Black
d90456a486
X86: Implement the stul microop.
...
This microop does a store and unlocks the requested address. The RISC86
microop ISA doesn't seem to have an equivalent to this, so I'm guessing that
the store following an ldstl is automatically unlocking. We don't do it this
way for performance reasons since the behavior is the same.
2009-04-19 04:55:58 -07:00
Gabe Black
d2554ff030
X86: Implement the ldstl microop.
...
This microop does a load, checks that a store would succeed, and locks the
requested address.
2009-04-19 04:55:43 -07:00
Gabe Black
1a8a765a5c
CPUs: Make the atomic CPU support locked memory accesses.
2009-04-19 04:50:07 -07:00
Gabe Black
742c3f045e
Memory: Add a LOCKED flag back in for x86 style locking.
2009-04-19 04:39:25 -07:00
Gabe Black
3e5f487663
Memory: Rename LOCKED for load locked store conditional to LLSC.
2009-04-19 04:25:01 -07:00
Gabe Black
ca85981478
SE mode: Make keeping track of the number of syscalls less hacky.
2009-04-19 04:15:32 -07:00
Gabe Black
e174239bd8
X86: Mask the PIC at startup to avoid a glitch which causes an NMI.
2009-04-19 04:15:06 -07:00
Gabe Black
5f164ba720
X86: Actually handle 16 bit mode modrm.
2009-04-19 04:14:31 -07:00
Gabe Black
93cccf7d19
X86: Make the TEST instruction set all the flags it's supposed to.
2009-04-19 04:14:16 -07:00
Gabe Black
f82c123242
X86: Implement broadcast IPIs.
2009-04-19 04:14:01 -07:00
Gabe Black
829e424353
X86: Fix the ordering of the vendor string reported by CPUID.
2009-04-19 04:13:45 -07:00
Gabe Black
8b2ac20753
X86: Keep track of what the initial count value was in the LAPIC timer.
2009-04-19 03:56:57 -07:00
Gabe Black
18b3863127
X86: Only recognize the first startup IPI after INIT or reset.
2009-04-19 03:56:36 -07:00
Gabe Black
4d32cd10ce
X86: Use recvResponse to implement the idle bit in the Local APIC ICR.
2009-04-19 03:56:24 -07:00
Gabe Black
bdda224d41
X86: Add a function which gets called when an interrupt message has been delivered.
2009-04-19 03:54:11 -07:00
Gabe Black
3031af21c7
X86: Fix the flags for interrupt response messages.
2009-04-19 03:53:29 -07:00
Gabe Black
3eed59768c
X86: Explicitly use the right width in a few places that need a 64 bit value.
2009-04-19 03:47:59 -07:00
Gabe Black
8761057c78
X86: Keep track of the pioAddr for the local APIC.
2009-04-19 03:47:12 -07:00
Gabe Black
038225a6ca
X86: Implement far jmp.
2009-04-19 03:42:41 -07:00
Gabe Black
3b1b21cb15
X86: Some segment selectors can be used when "NULL".
2009-04-19 03:41:10 -07:00
Gabe Black
a0cc081997
X86: Fix a bug in the chks microop where it ignored that it found a fault.
2009-04-19 03:40:08 -07:00
Gabe Black
f2ff5b9249
X86: Make the interrupt entering microcode record the value to use, not actually use it.
2009-04-19 03:36:57 -07:00
Gabe Black
35eea4191b
X86: LEA calculates an address before segmentation.
2009-04-19 03:24:51 -07:00
Gabe Black
bdd55ec8b6
X86: Implement the save machine status word instruction (SMSW).
2009-04-19 03:22:38 -07:00
Gabe Black
d86cd1d2a0
X86: Implement the load machine status word instruction (LMSW).
2009-04-19 03:17:14 -07:00
Gabe Black
eba640c963
X86: Only use %eax to select a function and look like we support sse2.
2009-04-19 03:11:24 -07:00
Gabe Black
27e54982b4
X86: Fix the mov to segment selector in real mode instruction microcode.
2009-04-19 03:08:40 -07:00
Gabe Black
633c96bd85
X86: The startup IPI delivery mode is not reserved.
2009-04-19 03:01:46 -07:00
Gabe Black
08f021aad0
X86: Implement the STARTUP IPI.
2009-04-19 02:56:03 -07:00
Gabe Black
d277feb925
X86: Implement the INIT IPI.
2009-04-19 02:53:00 -07:00
Gabe Black
a340b214cf
X86: Fix the halt microop.
2009-04-19 02:51:09 -07:00
Gabe Black
641513fe08
X86: Start implementing the interrupt command register in the local APIC.
2009-04-19 02:43:22 -07:00
Gabe Black
9549694ecd
X86: Make code that sends an interrupt from the IO APIC available for IPIs.
2009-04-19 02:42:19 -07:00
Gabe Black
d10195b1a4
CPU: If the simple CPU is already idle, just return from suspendContext, don't assert.
2009-04-19 02:23:29 -07:00
Gabe Black
05b5861419
X86: Condense the startupCPU code.
2009-04-19 02:20:57 -07:00
Gabe Black
f668340f2c
X86: Set the local APIC ID to something meaningful.
2009-04-19 02:16:49 -07:00
Gabe Black
79a3a6aecb
X86: Don't pretend to be an AMD CPU any more. We're not good enough at it.
2009-04-19 02:06:51 -07:00
Korey Sewell
d8a34a9745
mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS.
2009-04-18 10:42:29 -04:00
Korey Sewell
e501e1af54
mips-syscall: mark with correct flag. \nMIPS was using wrong serialization flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall
2009-04-18 10:42:29 -04:00
Korey Sewell
5c1742b822
o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly
2009-04-18 10:42:29 -04:00
Korey Sewell
cc9e834e93
mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg Calculations
2009-04-18 10:42:28 -04:00
Steve Reinhardt
14808ecac9
o3, inorder: fix FS bug due to initializing ThreadState to Halted.
...
For some reason o3 FS init() only called initCPU if the thread state
was Suspended, which was no longer the case. There's no apparent
reason to check, so I whacked the test completely rather than
changing the check to Halted.
The inorder init() was also updated to be symmetric, though the
previous code was just a fancy no-op.
2009-04-17 16:54:58 -07:00
Steve Reinhardt
b146131d18
o3: handle fetch with no active threads correctly.
...
This situation can arise now on the first fetch cycle after
the last active thread is halted. It seems easy enough to
deal with when it happens rather than trying to avoid it.
2009-04-15 23:12:00 -07:00
Steve Reinhardt
bb974d5a47
o3: fix {read,set}ArchFloatReg* functions.
...
Register indices were not being calculated properly.
2009-04-15 23:10:43 -07:00
Steve Reinhardt
7617dcf736
ThreadState: initialize status to Halted in constructor.
...
This provides a common initial status for all threads independent
of CPU model (unlike the prior situation where CPUs initialized
threads to inconsistent states).
This mostly matters for SE mode; in FS mode, ISA-specific startupCPU()
methods generally handle boot-time initialization of thread contexts
(since the right thing to do is ISA-dependent).
2009-04-15 13:18:24 -07:00
Steve Reinhardt
8882dc1283
Get rid of the Unallocated thread context state.
...
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
- InOrderCPU's setThreadRescheduleCondition.
- ThreadContext::exit(). This function was there to avoid terminating
simulation when one thread out of a multi-thread workload exits, but we
need to find a better (non-cpu-centric) way.
2009-04-15 13:13:47 -07:00
Gabe Black
5c79191603
X86: Fix minor bug in the page table walker from TLB shuffling.
2009-04-13 04:14:15 -07:00
Nathan Binkert
c87c9950df
stats: disallow duplicate statistic names.
2009-04-08 22:22:50 -07:00
Nathan Binkert
18a30524d6
alpha: get rid of all turbolaser remnants
2009-04-08 22:22:49 -07:00
Nathan Binkert
e0de2c3443
tlb: More fixing of unified TLB
2009-04-08 22:21:27 -07:00
Gabe Black
7b5a96f06b
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
2009-04-08 22:21:27 -07:00
Gabe Black
d080581db1
Merge ARM into the head. ARM will compile but may not actually work.
2009-04-06 10:19:36 -07:00
Stephen Hines
7a7c4c5fca
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
Ali Saidi
639cb0a42d
CPA: Fix a typo that managed to sneak in.
2009-03-25 20:06:54 -04:00
Nathan Binkert
4eea8acaf2
stats: fix compiler error
2009-03-16 15:16:58 -07:00
Steve Reinhardt
758bfe4eb5
cache: set dirty bit on swaps (oops!)
2009-03-11 23:05:26 -07:00
Steve Reinhardt
61ff48a1f8
cpu: fix minor endian issue with trace output
...
(no functional change)
2009-03-11 23:05:24 -07:00
Steve Reinhardt
a94c68228a
prefetch: don't panic on requests w/o contextID (e.g., writebacks).
2009-03-10 17:37:15 -07:00
Nathan Binkert
ac64586a99
build: fix compiler warnings in g++ 3.4
2009-03-07 21:34:50 -08:00
Steve Reinhardt
4f1855484c
Fix up regression execution to better handle tests that end abnormally.
...
E.g., mark aborts due to assertion failures as failed tests,
but those that get killed by the user as needing to be rerun, etc.
2009-03-07 16:58:51 -08:00
Nathan Binkert
ac7bda0212
stats: fix duplicate statistics names.
...
This generally requires providing a more meaningful name() function for a
class.
2009-03-07 14:30:54 -08:00
Nathan Binkert
fcaf1b74b0
stats: cleanup text output stuff and fix mysql output
2009-03-07 14:30:53 -08:00
Nathan Binkert
66a85b54e2
build: fix errors for compilers other than g++ 4.3
2009-03-07 14:30:52 -08:00
Nathan Binkert
6f787e3d36
stats: create an enable phase, and a prepare phase.
...
Enable more or less takes the place of check, but also allows stats to
do some other configuration. Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python code.
2009-03-05 19:09:53 -08:00
Nathan Binkert
9f45fbaaa6
stats: clean up how templates are used on the data side.
...
This basically works by taking advantage of the curiously recurring template
pattern in an intelligent way so as to reduce the number of lines of code
and hopefully make things a little bit clearer.
2009-03-05 19:09:53 -08:00
Nathan Binkert
cc95b57390
stats: Fix all stats usages to deal with template fixes
2009-03-05 19:09:53 -08:00
Nathan Binkert
c7e82f965f
stats: remove the template wart left over from the ancient binning stuff
2009-03-05 19:09:53 -08:00
Nathan Binkert
244c2a517a
stats: stick the distribution's fancy parameter into the parameters structure.
2009-03-05 19:09:53 -08:00
Nathan Binkert
e19fd1d521
stats: Add a wrapper class for the information side of things.
...
This provides an easy way to provide the callbacks into the data side
of things from the info side of things. Rename Wrap to DataWrap so it
is more easily distinguishable from InfoWrap
2009-03-05 19:09:53 -08:00
Nathan Binkert
c7bd1ec261
stats: better naming of template parameters for the wrapper stuff
...
Parent and Child are bad names. Derived and Base are better.
2009-03-05 19:09:53 -08:00
Nathan Binkert
2dd5a5b3dc
stats: get rid of meaningless uses of virtual
2009-03-05 19:09:53 -08:00
Nathan Binkert
ec209953e7
stats: miscellaneous cleanup
2009-03-05 19:09:53 -08:00
Nathan Binkert
a767819d56
serialize: Allow floats and doubles to be serialized
2009-03-05 19:09:53 -08:00
Steve Reinhardt
e3d6e8882e
Get rid of 'using namespace' declarations in headers.
2009-03-05 17:15:31 -08:00
Korey Sewell
9e1dc7f205
InOrderCPU: Clean up Constructors to initialize variables correctly (i.e. in a way for the compiler to play *nice*)
2009-03-04 22:37:45 -05:00
Korey Sewell
7c8d544216
Give each resource in InOrder it's own TraceFlag instead of just standard 'Resource' flag
2009-03-04 13:17:09 -05:00
Korey Sewell
30cd2d21fa
Remove unused functions/comments cluttering up the code.
2009-03-04 13:17:08 -05:00
Korey Sewell
f69b018571
make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads
2009-03-04 13:17:07 -05:00
Korey Sewell
f98e9161a8
InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use.
2009-03-04 13:17:05 -05:00
Korey Sewell
846f953c2b
Give TimeBuffer an ID that can be set. Necessary because InOrder uses generic stages so w/o an ID there is no way to differentiate buffers when debugging
2009-03-04 13:16:49 -05:00
Korey Sewell
e4aa4ca40c
use numCycles instead of simTicks to determine CPI stat in InOrder
2009-03-04 13:16:48 -05:00
Steve Reinhardt
9ee8e685a4
O3: Make numThreads error message more helpful.
2009-03-04 09:25:53 -05:00
Steve Reinhardt
307905095c
Fix Num_Syscall_Descs check bug in non-x86 ISAs.
...
(See cset d35d2b28df38 for x86 fix.)
2009-02-28 20:14:22 -05:00
Nathan Binkert
4523741c1c
quell gcc 4.3 warning
2009-02-27 17:29:58 -08:00
Gabe Black
b69a9ad45a
X86: Install the exit system call.
2009-02-27 09:26:41 -08:00
Gabe Black
9265b3d598
X86: Install the 32 bit write system call.
2009-02-27 09:26:32 -08:00
Gabe Black
b36f28472d
X86: Implement shrd.
2009-02-27 09:26:26 -08:00
Gabe Black
2fe87e62ba
X86: Add a structure to allow mapping between the host and guest fstat formats.
2009-02-27 09:26:17 -08:00
Gabe Black
27b751ec46
X86: Don't treat the REX prefixes as prefixes in 32 bit modes. These are inc/dec instructions.
2009-02-27 09:26:09 -08:00
Gabe Black
aa51c01d69
X86: Set address size to 64 bits when generating addresses internally.
2009-02-27 09:26:01 -08:00
Gabe Black
db3c51d3a0
X86: Add a vsyscall page for 32 bit processes to use.
2009-02-27 09:25:51 -08:00
Gabe Black
c3d7d7ed0e
X86: Implement sysenter as a system call interface.
2009-02-27 09:25:43 -08:00
Gabe Black
5c1cc99d48
X86: Add a 32 bit mmap2 system call.
2009-02-27 09:25:33 -08:00
Gabe Black
04dbed79f8
X86: Install a 32 bit fstat64 system call.
2009-02-27 09:25:26 -08:00
Gabe Black
8a1eb7e8be
X86: Take address size into account when computing an effective address.
2009-02-27 09:25:16 -08:00
Gabe Black
1d18eb9043
X86: Make instructions that use intseg preserve all 8 bytes of their addresses.
2009-02-27 09:25:02 -08:00
Gabe Black
79bc1b3740
X86: Fix a decoder bug and add in some missing instructions.
2009-02-27 09:24:10 -08:00
Gabe Black
3dfa564e70
X86: Respect segment override prefixes even when there's no ModRM byte.
2009-02-27 09:23:58 -08:00
Gabe Black
9dfa3f7f73
X86: Fix segment limit checks.
2009-02-27 09:23:50 -08:00
Gabe Black
9491debaa6
X86: Implement the 32 bit set_thread_area system call.
2009-02-27 09:23:42 -08:00
Gabe Black
1786f20058
X86: Set an initial value for the LDT selector.
2009-02-27 09:23:27 -08:00
Gabe Black
e23d688d8f
X86: Set up a space for a GDT in SE so we can set up TLS or LDT segments.
2009-02-27 09:23:17 -08:00
Gabe Black
281ef8111a
X86: Compute shift instruction flags correctly.
2009-02-27 09:23:00 -08:00
Gabe Black
14fc06640e
X86: Install some 32 bit system calls.
2009-02-27 09:22:50 -08:00
Gabe Black
6ca53f8675
X86: Handle 32 bit system call arguments.
2009-02-27 09:22:30 -08:00
Gabe Black
9a000c5173
Processes: Make getting and setting system call arguments part of a process object.
2009-02-27 09:22:14 -08:00
Gabe Black
60aab03e85
X86: Implement the int system call interface in the decoder.
2009-02-27 09:21:58 -08:00
Gabe Black
05de9f4e2c
X86: Distinguish the width of values on the stack between 32 and 64 bit processes.
2009-02-27 09:21:36 -08:00