sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
10900 commits 2 branches 0 tags 204 MiB
Commit graph

370 commits

Author SHA1 Message Date
Andrew Bardsley
5d0b25ba3f cpu: Minor CPU add regression tests for ARM and ALPHA 
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
 2014-07-23 16:09:05 -05:00
Steve Reinhardt
040fa23d01 stats: update for syscall DPRINTF change 
Only printing one rather than two args for the ignored syscall
warning means the count of register accesses has changed on
a few runs.  Oddly only Alpha Tru64 seems to have any ignored
syscalls in the regression tests.
 2014-07-19 19:04:58 -07:00
Steve Reinhardt
5b08e211ab stats: update for O3 changes 
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
 2014-06-22 14:33:09 -07:00
Nilay Vaish
2a8088f5ae stats: changes due to recent o3 patch. 2014-05-24 21:30:46 -05:00
Nilay Vaish
0aaa7d10d8 stats: changes due to o3 cpu and ruby message buffer patches 2014-05-23 06:07:02 -05:00
Steve Reinhardt
72403cb595 tests: update t1000 & pc-switcheroo-full stats 
committed reference config.json files too
 2014-05-12 17:22:17 -04:00
Andreas Hansson
57e5401d95 stats: Bump stats for the fixes, and mostly DRAM controller changes 2014-05-09 18:58:50 -04:00
Andreas Hansson
0c75581d03 stats: updates for pc-switcheroo-full due to o3 smt fix 2014-04-22 03:12:15 -04:00
Nilay Vaish
3bc5cfcc03 stats: updates due to o3 smt fix 
+ changes to one ruby regression config.ini file.
 2014-04-19 09:16:14 -05:00
Andreas Hansson
8b4b1dcb86 stats: Update stats for DRAM changes 
This patch updates the stats to reflect the changes to the DRAM
controller.
 2014-03-23 11:12:19 -04:00
Nilay Vaish
83d09ee215 stats: updates due to changes to ruby config scripts 
These updates to ruby regression stats are due to renaming piobus to iobus
and dropping piobus in the se mode.
 2014-03-20 09:16:35 -05:00
Nilay Vaish
3b404fb1a0 stats: updates due to changes to ruby pio access handling 2014-02-23 19:16:16 -06:00
Andreas Hansson
fd9343eb85 arm: Bump stats after FS config script update 
This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).
 2014-02-19 07:59:46 -05:00
Nilay Vaish
5abbb84f02 stats: updates due to branch predictor warming 2014-02-16 11:40:34 -06:00
Nilay Vaish
fa0ff1c902 stats: update sparc fs stats 2014-01-27 13:30:37 -06:00
Ali Saidi
cfb805cc71 stats: update stats for ARMv8 changes 2014-01-24 15:29:34 -06:00
Ali Saidi
f3585c841e stats: update stats for cache occupancy and clock domain changes 2014-01-24 15:29:33 -06:00
Nilay Vaish
fc6d1f3399 stats: updates due to changes to ruby 2014-01-10 16:19:58 -06:00
Nilay Vaish
bb6d7d402b ruby: rename MESI_CMP_directory to MESI_Two_Level 
This is because the next patch introduces a three level hierarchy.

--HG--
rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level
rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py
rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm
rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm
rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm
rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm
rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm
rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
 2014-01-04 00:03:33 -06:00
Nilay Vaish
e6008b6bc1 stats: updates due to bug fixed in mesi coherence protocol 2013-12-26 15:18:58 -06:00
Nilay Vaish
2823982a3c stats: updates due to changes to ticksToCycles() 2013-11-26 17:05:25 -06:00
Andreas Hansson
ccfdc533b9 stats: Bump stats to match DRAM controller changes 
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
 2013-11-01 11:56:34 -04:00
Steve Reinhardt
10e6450120 test: update stats 
Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
 2013-10-16 10:44:12 -04:00
Andreas Hansson
a44bb59192 stats: Bump pc-simple-timing-ruby stats 
This patch simply brings the stats for the pc-simple-timing-ruby
regression up to date. The particular regression seems to give
different results on different systems unfortunately, and this update
reflects the current behaviour on zizzer.
 2013-10-09 04:41:19 -04:00
Andreas Sandberg
0438bf9389 stats: Update x86 stats after x87 fixes 
The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
 2013-10-02 11:03:38 +02:00
Steve Reinhardt
fbc1feb39a tests: update reference outputs 
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes.  There are a few stats.txt updates too, but
they are in the minority.
 2013-09-28 15:25:17 -04:00
Nilay Vaish
143dfa31df stats: update sparc fs due to recent changes to memory class. 2013-09-15 13:45:59 -05:00
Nilay Vaish
ff87a0dd9c stats: ruby: updates due to recent changes. 2013-09-06 16:21:36 -05:00
Nilay Vaish
e351e846e3 stats: update ruby.stats, config.ini files for x86 fs test 2013-08-20 11:32:33 -05:00
Andreas Hansson
b63631536d stats: Cumulative stats update 
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
 2013-08-19 03:52:36 -04:00
Nilay Vaish
ba440f1cb9 regressions: update a couple stats.txt 
The statistics for 30.eio-mp, pc-simple-timing-ruby tests are being updated
to incorporate the changes due to recent patches.
 2013-07-02 10:11:00 -05:00
Andreas Hansson
5a15909bac stats: Update stats for monitor, cache and bus changes 
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
 2013-06-27 05:49:51 -04:00
Andreas Hansson
4de3205afa config: Add a BaseSESystem builder for re-use in regressions 
This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).

The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.

Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.
 2013-06-27 05:49:49 -04:00
Andreas Hansson
f821c5472b tests: Prune 00.gzip from the regressions 
This patch prunes the 00.gzip regressions with the main motivation
being that it adds little (or no) coverage and requires a substantial
amount of run time.

A complete regression run, including compilation from a clean repo, is
almost 20% faster(!).
 2013-06-27 05:49:49 -04:00
Nilay Vaish
a1e18270a1 stats: updates due to changes to stat collection in ruby 2013-06-25 00:32:04 -05:00
Andreas Hansson
beee57070a stats: Bump x86 stats 
This patch bumps the x86 stats to reflect the recent fixes.
 2013-06-24 14:17:22 -04:00
Nilay Vaish
247e4e9ab4 stats: updates due to changes to ruby 
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
 2013-06-10 06:46:20 -05:00
Andreas Hansson
74553c7d3f stats: Update the stats to reflect bus and memory changes 
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
 2013-05-30 12:54:18 -04:00
Nilay Vaish
af2e83c7f1 x86, regressions: updates stats 
This is due to op class, function call, walker patches.
 2013-05-21 11:41:27 -05:00
Nilay Vaish
5b49c3d255 stats: updates statistics for ruby regressions 2013-05-21 11:32:57 -05:00
Nilay Vaish
c2d799c6b0 x86: regressions: add switcher full test 2013-04-23 00:03:09 -05:00
Nilay Vaish
3295e6de69 x86, stats: updates due to lret bugfix 2013-04-23 00:03:05 -05:00
Ali Saidi
d69f904a18 stats: Update stats for O3 switching fix. 2013-04-22 13:20:33 -04:00
Andreas Hansson
5dd23833fd stats: Update stats for ldr_ret_uop (changeset 35198406dd72) 
This patch merely bumps the stats to match the changes introduced in
changeset 35198406dd72.
 2013-04-19 09:04:42 -04:00
Andreas Hansson
c704b7be16 stats: Bump the vortex stats to match latest behaviour 
This patch bumps the stats for the failing vortex o3 regression.
 2013-04-16 06:26:49 -04:00
Nilay Vaish
26e96b90e1 regressions: updates due to changes to o3 cpu, x86 memory map 2013-03-29 14:05:36 -05:00
Nilay Vaish
4646369afd regressions: update due to cache latency fix 2013-03-27 18:36:21 -05:00
Andreas Hansson
a84d026538 stats: Update stats for cache retry event check 
This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
 2013-03-26 14:47:03 -04:00
Andreas Hansson
08f7a8bc00 stats: Update stats to reflect bus retry changes 
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
 2013-03-26 14:46:49 -04:00
Nilay Vaish
04fe6b486a regressions: updates to config.ini for ruby tests 2013-03-22 17:21:25 -05:00
Nilay Vaish
53a0597805 regressions: x86: stats updates due to new x87 insts 2013-03-11 17:45:09 -05:00
Ali Saidi
09b2430e95 stats: update patches for branch predictor and fetch updates. 2013-03-04 23:33:47 -05:00
Andreas Hansson
cb9e208a4c stats: Update stats to reflect SimpleDRAM changes 
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
 2013-03-01 13:20:30 -05:00
Ali Saidi
a86f67e706 stats: more zizzer stats fun 2013-02-19 09:53:07 -05:00
Ali Saidi
bd31a5dc18 stats: update regressions for o3 changes in renaming and translation. 2013-02-15 17:40:14 -05:00
Nilay Vaish
1962e9262d regressions: update stats due to changes to ruby 2013-02-10 21:43:23 -06:00
Andreas Hansson
fce3433b2e stats: Update stats for regressions using SimpleDDR3 
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
 2013-01-31 07:49:16 -05:00
Andreas Hansson
093fc6707f stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3 
This patch bumps the stats for 20.parser for ARM o3-timing to reflect
a namechange of the branch predictor.
 2013-01-28 07:44:26 -05:00
Nilay Vaish
9bc132e473 regressions: update stats due to branch predictor changes 
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
 2013-01-24 12:29:00 -06:00
Nilay Vaish
4526f33062 x86 regressions: updates due to new instructions and cpuid 2013-01-15 07:43:23 -06:00
Nilay Vaish
7fdcfdf08b regressions: update stats due to changes in ruby obj hierarchy 2013-01-14 10:20:16 -06:00
Andreas Hansson
5b90902437 stats: Bump failing x86 regression stats 
This patch bumps the stats of mcf and twolf for the o3 CPU such that
the regressions pass.
 2013-01-14 10:23:54 -05:00
Ali Saidi
fbeced6135 stats: update stats for previous six changes 2013-01-08 08:54:16 -05:00
Ali Saidi
9f15510c2c stats: update stats for previous changes. 2013-01-07 13:05:54 -05:00
Andreas Sandberg
5fb00e1df6 tests: Add CPU switching tests 
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:

 * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
 * realview-switcheroo-atomic -- ARM system (atomic<->atomic)
 * realview-switcheroo-timing -- ARM system (timing<->timing)
 * realview-switcheroo-o3 -- ARM system (O3<->O3)
 * realview-switcheroo-full -- ARM system (atomic, timing, O3)

Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.

The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
 2013-01-07 13:05:52 -05:00
Nilay Vaish
5ebe3210d8 regressions: stats update due to decoder changes 2013-01-04 19:00:48 -06:00
Nilay Vaish
1945f9963d x86 regressions: stats update due to new x87 instructions 2012-12-30 12:45:52 -06:00
Nilay Vaish
3b01edd7fa arm regressions: updates to config.ini, terminal files 2012-12-12 09:51:55 -06:00
Nilay Vaish
141ee38794 regressions: stats update due to stats from ruby prefetcher 2012-12-11 10:06:01 -06:00
Ali Saidi
1dbf9bb4ca update stats for preceeding changes 2012-11-02 11:50:06 -05:00
Andreas Hansson
10b70d5452 stats: Update stats for unified cache configuration 
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
 2012-10-30 09:35:32 -04:00
Nilay Vaish
30f5bf5f23 regressions: update stats for ruby fs test 2012-10-27 16:05:06 -05:00
Andreas Hansson
b387d8e213 stats: Update the stats to reflect the 1GHz default system clock 
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
 2012-10-25 13:15:59 -04:00
Andreas Hansson
8fe556338d stats: Update stats to reflect use of SimpleDRAM 
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
 2012-10-25 13:14:42 -04:00
Andreas Hansson
a4329af937 stats: Update stats for DMA port send 
This patch updates the stats after removing the zero-time send used in
the DMA port.
 2012-10-23 04:49:48 -04:00
Andreas Hansson
37ded2c2cc stats: Update t1000 stats to match recent changes 
This patch brings the t1000 stats up to date.
 2012-10-23 04:24:32 -04:00
Andreas Hansson
d52adc4eb6 Stats: Update stats for cache timings in cycles 
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
 2012-10-15 08:12:21 -04:00
Andreas Hansson
54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width 
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
 2012-10-15 08:09:54 -04:00
Andreas Hansson
a850fc916f Stats: Update stats for use of two-level builder 
This patch updates the name of the l2 stats.
 2012-10-15 08:08:06 -04:00
Nilay Vaish
0de0ce106a Regression Tests: Update statistics 2012-10-02 14:35:46 -05:00
Ali Saidi
91e74beee6 ARM: update stats for bp and squash fixes. 2012-09-25 11:49:41 -05:00
Andreas Hansson
d2b57a7473 Stats: Update stats to reflect SimpleMemory bandwidth 
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
 2012-09-18 10:30:04 -04:00
Andreas Hansson
ae1652b813 Stats: Remove the reference stats that are no longer present 
This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.
 2012-09-13 08:02:55 -04:00
Nilay Vaish
fe5deb4a22 x86 Regressions: Update stats due to register predication 2012-09-11 09:34:40 -05:00
Nilay Vaish
5cdf221d8c Regression: Updates due to changes to Ruby memory controller 2012-09-10 12:44:03 -05:00
Andreas Hansson
d628344574 Device: Update stats for PIO and PCI latency change 
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
 2012-09-10 11:57:37 -04:00
Andreas Hansson
fb5dd28420 Checker: Bump the realview-o3-checker regression 
This patch bumps the stats for the realview-o3-checker after fixing
the checker CPU in the previous patch.
 2012-08-28 14:30:25 -04:00
Nilay Vaish
1032bc72ed Regression: updates ruby.stats due to change in virtual network 2012-08-25 15:49:07 -05:00
Ali Saidi
73e9e923d0 stats: Update stats for syscall emulation Linux kernel changes. 2012-08-15 10:38:05 -04:00
Ali Saidi
6a70ef30a3 stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update 2012-07-30 12:11:25 -04:00
Ali Saidi
b1a58933e0 stats: update stats for icache change not allowing dirty data 2012-07-27 16:08:05 -04:00
Nilay Vaish
2590a7dd0a Regression: Update stats due to changes to x86 cpuid instruction 2012-07-22 20:31:24 -05:00
Nilay Vaish
019ced8d85 Regression: update ruby.stats file 2012-07-12 08:39:20 -05:00
Andreas Hansson
fda338f8d3 Stats: Updates due to bus changes 
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
 2012-07-09 12:35:41 -04:00
Ali Saidi
3965ecc36b Stats: Update stats for RAS and LRU fixes. 2012-06-29 11:19:03 -04:00
Ali Saidi
c49e739352 all: Update stats for memory per master and total fix. 2012-06-05 01:23:16 -04:00
Gabe Black
6437f3f4ee X86: Update stats for the CPUID change. 2012-06-04 10:43:11 -07:00
Andreas Hansson
fb9bfb9cfc Stats: Fix stats to match output after changeset 8800b05e1cb3 
This patch updates the stats for parser to be aligned with the most
up-to-date behaviour. Somehow the wrong results got committed as part
of 8800b05e1cb3 (see details below) when fixing the no_value -> nan
stats.

changeset:   8983:8800b05e1cb3
user:        Nathan Binkert <nate@binkert.org>
summary:     stats: update stats for no_value -> nan
 2012-05-09 11:52:14 -07:00
Nilay Vaish
0bff8eb210 X86 Regression: update stats due to cc register split 2012-05-22 11:38:04 -05:00
Ali Saidi
e62beaaa8f ARM: update stats for clock frequency fix. 2012-05-10 18:04:29 -05:00