tests: update reference outputs
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
This commit is contained in:
Steve Reinhardt
parent
e5c319db43
commit
fbc1feb39a
392 changed files with 38342 additions and 16308 deletions
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@ -8,10 +8,11 @@ time_sync_spin_threshold=100000000
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[system]
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type=LinuxAlphaSystem
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children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
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children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
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boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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clock=1000
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/dist/m5/system/binaries/console
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init_param=0
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kernel=/dist/m5/system/binaries/vmlinux
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@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
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[system.bridge]
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type=Bridge
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clock=1000
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clk_domain=system.clk_domain
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delay=50000
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ranges=8796093022208:18446744073709551615
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req_size=16
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@ -44,6 +45,11 @@ resp_size=16
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master=system.iobus.slave[0]
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slave=system.membus.master[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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voltage_domain=system.voltage_domain
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[system.cpu0]
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type=DerivO3CPU
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children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
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@ -58,7 +64,7 @@ backComSize=5
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branchPred=system.cpu0.branchPred
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cachePorts=200
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checker=Null
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clock=500
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clk_domain=system.cpu_clk_domain
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commitToDecodeDelay=1
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commitToFetchDelay=1
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commitToIEWDelay=1
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@ -137,11 +143,9 @@ RASSize=16
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choiceCtrBits=2
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choicePredictorSize=8192
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globalCtrBits=2
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globalHistoryBits=13
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globalPredictorSize=8192
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instShiftAmt=2
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localCtrBits=2
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localHistoryBits=11
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localHistoryTableSize=2048
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localPredictorSize=2048
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numThreads=1
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@ -149,10 +153,10 @@ predType=tournament
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[system.cpu0.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -163,12 +167,21 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu0.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.dcache_port
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mem_side=system.toL2Bus.slave[1]
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[system.cpu0.dcache.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu0.dtb]
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type=AlphaTLB
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size=64
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@ -438,10 +451,10 @@ opLat=3
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[system.cpu0.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -452,12 +465,21 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu0.icache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.icache_port
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mem_side=system.toL2Bus.slave[0]
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[system.cpu0.icache.tags]
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type=LRU
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assoc=1
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu0.interrupts]
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type=AlphaInterrupts
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@ -485,7 +507,7 @@ backComSize=5
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branchPred=system.cpu1.branchPred
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cachePorts=200
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checker=Null
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clock=500
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clk_domain=system.cpu_clk_domain
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commitToDecodeDelay=1
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commitToFetchDelay=1
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commitToIEWDelay=1
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@ -564,11 +586,9 @@ RASSize=16
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choiceCtrBits=2
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choicePredictorSize=8192
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globalCtrBits=2
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globalHistoryBits=13
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globalPredictorSize=8192
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instShiftAmt=2
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localCtrBits=2
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localHistoryBits=11
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localHistoryTableSize=2048
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localPredictorSize=2048
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numThreads=1
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@ -576,10 +596,10 @@ predType=tournament
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[system.cpu1.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -590,12 +610,21 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu1.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.dcache_port
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mem_side=system.toL2Bus.slave[3]
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[system.cpu1.dcache.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu1.dtb]
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type=AlphaTLB
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size=64
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@ -865,10 +894,10 @@ opLat=3
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[system.cpu1.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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@ -879,12 +908,21 @@ prefetcher=Null
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response_latency=2
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size=32768
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system=system
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tags=system.cpu1.icache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.icache_port
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mem_side=system.toL2Bus.slave[2]
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[system.cpu1.icache.tags]
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type=LRU
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assoc=1
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=32768
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[system.cpu1.interrupts]
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type=AlphaInterrupts
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@ -898,6 +936,11 @@ size=48
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[system.cpu1.tracer]
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type=ExeTracer
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[system.cpu_clk_domain]
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type=SrcClockDomain
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clock=500
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voltage_domain=system.voltage_domain
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[system.disk0]
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type=IdeDisk
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children=image
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@ -944,8 +987,7 @@ sys=system
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[system.iobus]
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type=NoncoherentBus
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block_size=64
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clock=1000
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clk_domain=system.clk_domain
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header_cycles=1
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use_default_range=true
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width=8
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@ -955,10 +997,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
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[system.iocache]
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type=BaseCache
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children=tags
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addr_ranges=0:134217727
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assoc=8
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block_size=64
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clock=1000
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clk_domain=system.clk_domain
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forward_snoops=false
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hit_latency=50
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is_top_level=true
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@ -969,18 +1011,27 @@ prefetcher=Null
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response_latency=50
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size=1024
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system=system
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tags=system.iocache.tags
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.iobus.master[29]
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mem_side=system.membus.slave[2]
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[system.l2c]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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[system.iocache.tags]
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type=LRU
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assoc=8
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block_size=64
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clock=500
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clk_domain=system.clk_domain
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hit_latency=50
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size=1024
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[system.l2c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=8
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=20
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is_top_level=false
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@ -991,17 +1042,25 @@ prefetcher=Null
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response_latency=20
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size=4194304
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system=system
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tags=system.l2c.tags
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.toL2Bus.master[0]
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mem_side=system.membus.slave[1]
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[system.l2c.tags]
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type=LRU
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assoc=8
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=20
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size=4194304
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[system.membus]
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type=CoherentBus
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children=badaddr_responder
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block_size=64
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clock=1000
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clk_domain=system.clk_domain
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header_cycles=1
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system=system
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use_default_range=false
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@ -1012,7 +1071,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
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[system.membus.badaddr_responder]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=0
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pio_latency=100000
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@ -1030,19 +1089,24 @@ pio=system.membus.default
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[system.physmem]
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type=SimpleDRAM
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activation_limit=4
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addr_mapping=openmap
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addr_mapping=RaBaChCo
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banks_per_rank=8
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burst_length=8
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channels=1
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clock=1000
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conf_table_reported=false
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clk_domain=system.clk_domain
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conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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devices_per_rank=8
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in_addr_map=true
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lines_per_rowbuffer=32
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mem_sched_policy=frfcfs
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null=false
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page_policy=open
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCL=13750
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tRCD=13750
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@ -1053,7 +1117,6 @@ tWTR=7500
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tXAW=40000
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write_buffer_size=32
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write_thresh_perc=70
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zero=false
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port=system.membus.master[1]
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[system.simple_disk]
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@ -1076,8 +1139,7 @@ port=3456
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[system.toL2Bus]
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type=CoherentBus
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block_size=64
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clock=500
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clk_domain=system.cpu_clk_domain
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header_cycles=1
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system=system
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use_default_range=false
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@ -1093,7 +1155,7 @@ system=system
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[system.tsunami.backdoor]
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type=AlphaBackdoor
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clock=1000
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clk_domain=system.clk_domain
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cpu=system.cpu0
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disk=system.simple_disk
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pio_addr=8804682956800
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@ -1105,7 +1167,7 @@ pio=system.iobus.master[24]
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[system.tsunami.cchip]
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type=TsunamiCChip
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clock=1000
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clk_domain=system.clk_domain
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pio_addr=8803072344064
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pio_latency=100000
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system=system
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@ -1152,7 +1214,7 @@ SubClassCode=0
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SubsystemID=0
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SubsystemVendorID=0
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VendorID=4107
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clock=2000
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clk_domain=system.clk_domain
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config_latency=20000
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dma_data_free=false
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dma_desc_free=false
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@ -1183,7 +1245,7 @@ pio=system.iobus.master[27]
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[system.tsunami.fake_OROM]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8796093677568
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pio_latency=100000
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@ -1200,7 +1262,7 @@ pio=system.iobus.master[8]
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[system.tsunami.fake_ata0]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848432
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pio_latency=100000
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@ -1217,7 +1279,7 @@ pio=system.iobus.master[19]
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[system.tsunami.fake_ata1]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848304
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pio_latency=100000
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@ -1234,7 +1296,7 @@ pio=system.iobus.master[20]
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[system.tsunami.fake_pnp_addr]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848569
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pio_latency=100000
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@ -1251,7 +1313,7 @@ pio=system.iobus.master[9]
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[system.tsunami.fake_pnp_read0]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848451
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pio_latency=100000
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@ -1268,7 +1330,7 @@ pio=system.iobus.master[11]
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[system.tsunami.fake_pnp_read1]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848515
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pio_latency=100000
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@ -1285,7 +1347,7 @@ pio=system.iobus.master[12]
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[system.tsunami.fake_pnp_read2]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848579
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pio_latency=100000
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@ -1302,7 +1364,7 @@ pio=system.iobus.master[13]
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[system.tsunami.fake_pnp_read3]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848643
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pio_latency=100000
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@ -1319,7 +1381,7 @@ pio=system.iobus.master[14]
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[system.tsunami.fake_pnp_read4]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
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fake_mem=false
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pio_addr=8804615848707
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pio_latency=100000
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@ -1336,7 +1398,7 @@ pio=system.iobus.master[15]
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[system.tsunami.fake_pnp_read5]
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type=IsaFake
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clock=1000
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clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -1353,7 +1415,7 @@ pio=system.iobus.master[16]
|
|||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -1370,7 +1432,7 @@ pio=system.iobus.master[17]
|
|||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -1387,7 +1449,7 @@ pio=system.iobus.master[18]
|
|||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -1404,7 +1466,7 @@ pio=system.iobus.master[10]
|
|||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -1421,7 +1483,7 @@ pio=system.iobus.master[7]
|
|||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -1438,7 +1500,7 @@ pio=system.iobus.master[2]
|
|||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -1455,7 +1517,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -1472,7 +1534,7 @@ pio=system.iobus.master[4]
|
|||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -1489,7 +1551,7 @@ pio=system.iobus.master[5]
|
|||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -1506,7 +1568,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
|
|
@ -1553,7 +1615,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
|
|
@ -1570,7 +1632,7 @@ pio=system.iobus.master[25]
|
|||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -1582,7 +1644,7 @@ pio=system.iobus.master[22]
|
|||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1592,7 +1654,8 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
|
|
@ -1601,7 +1664,7 @@ pio=system.iobus.default
|
|||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1609,3 +1672,7 @@ system=system
|
|||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 28 2013 09:43:29
|
||||
gem5 started Mar 28 2013 09:43:43
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 10:33:13
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 110215000
|
||||
Exiting @ tick 1900727697500 because m5_exit instruction encountered
|
||||
info: Launching CPU 1 @ 125036000
|
||||
Exiting @ tick 1902738973500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
memcluster 1, usage 0, start 392, end 16384
|
||||
freeing pages 1069:16384
|
||||
reserving pages 1069:1070
|
||||
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
|
||||
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
||||
Built 1 zonelists
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
|
|
|||
|
|
@ -8,10 +8,11 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
|
||||
children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
|
|
@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
|
|
@ -44,6 +45,11 @@ resp_size=16
|
|||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
||||
|
|
@ -58,7 +64,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -137,11 +143,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -149,10 +153,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -163,12 +167,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
|
@ -438,10 +451,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -452,12 +465,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -470,10 +492,10 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -484,16 +506,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -504,6 +534,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
|
|
@ -550,8 +585,7 @@ sys=system
|
|||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -561,10 +595,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -575,17 +609,25 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -596,7 +638,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -614,19 +656,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -637,7 +684,6 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
|
|
@ -666,7 +712,7 @@ system=system
|
|||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
|
|
@ -678,7 +724,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -725,7 +771,7 @@ SubClassCode=0
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=2000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
|
|
@ -756,7 +802,7 @@ pio=system.iobus.master[27]
|
|||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
|
|
@ -773,7 +819,7 @@ pio=system.iobus.master[8]
|
|||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
|
|
@ -790,7 +836,7 @@ pio=system.iobus.master[19]
|
|||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
|
|
@ -807,7 +853,7 @@ pio=system.iobus.master[20]
|
|||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
|
|
@ -824,7 +870,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
|
|
@ -841,7 +887,7 @@ pio=system.iobus.master[11]
|
|||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
|
|
@ -858,7 +904,7 @@ pio=system.iobus.master[12]
|
|||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
|
|
@ -875,7 +921,7 @@ pio=system.iobus.master[13]
|
|||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
|
|
@ -892,7 +938,7 @@ pio=system.iobus.master[14]
|
|||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
|
|
@ -909,7 +955,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -926,7 +972,7 @@ pio=system.iobus.master[16]
|
|||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -943,7 +989,7 @@ pio=system.iobus.master[17]
|
|||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -960,7 +1006,7 @@ pio=system.iobus.master[18]
|
|||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -977,7 +1023,7 @@ pio=system.iobus.master[10]
|
|||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -994,7 +1040,7 @@ pio=system.iobus.master[7]
|
|||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -1011,7 +1057,7 @@ pio=system.iobus.master[2]
|
|||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -1028,7 +1074,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -1045,7 +1091,7 @@ pio=system.iobus.master[4]
|
|||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -1062,7 +1108,7 @@ pio=system.iobus.master[5]
|
|||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -1079,7 +1125,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
|
|
@ -1126,7 +1172,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
|
|
@ -1143,7 +1189,7 @@ pio=system.iobus.master[25]
|
|||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -1155,7 +1201,7 @@ pio=system.iobus.master[22]
|
|||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1165,7 +1211,8 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
|
|
@ -1174,7 +1221,7 @@ pio=system.iobus.default
|
|||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1182,3 +1229,7 @@ system=system
|
|||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 23:18:16
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 10:33:00
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1854315933000 because m5_exit instruction encountered
|
||||
Exiting @ tick 1860200687500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
memcluster 1, usage 0, start 392, end 16384
|
||||
freeing pages 1069:16384
|
||||
reserving pages 1069:1070
|
||||
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
|
||||
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
Built 1 zonelists
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
|
|
|||
|
|
@ -8,10 +8,11 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxAlphaSystem
|
||||
children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
children=bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
|
|
@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
|
|
@ -44,12 +45,16 @@ resp_size=16
|
|||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -84,10 +89,10 @@ icache_port=system.cpu0.icache.cpu_side
|
|||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -98,22 +103,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -124,12 +138,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -145,10 +168,9 @@ type=ExeTracer
|
|||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
children=dtb isa itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -156,7 +178,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
interrupts=Null
|
||||
isa=system.cpu1.isa
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
|
|
@ -176,9 +198,6 @@ workload=
|
|||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=AlphaISA
|
||||
|
||||
|
|
@ -191,7 +210,7 @@ type=ExeTracer
|
|||
|
||||
[system.cpu2]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dtb fuPool interrupts isa itb tracer
|
||||
children=branchPred dtb fuPool isa itb tracer
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
|
|
@ -203,7 +222,7 @@ backComSize=5
|
|||
branchPred=system.cpu2.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -229,7 +248,7 @@ iewToCommitDelay=1
|
|||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
interrupts=system.cpu2.interrupts
|
||||
interrupts=Null
|
||||
isa=system.cpu2.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
|
|
@ -280,11 +299,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -557,9 +574,6 @@ issueLat=3
|
|||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu2.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu2.isa]
|
||||
type=AlphaISA
|
||||
|
||||
|
|
@ -570,6 +584,11 @@ size=48
|
|||
[system.cpu2.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.disk0]
|
||||
type=IdeDisk
|
||||
children=image
|
||||
|
|
@ -616,8 +635,7 @@ sys=system
|
|||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -627,10 +645,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -641,18 +659,27 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -663,17 +690,25 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -684,7 +719,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -702,19 +737,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -725,7 +765,6 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
|
|
@ -748,8 +787,7 @@ port=3456
|
|||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -765,7 +803,7 @@ system=system
|
|||
|
||||
[system.tsunami.backdoor]
|
||||
type=AlphaBackdoor
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu0
|
||||
disk=system.simple_disk
|
||||
pio_addr=8804682956800
|
||||
|
|
@ -777,7 +815,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -824,7 +862,7 @@ SubClassCode=0
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=4107
|
||||
clock=2000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
|
|
@ -855,7 +893,7 @@ pio=system.iobus.master[27]
|
|||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
|
|
@ -872,7 +910,7 @@ pio=system.iobus.master[8]
|
|||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
|
|
@ -889,7 +927,7 @@ pio=system.iobus.master[19]
|
|||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
|
|
@ -906,7 +944,7 @@ pio=system.iobus.master[20]
|
|||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
|
|
@ -923,7 +961,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
|
|
@ -940,7 +978,7 @@ pio=system.iobus.master[11]
|
|||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
|
|
@ -957,7 +995,7 @@ pio=system.iobus.master[12]
|
|||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
|
|
@ -974,7 +1012,7 @@ pio=system.iobus.master[13]
|
|||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
|
|
@ -991,7 +1029,7 @@ pio=system.iobus.master[14]
|
|||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
|
|
@ -1008,7 +1046,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
|
|
@ -1025,7 +1063,7 @@ pio=system.iobus.master[16]
|
|||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
|
|
@ -1042,7 +1080,7 @@ pio=system.iobus.master[17]
|
|||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
|
|
@ -1059,7 +1097,7 @@ pio=system.iobus.master[18]
|
|||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
|
|
@ -1076,7 +1114,7 @@ pio=system.iobus.master[10]
|
|||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
|
|
@ -1093,7 +1131,7 @@ pio=system.iobus.master[7]
|
|||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
|
|
@ -1110,7 +1148,7 @@ pio=system.iobus.master[2]
|
|||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
|
|
@ -1127,7 +1165,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
|
|
@ -1144,7 +1182,7 @@ pio=system.iobus.master[4]
|
|||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
|
|
@ -1161,7 +1199,7 @@ pio=system.iobus.master[5]
|
|||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
|
|
@ -1178,7 +1216,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
devicename=FrameBuffer
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
|
|
@ -1225,7 +1263,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
|
|
@ -1242,7 +1280,7 @@ pio=system.iobus.master[25]
|
|||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
frequency=976562500
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
|
|
@ -1254,7 +1292,7 @@ pio=system.iobus.master[22]
|
|||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1264,7 +1302,8 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.tsunami
|
||||
size=16777216
|
||||
|
|
@ -1273,7 +1312,7 @@ pio=system.iobus.default
|
|||
|
||||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
|
|
@ -1281,3 +1320,7 @@ system=system
|
|||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
|
|
@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -70,6 +71,11 @@ type=RawDiskImage
|
|||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
||||
|
|
@ -84,7 +90,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=system.cpu.checker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -163,11 +169,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -176,9 +180,8 @@ predType=tournament
|
|||
[system.cpu.checker]
|
||||
type=O3Checker
|
||||
children=dtb isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -213,7 +216,7 @@ walker=system.cpu.checker.dtb.walker
|
|||
|
||||
[system.cpu.checker.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
|
@ -243,7 +246,7 @@ walker=system.cpu.checker.itb.walker
|
|||
|
||||
[system.cpu.checker.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
|
@ -253,10 +256,10 @@ type=ExeTracer
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -267,12 +270,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -281,7 +293,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -551,10 +563,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -565,12 +577,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -599,17 +620,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -620,16 +641,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -640,14 +669,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -656,10 +689,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -670,28 +703,36 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -709,19 +750,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -732,8 +778,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
|
|
@ -746,16 +791,16 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -802,7 +847,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -820,7 +865,7 @@ pio=system.iobus.master[7]
|
|||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -834,7 +879,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -843,7 +888,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -860,7 +905,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Pl390
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -869,12 +914,12 @@ int_latency=10000
|
|||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -884,7 +929,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -894,7 +939,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -904,7 +949,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -918,7 +963,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -931,7 +976,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -944,23 +989,23 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -970,19 +1015,18 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -994,7 +1038,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -1007,7 +1051,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -1017,7 +1061,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -1027,7 +1071,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1037,7 +1081,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1047,7 +1091,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1061,7 +1105,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1074,7 +1118,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -1089,7 +1133,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1099,7 +1143,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1109,7 +1153,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1119,7 +1163,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1139,3 +1183,7 @@ frame_capture=false
|
|||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -11,23 +11,22 @@ warn: instruction 'mcr icialluis' unimplemented
|
|||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: 5695245000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
|
||||
warn: 5701912500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 5710381500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 5745167500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 5760086500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6281852500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: 6117297500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 6125706500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 6160975500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 6176055500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6715294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: 52533955500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 2291148077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: 51807478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: 2483713797000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2498675085000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2519713161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2520226805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2525908166000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2526415429500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2526974192500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2526975291500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
warn: 2474714862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2488540668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2489750451500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2510845218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2511359133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2517064152000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2517573704500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2518135055000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2518136146000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 28 2013 10:14:03
|
||||
gem5 started Mar 28 2013 10:14:28
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:14:57
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2533114761500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2524309551500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
|
|
@ -24,7 +25,7 @@ load_addr_mask=268435455
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -70,6 +71,11 @@ type=RawDiskImage
|
|||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
|
||||
|
|
@ -84,7 +90,7 @@ backComSize=5
|
|||
branchPred=system.cpu0.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -163,11 +169,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -175,10 +179,10 @@ predType=tournament
|
|||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -189,12 +193,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -203,7 +216,7 @@ walker=system.cpu0.dtb.walker
|
|||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -473,10 +486,10 @@ opLat=3
|
|||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -487,12 +500,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -521,7 +543,7 @@ walker=system.cpu0.itb.walker
|
|||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
|
@ -543,7 +565,7 @@ backComSize=5
|
|||
branchPred=system.cpu1.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -622,11 +644,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -634,10 +654,10 @@ predType=tournament
|
|||
|
||||
[system.cpu1.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -648,12 +668,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -662,7 +691,7 @@ walker=system.cpu1.dtb.walker
|
|||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[7]
|
||||
|
|
@ -932,10 +961,10 @@ opLat=3
|
|||
|
||||
[system.cpu1.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -946,12 +975,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -980,7 +1018,7 @@ walker=system.cpu1.itb.walker
|
|||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[6]
|
||||
|
|
@ -988,14 +1026,18 @@ port=system.toL2Bus.slave[6]
|
|||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -1004,10 +1046,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -1018,18 +1060,27 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -1040,28 +1091,36 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -1079,19 +1138,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -1102,8 +1166,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
|
|
@ -1116,16 +1179,16 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -1172,7 +1235,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -1190,7 +1253,7 @@ pio=system.iobus.master[7]
|
|||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -1204,7 +1267,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -1213,7 +1276,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -1230,7 +1293,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Pl390
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -1239,12 +1302,12 @@ int_latency=10000
|
|||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -1254,7 +1317,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -1264,7 +1327,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -1274,7 +1337,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -1288,7 +1351,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -1301,7 +1364,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -1314,23 +1377,23 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -1340,19 +1403,18 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -1364,7 +1426,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -1377,7 +1439,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -1387,7 +1449,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -1397,7 +1459,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1407,7 +1469,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1417,7 +1479,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1431,7 +1493,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1444,7 +1506,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -1459,7 +1521,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1469,7 +1531,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1479,7 +1541,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1489,7 +1551,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1505,8 +1567,7 @@ port=3456
|
|||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -1520,3 +1581,7 @@ frame_capture=false
|
|||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 28 2013 10:14:03
|
||||
gem5 started Mar 28 2013 10:17:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 07:58:48
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2602778916500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1104038330000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,13 +4,31 @@ sim_seconds 1.104038 # Nu
|
|||
sim_ticks 1104038330000 # Number of ticks simulated
|
||||
final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 80920 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 104171 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1450259542 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 402880 # Number of bytes of host memory used
|
||||
host_seconds 761.27 # Real time elapsed on the host
|
||||
host_inst_rate 67767 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 87238 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1214516577 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 404472 # Number of bytes of host memory used
|
||||
host_seconds 909.04 # Real time elapsed on the host
|
||||
sim_insts 61602211 # Number of instructions simulated
|
||||
sim_ops 79302243 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
|
||||
|
|
@ -467,24 +485,6 @@ system.physmem.writeRowHits 98940 # Nu
|
|||
system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 155904.23 # Average gap between requests
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 62410733 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 7306749 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 7306749 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
|
||||
Binary file not shown.
|
|
@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
|
|
@ -24,7 +25,7 @@ load_addr_mask=268435455
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -70,6 +71,11 @@ type=RawDiskImage
|
|||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
|
||||
|
|
@ -84,7 +90,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -163,11 +169,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -175,10 +179,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -189,12 +193,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -203,7 +216,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -473,10 +486,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -487,12 +500,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -521,17 +543,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -542,16 +564,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -562,14 +592,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -578,10 +612,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -592,28 +626,36 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -631,19 +673,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -654,8 +701,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
|
|
@ -668,16 +714,16 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -724,7 +770,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -742,7 +788,7 @@ pio=system.iobus.master[7]
|
|||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -756,7 +802,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -765,7 +811,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -782,7 +828,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Pl390
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -791,12 +837,12 @@ int_latency=10000
|
|||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -806,7 +852,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -816,7 +862,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -826,7 +872,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -840,7 +886,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -853,7 +899,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -866,23 +912,23 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -892,19 +938,18 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -916,7 +961,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -929,7 +974,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -939,7 +984,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -949,7 +994,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -959,7 +1004,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -969,7 +1014,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -983,7 +1028,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -996,7 +1041,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -1011,7 +1056,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1021,7 +1066,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1031,7 +1076,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1041,7 +1086,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1061,3 +1106,7 @@ frame_capture=false
|
|||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 28 2013 10:14:03
|
||||
gem5 started Mar 28 2013 10:15:55
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 07:59:33
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2533114761500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2524309551500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,13 +4,25 @@ sim_seconds 2.524310 # Nu
|
|||
sim_ticks 2524309551500 # Number of ticks simulated
|
||||
final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 81082 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 104330 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3394002800 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 397632 # Number of bytes of host memory used
|
||||
host_seconds 743.76 # Real time elapsed on the host
|
||||
host_inst_rate 66090 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 85039 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2766442256 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401396 # Number of bytes of host memory used
|
||||
host_seconds 912.48 # Real time elapsed on the host
|
||||
sim_insts 60305560 # Number of instructions simulated
|
||||
sim_ops 77596391 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||
|
|
@ -428,18 +440,6 @@ system.physmem.writeRowHits 94229 # Nu
|
|||
system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 158662.04 # Average gap between requests
|
||||
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 54917647 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
|
|
@ -24,7 +25,7 @@ load_addr_mask=268435455
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -70,12 +71,16 @@ type=RawDiskImage
|
|||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -110,10 +115,10 @@ icache_port=system.cpu0.icache.cpu_side
|
|||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -124,12 +129,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -138,17 +152,17 @@ walker=system.cpu0.dtb.walker
|
|||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -159,12 +173,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -193,7 +216,7 @@ walker=system.cpu0.itb.walker
|
|||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
|
@ -203,10 +226,9 @@ type=ExeTracer
|
|||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
children=dtb isa itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -214,7 +236,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
interrupts=Null
|
||||
isa=system.cpu1.isa
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
|
|
@ -238,13 +260,10 @@ walker=system.cpu1.dtb.walker
|
|||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
|
|
@ -270,7 +289,7 @@ walker=system.cpu1.itb.walker
|
|||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
|
|
@ -279,7 +298,7 @@ type=ExeTracer
|
|||
|
||||
[system.cpu2]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dtb fuPool interrupts isa itb tracer
|
||||
children=branchPred dtb fuPool isa itb tracer
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
|
|
@ -291,7 +310,7 @@ backComSize=5
|
|||
branchPred=system.cpu2.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -317,7 +336,7 @@ iewToCommitDelay=1
|
|||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
interrupts=system.cpu2.interrupts
|
||||
interrupts=Null
|
||||
isa=system.cpu2.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
|
|
@ -368,11 +387,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -386,7 +403,7 @@ walker=system.cpu2.dtb.walker
|
|||
|
||||
[system.cpu2.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
|
|
@ -653,9 +670,6 @@ issueLat=3
|
|||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu2.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu2.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
|
|
@ -681,21 +695,25 @@ walker=system.cpu2.itb.walker
|
|||
|
||||
[system.cpu2.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu2.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -704,10 +722,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -718,18 +736,27 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -740,28 +767,36 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -779,19 +814,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -802,8 +842,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
|
|
@ -816,16 +855,16 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -872,7 +911,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -890,7 +929,7 @@ pio=system.iobus.master[7]
|
|||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -904,7 +943,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -913,7 +952,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -930,7 +969,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Pl390
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -939,12 +978,12 @@ int_latency=10000
|
|||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -954,7 +993,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -964,7 +1003,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -974,7 +1013,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -988,7 +1027,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -1001,7 +1040,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -1014,23 +1053,23 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -1040,19 +1079,18 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -1064,7 +1102,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -1077,7 +1115,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -1087,7 +1125,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -1097,7 +1135,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1107,7 +1145,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1117,7 +1155,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1131,7 +1169,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1144,7 +1182,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -1159,7 +1197,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1169,7 +1207,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1179,7 +1217,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1189,7 +1227,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1205,8 +1243,7 @@ port=3456
|
|||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -1220,3 +1257,7 @@ frame_capture=false
|
|||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
|
|
@ -24,7 +25,7 @@ load_addr_mask=268435455
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -70,6 +71,11 @@ type=RawDiskImage
|
|||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
|
||||
|
|
@ -84,7 +90,7 @@ backComSize=5
|
|||
branchPred=system.cpu0.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -163,11 +169,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -175,10 +179,10 @@ predType=tournament
|
|||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -189,12 +193,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -203,7 +216,7 @@ walker=system.cpu0.dtb.walker
|
|||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
|
@ -473,10 +486,10 @@ opLat=3
|
|||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -487,12 +500,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -521,7 +543,7 @@ walker=system.cpu0.itb.walker
|
|||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
|
@ -531,7 +553,7 @@ type=ExeTracer
|
|||
|
||||
[system.cpu1]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dtb fuPool interrupts isa itb tracer
|
||||
children=branchPred dtb fuPool isa itb tracer
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
|
|
@ -543,7 +565,7 @@ backComSize=5
|
|||
branchPred=system.cpu1.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -569,7 +591,7 @@ iewToCommitDelay=1
|
|||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
interrupts=system.cpu1.interrupts
|
||||
interrupts=Null
|
||||
isa=system.cpu1.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
|
|
@ -620,11 +642,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -638,7 +658,7 @@ walker=system.cpu1.dtb.walker
|
|||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
|
|
@ -905,9 +925,6 @@ issueLat=3
|
|||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
|
|
@ -933,21 +950,25 @@ walker=system.cpu1.itb.walker
|
|||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -956,10 +977,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -970,18 +991,27 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -992,28 +1022,36 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -1031,19 +1069,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -1054,8 +1097,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
|
|
@ -1068,16 +1110,16 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -1124,7 +1166,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -1142,7 +1184,7 @@ pio=system.iobus.master[7]
|
|||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -1156,7 +1198,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -1165,7 +1207,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -1182,7 +1224,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Pl390
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -1191,12 +1233,12 @@ int_latency=10000
|
|||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -1206,7 +1248,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -1216,7 +1258,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -1226,7 +1268,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -1240,7 +1282,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -1253,7 +1295,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -1266,23 +1308,23 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -1292,19 +1334,18 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -1316,7 +1357,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -1329,7 +1370,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -1339,7 +1380,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -1349,7 +1390,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -1359,7 +1400,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -1369,7 +1410,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1383,7 +1424,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -1396,7 +1437,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -1411,7 +1452,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -1421,7 +1462,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -1431,7 +1472,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -1441,7 +1482,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -1457,8 +1498,7 @@ port=3456
|
|||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -1472,3 +1512,7 @@ frame_capture=false
|
|||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -21,3 +21,5 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=False
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
|
|
@ -24,7 +25,7 @@ load_addr_mask=268435455
|
|||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=268435456:520093695 1073741824:1610612735
|
||||
req_size=16
|
||||
|
|
@ -70,12 +71,16 @@ type=RawDiskImage
|
|||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -103,10 +108,10 @@ icache_port=system.cpu0.icache.cpu_side
|
|||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -117,12 +122,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -131,17 +145,17 @@ walker=system.cpu0.dtb.walker
|
|||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -152,12 +166,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -186,7 +209,7 @@ walker=system.cpu0.itb.walker
|
|||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
|
@ -196,10 +219,9 @@ type=ExeTracer
|
|||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
children=dtb isa itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -207,7 +229,7 @@ do_statistics_insts=true
|
|||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
interrupts=Null
|
||||
isa=system.cpu1.isa
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
|
|
@ -231,13 +253,10 @@ walker=system.cpu1.dtb.walker
|
|||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
fpsid=1090793632
|
||||
|
|
@ -263,21 +282,25 @@ walker=system.cpu1.itb.walker
|
|||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
|
|
@ -286,10 +309,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -300,18 +323,27 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[25]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -322,28 +354,36 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -361,19 +401,24 @@ pio=system.membus.default
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -384,8 +429,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[2]
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
|
|
@ -398,16 +442,16 @@ system=system
|
|||
|
||||
[system.realview.a9scu]
|
||||
type=A9SCU
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=520093696
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[5]
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.aaci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268451840
|
||||
pio_latency=100000
|
||||
|
|
@ -454,7 +498,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=system.cf0
|
||||
|
|
@ -472,7 +516,7 @@ pio=system.iobus.master[7]
|
|||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
amba_id=1315089
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num=55
|
||||
pio_addr=268566528
|
||||
|
|
@ -486,7 +530,7 @@ pio=system.iobus.master[4]
|
|||
[system.realview.dmac_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268632064
|
||||
pio_latency=100000
|
||||
|
|
@ -495,7 +539,7 @@ pio=system.iobus.master[9]
|
|||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=true
|
||||
pio_addr=1073741824
|
||||
pio_latency=100000
|
||||
|
|
@ -512,7 +556,7 @@ pio=system.iobus.master[24]
|
|||
|
||||
[system.realview.gic]
|
||||
type=Pl390
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
dist_addr=520097792
|
||||
|
|
@ -521,12 +565,12 @@ int_latency=10000
|
|||
it_lines=128
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.realview.gpio0_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268513280
|
||||
pio_latency=100000
|
||||
|
|
@ -536,7 +580,7 @@ pio=system.iobus.master[16]
|
|||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268517376
|
||||
pio_latency=100000
|
||||
|
|
@ -546,7 +590,7 @@ pio=system.iobus.master[17]
|
|||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268521472
|
||||
pio_latency=100000
|
||||
|
|
@ -556,7 +600,7 @@ pio=system.iobus.master[18]
|
|||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=52
|
||||
|
|
@ -570,7 +614,7 @@ pio=system.iobus.master[5]
|
|||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
amba_id=1314896
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=53
|
||||
|
|
@ -583,7 +627,7 @@ pio=system.iobus.master[6]
|
|||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=520101888
|
||||
pio_latency=100000
|
||||
|
|
@ -596,23 +640,23 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.master[4]
|
||||
pio=system.membus.master[3]
|
||||
|
||||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
pio_addr=520095232
|
||||
pio_latency=100000
|
||||
system=system
|
||||
pio=system.membus.master[6]
|
||||
pio=system.membus.master[5]
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268455936
|
||||
pio_latency=100000
|
||||
|
|
@ -622,19 +666,18 @@ pio=system.iobus.master[22]
|
|||
[system.realview.nvmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2214592511
|
||||
zero=true
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
idreg=0
|
||||
pio_addr=268435456
|
||||
pio_latency=100000
|
||||
|
|
@ -646,7 +689,7 @@ pio=system.iobus.master[1]
|
|||
[system.realview.rtc]
|
||||
type=PL031
|
||||
amba_id=3412017
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=42
|
||||
|
|
@ -659,7 +702,7 @@ pio=system.iobus.master[23]
|
|||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268492800
|
||||
pio_latency=100000
|
||||
|
|
@ -669,7 +712,7 @@ pio=system.iobus.master[20]
|
|||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=269357056
|
||||
pio_latency=100000
|
||||
|
|
@ -679,7 +722,7 @@ pio=system.iobus.master[13]
|
|||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=true
|
||||
pio_addr=268439552
|
||||
pio_latency=100000
|
||||
|
|
@ -689,7 +732,7 @@ pio=system.iobus.master[14]
|
|||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268488704
|
||||
pio_latency=100000
|
||||
|
|
@ -699,7 +742,7 @@ pio=system.iobus.master[19]
|
|||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -713,7 +756,7 @@ pio=system.iobus.master[2]
|
|||
[system.realview.timer1]
|
||||
type=Sp804
|
||||
amba_id=1316868
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
gic=system.realview.gic
|
||||
|
|
@ -726,7 +769,7 @@ pio=system.iobus.master[3]
|
|||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
end_on_eot=false
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
|
|
@ -741,7 +784,7 @@ pio=system.iobus.master[0]
|
|||
[system.realview.uart1_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268476416
|
||||
pio_latency=100000
|
||||
|
|
@ -751,7 +794,7 @@ pio=system.iobus.master[10]
|
|||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268480512
|
||||
pio_latency=100000
|
||||
|
|
@ -761,7 +804,7 @@ pio=system.iobus.master[11]
|
|||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268484608
|
||||
pio_latency=100000
|
||||
|
|
@ -771,7 +814,7 @@ pio=system.iobus.master[12]
|
|||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
ignore_access=false
|
||||
pio_addr=268500992
|
||||
pio_latency=100000
|
||||
|
|
@ -787,8 +830,7 @@ port=3456
|
|||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -802,3 +844,7 @@ frame_capture=false
|
|||
number=0
|
||||
port=5900
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -31,3 +31,5 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
|
|
@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxX86System
|
||||
children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table
|
||||
children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
|
||||
acpi_description_table_pointer=system.acpi_description_table_pointer
|
||||
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
e820_table=system.e820_table
|
||||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
|
|
@ -53,7 +54,7 @@ oem_table_id=
|
|||
|
||||
[system.apicbridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=11529215046068469760:11529215046068473855
|
||||
req_size=16
|
||||
|
|
@ -63,17 +64,22 @@ slave=system.iobus.master[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[1]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
|
||||
children=apic_clk_domain branchPred dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
|
|
@ -85,7 +91,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -134,6 +140,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -155,6 +162,11 @@ workload=
|
|||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
|
|
@ -163,11 +175,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -175,10 +185,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -189,12 +199,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -203,16 +222,17 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.dtb_walker_cache.cpu_side
|
||||
|
||||
[system.cpu.dtb_walker_cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -223,12 +243,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.cpu.dtb_walker_cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dtb.walker.port
|
||||
mem_side=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.dtb_walker_cache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=1024
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
|
|
@ -494,10 +523,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -508,22 +537,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
system=system
|
||||
int_master=system.membus.slave[3]
|
||||
int_slave=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
|
@ -536,16 +574,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.itb_walker_cache.cpu_side
|
||||
|
||||
[system.cpu.itb_walker_cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -556,18 +595,27 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.cpu.itb_walker_cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.itb.walker.port
|
||||
mem_side=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.itb_walker_cache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=1024
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -578,16 +626,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -598,6 +654,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke
|
|||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.e820_table]
|
||||
type=X86E820Table
|
||||
children=entries0 entries1 entries2
|
||||
|
|
@ -969,8 +1030,7 @@ sys=system
|
|||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -980,10 +1040,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -994,28 +1054,36 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[18]
|
||||
mem_side=system.membus.slave[4]
|
||||
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
|
||||
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -1038,7 +1106,7 @@ system=system
|
|||
|
||||
[system.pc.behind_pci]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854779128
|
||||
pio_latency=100000
|
||||
|
|
@ -1056,7 +1124,7 @@ pio=system.iobus.master[12]
|
|||
[system.pc.com_1]
|
||||
type=Uart8250
|
||||
children=terminal
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=9223372036854776824
|
||||
pio_latency=100000
|
||||
platform=system.pc
|
||||
|
|
@ -1080,7 +1148,7 @@ port=3456
|
|||
|
||||
[system.pc.fake_com_2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776568
|
||||
pio_latency=100000
|
||||
|
|
@ -1097,7 +1165,7 @@ pio=system.iobus.master[14]
|
|||
|
||||
[system.pc.fake_com_3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776808
|
||||
pio_latency=100000
|
||||
|
|
@ -1114,7 +1182,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.pc.fake_com_4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776552
|
||||
pio_latency=100000
|
||||
|
|
@ -1131,7 +1199,7 @@ pio=system.iobus.master[16]
|
|||
|
||||
[system.pc.fake_floppy]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776818
|
||||
pio_latency=100000
|
||||
|
|
@ -1148,7 +1216,7 @@ pio=system.iobus.master[17]
|
|||
|
||||
[system.pc.i_dont_exist]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854775936
|
||||
pio_latency=100000
|
||||
|
|
@ -1166,7 +1234,8 @@ pio=system.iobus.master[11]
|
|||
[system.pc.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.pc
|
||||
size=16777216
|
||||
|
|
@ -1189,7 +1258,7 @@ speaker=system.pc.south_bridge.speaker
|
|||
[system.pc.south_bridge.cmos]
|
||||
type=Cmos
|
||||
children=int_pin
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
int_pin=system.pc.south_bridge.cmos.int_pin
|
||||
pio_addr=9223372036854775920
|
||||
pio_latency=100000
|
||||
|
|
@ -1202,7 +1271,7 @@ type=X86IntSourcePin
|
|||
|
||||
[system.pc.south_bridge.dma1]
|
||||
type=I8237
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=9223372036854775808
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1249,7 +1318,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
|
||||
|
|
@ -1281,7 +1350,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1301,7 +1370,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
@ -1384,7 +1453,7 @@ number=12
|
|||
[system.pc.south_bridge.io_apic]
|
||||
type=I82094AA
|
||||
apic_id=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
external_int_pic=system.pc.south_bridge.pic1
|
||||
int_latency=1000
|
||||
pio_addr=4273995776
|
||||
|
|
@ -1396,7 +1465,7 @@ pio=system.iobus.master[10]
|
|||
[system.pc.south_bridge.keyboard]
|
||||
type=I8042
|
||||
children=keyboard_int_pin mouse_int_pin
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
command_port=9223372036854775908
|
||||
data_port=9223372036854775904
|
||||
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
|
|
@ -1415,7 +1484,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pic1]
|
||||
type=I8259
|
||||
children=output
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
mode=I8259Master
|
||||
output=system.pc.south_bridge.pic1.output
|
||||
pio_addr=9223372036854775840
|
||||
|
|
@ -1430,7 +1499,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pic2]
|
||||
type=I8259
|
||||
children=output
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
mode=I8259Slave
|
||||
output=system.pc.south_bridge.pic2.output
|
||||
pio_addr=9223372036854775968
|
||||
|
|
@ -1445,7 +1514,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pit]
|
||||
type=I8254
|
||||
children=int_pin
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
int_pin=system.pc.south_bridge.pit.int_pin
|
||||
pio_addr=9223372036854775872
|
||||
pio_latency=100000
|
||||
|
|
@ -1457,7 +1526,7 @@ type=X86IntSourcePin
|
|||
|
||||
[system.pc.south_bridge.speaker]
|
||||
type=PcSpeaker
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
i8254=system.pc.south_bridge.pit
|
||||
pio_addr=9223372036854775905
|
||||
pio_latency=100000
|
||||
|
|
@ -1467,19 +1536,24 @@ pio=system.iobus.master[9]
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -1490,8 +1564,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.smbios_table]
|
||||
type=X86SMBiosSMBiosTable
|
||||
|
|
@ -1514,3 +1587,7 @@ starting_addr_segment=0
|
|||
vendor=
|
||||
version=
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,6 @@ warn: Sockets disabled, not accepting terminal connections
|
|||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 18 2013 13:37:41
|
||||
gem5 started Apr 18 2013 13:56:06
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:21:20
|
||||
gem5 started Sep 22 2013 06:54:38
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5132953103000 because m5_exit instruction encountered
|
||||
Exiting @ tick 5133762710000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
|
||||
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
kernel direct mapping tables up to 8000000 @ 8000-a000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA 0 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
early_node_map[2] active PFN ranges
|
||||
0: 0 -> 159
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
|
|
@ -18,8 +20,10 @@ Processor #0 (Bootup-CPU)
|
|||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
|
||||
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
Built 1 zonelists. Total pages: 30458
|
||||
Built 1 zonelists. Total pages: 30613
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
|
|
@ -29,7 +33,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
|
|||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
|
||||
Memory: 122188k/131072k available (3742k kernel code, 8460k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
|
|
@ -39,7 +43,7 @@ ACPI: Core revision 20070126
|
|||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812557
|
||||
result 7812560
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ e820_table=system.e820_table
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
|
|
@ -60,7 +60,6 @@ voltage_domain=system.voltage_domain
|
|||
[system.cpu0]
|
||||
type=TimingSimpleCPU
|
||||
children=apic_clk_domain dtb interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
|
|
@ -139,7 +138,6 @@ type=ExeTracer
|
|||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=apic_clk_domain dtb interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=1
|
||||
|
|
@ -852,7 +850,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -872,7 +870,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
|||
|
|
@ -1,24 +1,24 @@
|
|||
Real time: Aug/29/2013 10:24:02
|
||||
Real time: Sep/22/2013 07:54:54
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 771
|
||||
Elapsed_time_in_minutes: 12.85
|
||||
Elapsed_time_in_hours: 0.214167
|
||||
Elapsed_time_in_days: 0.00892361
|
||||
Elapsed_time_in_seconds: 689
|
||||
Elapsed_time_in_minutes: 11.4833
|
||||
Elapsed_time_in_hours: 0.191389
|
||||
Elapsed_time_in_days: 0.00797454
|
||||
|
||||
Virtual_time_in_seconds: 767.55
|
||||
Virtual_time_in_minutes: 12.7925
|
||||
Virtual_time_in_hours: 0.213208
|
||||
Virtual_time_in_days: 0.00888368
|
||||
Virtual_time_in_seconds: 688.52
|
||||
Virtual_time_in_minutes: 11.4753
|
||||
Virtual_time_in_hours: 0.191256
|
||||
Virtual_time_in_days: 0.00796898
|
||||
|
||||
Ruby_current_time: 10608810122
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 10608810122
|
||||
|
||||
mbytes_resident: 612.449
|
||||
mbytes_total: 859.008
|
||||
resident_ratio: 0.712982
|
||||
mbytes_resident: 589.816
|
||||
mbytes_total: 810.262
|
||||
resident_ratio: 0.727933
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:10 L1Cache-1:9
|
||||
|
|
@ -28,28 +28,28 @@ DMA-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826686 average: 1.00012 | standard deviation: 0.0109671 | 0 154808062 18624 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826690 average: 1.00012 | standard deviation: 0.0109671 | 0 154808066 18624 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
latency: [binsize: 8 max: 146 count: 154826685 average: 3.40667 | standard deviation: 3.89546 | 152128103 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88160 4468 159 160 697 95 ]
|
||||
latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.1602 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20230 1017 49 23 146 37 ]
|
||||
latency: ST: [binsize: 8 max: 146 count: 9754589 average: 4.6097 | standard deviation: 10.5962 | 9399925 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
|
||||
latency: IFETCH: [binsize: 8 max: 145 count: 128502467 average: 3.10882 | standard deviation: 1.62805 | 127704896 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 17 24 76 1 ]
|
||||
latency: RMW_Read: [binsize: 8 max: 143 count: 526559 average: 6.05821 | standard deviation: 8.42497 | 454440 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
|
||||
latency: [binsize: 8 max: 146 count: 154826689 average: 3.40667 | standard deviation: 3.89546 | 152128107 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
|
||||
latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.16019 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
|
||||
latency: ST: [binsize: 8 max: 146 count: 9754590 average: 4.6097 | standard deviation: 10.5962 | 9399926 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
|
||||
latency: IFETCH: [binsize: 8 max: 145 count: 128502469 average: 3.10882 | standard deviation: 1.62805 | 127704898 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
|
||||
latency: RMW_Read: [binsize: 8 max: 143 count: 526560 average: 6.05821 | standard deviation: 8.42496 | 454441 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
|
||||
latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343870 average: 5.61917 | standard deviation: 7.40449 | 302009 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
|
||||
latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average: 3 | standard deviation: 0 | 0 0 0 343870 ]
|
||||
hit latency: [binsize: 1 max: 3 count: 152128103 average: 3 | standard deviation: 0 | 0 0 0 152128103 ]
|
||||
hit latency: [binsize: 1 max: 3 count: 152128107 average: 3 | standard deviation: 0 | 0 0 0 152128107 ]
|
||||
hit latency: LD: [binsize: 1 max: 3 count: 13922963 average: 3 | standard deviation: 0 | 0 0 0 13922963 ]
|
||||
hit latency: ST: [binsize: 1 max: 3 count: 9399925 average: 3 | standard deviation: 0 | 0 0 0 9399925 ]
|
||||
hit latency: IFETCH: [binsize: 1 max: 3 count: 127704896 average: 3 | standard deviation: 0 | 0 0 0 127704896 ]
|
||||
hit latency: RMW_Read: [binsize: 1 max: 3 count: 454440 average: 3 | standard deviation: 0 | 0 0 0 454440 ]
|
||||
hit latency: ST: [binsize: 1 max: 3 count: 9399926 average: 3 | standard deviation: 0 | 0 0 0 9399926 ]
|
||||
hit latency: IFETCH: [binsize: 1 max: 3 count: 127704898 average: 3 | standard deviation: 0 | 0 0 0 127704898 ]
|
||||
hit latency: RMW_Read: [binsize: 1 max: 3 count: 454441 average: 3 | standard deviation: 0 | 0 0 0 454441 ]
|
||||
hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302009 average: 3 | standard deviation: 0 | 0 0 0 302009 ]
|
||||
hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average: 3 | standard deviation: 0 | 0 0 0 343870 ]
|
||||
miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88160 4468 159 160 697 95 ]
|
||||
miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4572 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20230 1017 49 23 146 37 ]
|
||||
miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
|
||||
miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4571 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
|
||||
miss latency: ST: [binsize: 8 max: 146 count: 354664 average: 47.2728 | standard deviation: 34.6308 | 0 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
|
||||
miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5324 | standard deviation: 11.0261 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 17 24 76 1 ]
|
||||
miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5323 | standard deviation: 11.026 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
|
||||
miss latency: RMW_Read: [binsize: 8 max: 143 count: 72119 average: 25.3288 | standard deviation: 9.37846 | 0 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
|
||||
miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5153 | standard deviation: 6.61955 | 0 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
|
||||
|
||||
|
|
|
|||
|
|
@ -3,12 +3,12 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 18 2013 13:38:36
|
||||
gem5 started Apr 18 2013 13:38:48
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:43:05
|
||||
gem5 started Sep 22 2013 07:43:21
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5205148879000 because m5_exit instruction encountered
|
||||
Exiting @ tick 5304405061000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,74 +4,74 @@ sim_seconds 5.304405 # Nu
|
|||
sim_ticks 5304405061000 # Number of ticks simulated
|
||||
final_tick 5304405061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 140464 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 269516 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6884731594 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 879628 # Number of bytes of host memory used
|
||||
host_seconds 770.46 # Real time elapsed on the host
|
||||
sim_insts 108221986 # Number of instructions simulated
|
||||
sim_ops 207651285 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 157121 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 301476 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7701146515 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 829712 # Number of bytes of host memory used
|
||||
host_seconds 688.78 # Real time elapsed on the host
|
||||
sim_insts 108221987 # Number of instructions simulated
|
||||
sim_ops 207651289 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 136528 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 67168 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 857531504 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 68407513 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 857531520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 68407514 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 89360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 41152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 170488232 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 28476928 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1125273489 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 857531504 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::total 1125273506 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 857531520 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 170488232 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1028019736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1028019752 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 47712171 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 47712172 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 22210158 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 72913449 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 72913450 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 804 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 17066 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 8396 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 107191438 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 11941415 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 107191440 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 11941416 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 11170 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 5144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 21311029 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 4242568 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 144729030 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 144729033 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 7031339 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 7031340 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 3067118 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 10145195 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 10145196 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 6618 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 25739 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 12663 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 161664031 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 161664034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 12896359 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 16846 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 7758 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 32140877 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 5368543 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 212139434 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 161664031 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 212139438 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 161664034 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 32140877 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 193804908 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 193804911 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 563891 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 8994820 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 8994821 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 4187116 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13745830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 570508 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 25739 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 12666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 161664031 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 161664034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 21891180 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 16846 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 7758 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 32140877 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 9555659 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 225885264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 225885267 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
|
|
@ -409,12 +409,12 @@ system.piobus.respLayer4.occupancy 644500 # La
|
|||
system.piobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer5.occupancy 632500 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 17394866 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 17394868 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 1603352 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 18998218 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 106683217 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 18998220 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 106683219 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 508221 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 107191438 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 107191440 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
|
||||
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
|
||||
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
|
||||
|
|
@ -497,16 +497,16 @@ system.ruby.dir_cntrl0.memBuffer.memReq 266936 # To
|
|||
system.ruby.dir_cntrl0.memBuffer.memRead 172650 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 94286 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 684164 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 919467 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 919462 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 20 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 5913 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 925400 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 3.466749 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 908855 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 7819 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 5908 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 925390 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 3.466711 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 908852 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 7818 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 5 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 3 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 2785 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 2784 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 8698 3.26% 3.26% | 8135 3.05% 6.31% | 8180 3.06% 9.37% | 8226 3.08% 12.45% | 8503 3.19% 15.64% | 8270 3.10% 18.74% | 8180 3.06% 21.80% | 8201 3.07% 24.87% | 8428 3.16% 28.03% | 8229 3.08% 31.11% | 8315 3.11% 34.23% | 8269 3.10% 37.33% | 8279 3.10% 40.43% | 8033 3.01% 43.44% | 8160 3.06% 46.49% | 7316 2.74% 49.23% | 8186 3.07% 52.30% | 8370 3.14% 55.44% | 8196 3.07% 58.51% | 8109 3.04% 61.54% | 8870 3.32% 64.87% | 8313 3.11% 67.98% | 8266 3.10% 71.08% | 8194 3.07% 74.15% | 8414 3.15% 77.30% | 8231 3.08% 80.38% | 8474 3.17% 83.56% | 9055 3.39% 86.95% | 8979 3.36% 90.31% | 8905 3.34% 93.65% | 8853 3.32% 96.97% | 8099 3.03% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 266936 # Number of accesses per bank
|
||||
|
||||
|
|
@ -535,6 +535,18 @@ system.ruby.network.routers5.msg_bytes.Response_Control::2 14631224
|
|||
system.ruby.network.routers5.msg_bytes.Writeback_Data::0 116862408
|
||||
system.ruby.network.routers5.msg_bytes.Writeback_Data::1 23472
|
||||
system.ruby.network.routers5.msg_bytes.Writeback_Control::0 657680
|
||||
system.ruby.network.msg_count.Control 8613696
|
||||
system.ruby.network.msg_count.Request_Control 388888
|
||||
system.ruby.network.msg_count.Response_Data 8909307
|
||||
system.ruby.network.msg_count.Response_Control 11246253
|
||||
system.ruby.network.msg_count.Writeback_Data 4870245
|
||||
system.ruby.network.msg_count.Writeback_Control 246630
|
||||
system.ruby.network.msg_byte.Control 68909568
|
||||
system.ruby.network.msg_byte.Request_Control 3111104
|
||||
system.ruby.network.msg_byte.Response_Data 641470104
|
||||
system.ruby.network.msg_byte.Response_Control 89970024
|
||||
system.ruby.network.msg_byte.Writeback_Data 350657640
|
||||
system.ruby.network.msg_byte.Writeback_Control 1973040
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -550,21 +562,21 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1
|
|||
system.cpu0.numCycles 10606609404 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 91816947 # Number of instructions committed
|
||||
system.cpu0.committedOps 177194839 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 167195942 # Number of integer alu accesses
|
||||
system.cpu0.committedInsts 91816948 # Number of instructions committed
|
||||
system.cpu0.committedOps 177194843 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 167195946 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 2105705 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 16302138 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 167195942 # number of integer instructions
|
||||
system.cpu0.num_int_insts 167195946 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 0 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 412764336 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 208844309 # number of times the integer registers were written
|
||||
system.cpu0.num_int_register_reads 412764349 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 208844314 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 19832606 # number of memory refs
|
||||
system.cpu0.num_load_insts 12787611 # Number of load instructions
|
||||
system.cpu0.num_store_insts 7044995 # Number of store instructions
|
||||
system.cpu0.num_mem_refs 19832608 # number of memory refs
|
||||
system.cpu0.num_load_insts 12787612 # Number of load instructions
|
||||
system.cpu0.num_store_insts 7044996 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 9879410853.538599 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 727198550.461401 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.068561 # Percentage of non-idle cycles
|
||||
|
|
@ -717,11 +729,11 @@ system.ruby.network.routers5.throttle4.link_utilization 0
|
|||
system.ruby.l1_cntrl0.Load | 11418758 74.36% 74.36% | 3936572 25.64% 100.00%
|
||||
system.ruby.l1_cntrl0.Load::total 15355330
|
||||
|
||||
system.ruby.l1_cntrl0.Ifetch | 107191441 83.42% 83.42% | 21311032 16.58% 100.00%
|
||||
system.ruby.l1_cntrl0.Ifetch::total 128502473
|
||||
system.ruby.l1_cntrl0.Ifetch | 107191443 83.42% 83.42% | 21311032 16.58% 100.00%
|
||||
system.ruby.l1_cntrl0.Ifetch::total 128502475
|
||||
|
||||
system.ruby.l1_cntrl0.Store | 7579460 69.10% 69.10% | 3389428 30.90% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 10968888
|
||||
system.ruby.l1_cntrl0.Store | 7579462 69.10% 69.10% | 3389428 30.90% 100.00%
|
||||
system.ruby.l1_cntrl0.Store::total 10968890
|
||||
|
||||
system.ruby.l1_cntrl0.Inv | 28983 54.10% 54.10% | 24594 45.90% 100.00%
|
||||
system.ruby.l1_cntrl0.Inv::total 53577
|
||||
|
|
@ -786,8 +798,8 @@ system.ruby.l1_cntrl0.I.L1_Replacement::total 26006
|
|||
system.ruby.l1_cntrl0.S.Load | 738269 59.20% 59.20% | 508761 40.80% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Load::total 1247030
|
||||
|
||||
system.ruby.l1_cntrl0.S.Ifetch | 106683217 83.54% 83.54% | 21021679 16.46% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Ifetch::total 127704896
|
||||
system.ruby.l1_cntrl0.S.Ifetch | 106683219 83.54% 83.54% | 21021679 16.46% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Ifetch::total 127704898
|
||||
|
||||
system.ruby.l1_cntrl0.S.Store | 19704 47.71% 47.71% | 21592 52.29% 100.00%
|
||||
system.ruby.l1_cntrl0.S.Store::total 41296
|
||||
|
|
@ -819,8 +831,8 @@ system.ruby.l1_cntrl0.E.Fwd_GETS::total 2430
|
|||
system.ruby.l1_cntrl0.M.Load | 6351147 70.61% 70.61% | 2643736 29.39% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Load::total 8994883
|
||||
|
||||
system.ruby.l1_cntrl0.M.Store | 7142229 69.03% 69.03% | 3204343 30.97% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Store::total 10346572
|
||||
system.ruby.l1_cntrl0.M.Store | 7142231 69.03% 69.03% | 3204343 30.97% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Store::total 10346574
|
||||
|
||||
system.ruby.l1_cntrl0.M.Inv | 52 15.95% 15.95% | 274 84.05% 100.00%
|
||||
system.ruby.l1_cntrl0.M.Inv::total 326
|
||||
|
|
@ -922,18 +934,6 @@ system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 561 0.00% 0.00%
|
|||
system.ruby.l2_cntrl0.MT_IIB.Unblock 98 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_IB.WB_Data 98 0.00% 0.00%
|
||||
system.ruby.l2_cntrl0.MT_SB.Unblock 45449 0.00% 0.00%
|
||||
system.ruby.network.msg_count.Control 8613696
|
||||
system.ruby.network.msg_count.Request_Control 388888
|
||||
system.ruby.network.msg_count.Response_Data 8909307
|
||||
system.ruby.network.msg_count.Response_Control 11246253
|
||||
system.ruby.network.msg_count.Writeback_Data 4870245
|
||||
system.ruby.network.msg_count.Writeback_Control 246630
|
||||
system.ruby.network.msg_byte.Control 68909568
|
||||
system.ruby.network.msg_byte.Request_Control 3111104
|
||||
system.ruby.network.msg_byte.Response_Data 641470104
|
||||
system.ruby.network.msg_byte.Response_Control 89970024
|
||||
system.ruby.network.msg_byte.Writeback_Data 350657640
|
||||
system.ruby.network.msg_byte.Writeback_Control 1973040
|
||||
system.ruby.dir_cntrl0.Fetch 172650 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Data 94286 0.00% 0.00%
|
||||
system.ruby.dir_cntrl0.Memory_Data 172650 0.00% 0.00%
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
|
||||
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
end_pfn_map = 32768
|
||||
kernel direct mapping tables up to 8000000 @ 100000-102000
|
||||
kernel direct mapping tables up to 8000000 @ 8000-a000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 256 -> 4096
|
||||
DMA 0 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[1] active PFN ranges
|
||||
early_node_map[2] active PFN ranges
|
||||
0: 0 -> 159
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
|
|
@ -21,25 +23,25 @@ Setting APIC routing to flat
|
|||
Processors: 2
|
||||
Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
|
||||
PERCPU: Allocating 34160 bytes of per cpu data
|
||||
Built 1 zonelists. Total pages: 30461
|
||||
Built 1 zonelists. Total pages: 30616
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
Marking TSC unstable due to TSCs unsynchronized
|
||||
time.c: Detected 2000.001 MHz processor.
|
||||
time.c: Detected 2000.000 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121384k/131072k available (3699k kernel code, 8500k reserved, 1767k data, 248k init)
|
||||
Memory: 122008k/131072k available (3699k kernel code, 8512k reserved, 1767k data, 248k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
Freeing SMP alternatives: 34k freed
|
||||
Using local APIC timer interrupts.
|
||||
result 7812503
|
||||
result 7812500
|
||||
Detected 7.812 MHz APIC timer.
|
||||
Booting processor 1/2 APIC 0x1
|
||||
Initializing CPU#1
|
||||
|
|
@ -125,8 +127,8 @@ oprofile: using timer interrupt.
|
|||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
IPv6 over IPv4 tunneling driver
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
|
|
|
|||
|
|
@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxX86System
|
||||
children=acpi_description_table_pointer apicbridge bridge cpu0 cpu1 cpu2 e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
||||
children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
|
||||
acpi_description_table_pointer=system.acpi_description_table_pointer
|
||||
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
e820_table=system.e820_table
|
||||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
|
|
@ -53,7 +54,7 @@ oem_table_id=
|
|||
|
||||
[system.apicbridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=11529215046068469760:11529215046068473855
|
||||
req_size=16
|
||||
|
|
@ -63,20 +64,24 @@ slave=system.iobus.master[0]
|
|||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
delay=50000
|
||||
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[1]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -109,12 +114,17 @@ workload=
|
|||
dcache_port=system.cpu0.dcache.cpu_side
|
||||
icache_port=system.cpu0.icache.cpu_side
|
||||
|
||||
[system.cpu0.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -125,12 +135,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dcache.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -139,16 +158,17 @@ walker=system.cpu0.dtb.walker
|
|||
|
||||
[system.cpu0.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu0.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -159,22 +179,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.icache.tags]
|
||||
type=LRU
|
||||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu0.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
system=system
|
||||
int_master=system.membus.slave[3]
|
||||
int_slave=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=X86ISA
|
||||
|
|
@ -187,7 +216,8 @@ walker=system.cpu0.itb.walker
|
|||
|
||||
[system.cpu0.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -197,9 +227,8 @@ type=ExeTracer
|
|||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -231,7 +260,8 @@ walker=system.cpu1.dtb.walker
|
|||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
|
||||
[system.cpu1.isa]
|
||||
|
|
@ -245,7 +275,8 @@ walker=system.cpu1.itb.walker
|
|||
|
||||
[system.cpu1.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
|
|
@ -265,7 +296,7 @@ backComSize=5
|
|||
branchPred=system.cpu2.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -342,11 +373,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -360,7 +389,8 @@ walker=system.cpu2.dtb.walker
|
|||
|
||||
[system.cpu2.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
|
||||
[system.cpu2.fuPool]
|
||||
|
|
@ -637,12 +667,18 @@ walker=system.cpu2.itb.walker
|
|||
|
||||
[system.cpu2.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
|
||||
[system.cpu2.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.e820_table]
|
||||
type=X86E820Table
|
||||
children=entries0 entries1 entries2
|
||||
|
|
@ -1014,8 +1050,7 @@ sys=system
|
|||
|
||||
[system.iobus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
use_default_range=true
|
||||
width=8
|
||||
|
|
@ -1025,10 +1060,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge
|
|||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:134217727
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
|
|
@ -1039,18 +1074,27 @@ prefetcher=Null
|
|||
response_latency=50
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[18]
|
||||
mem_side=system.membus.slave[4]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_ranges=0:18446744073709551615
|
||||
[system.iocache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.clk_domain
|
||||
hit_latency=50
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -1061,28 +1105,36 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
children=badaddr_responder
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.physmem.port system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
|
||||
master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
|
||||
slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
|
|
@ -1105,7 +1157,7 @@ system=system
|
|||
|
||||
[system.pc.behind_pci]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854779128
|
||||
pio_latency=100000
|
||||
|
|
@ -1123,7 +1175,7 @@ pio=system.iobus.master[12]
|
|||
[system.pc.com_1]
|
||||
type=Uart8250
|
||||
children=terminal
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=9223372036854776824
|
||||
pio_latency=100000
|
||||
platform=system.pc
|
||||
|
|
@ -1147,7 +1199,7 @@ port=3456
|
|||
|
||||
[system.pc.fake_com_2]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776568
|
||||
pio_latency=100000
|
||||
|
|
@ -1164,7 +1216,7 @@ pio=system.iobus.master[14]
|
|||
|
||||
[system.pc.fake_com_3]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776808
|
||||
pio_latency=100000
|
||||
|
|
@ -1181,7 +1233,7 @@ pio=system.iobus.master[15]
|
|||
|
||||
[system.pc.fake_com_4]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776552
|
||||
pio_latency=100000
|
||||
|
|
@ -1198,7 +1250,7 @@ pio=system.iobus.master[16]
|
|||
|
||||
[system.pc.fake_floppy]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776818
|
||||
pio_latency=100000
|
||||
|
|
@ -1215,7 +1267,7 @@ pio=system.iobus.master[17]
|
|||
|
||||
[system.pc.i_dont_exist]
|
||||
type=IsaFake
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854775936
|
||||
pio_latency=100000
|
||||
|
|
@ -1233,7 +1285,8 @@ pio=system.iobus.master[11]
|
|||
[system.pc.pciconfig]
|
||||
type=PciConfigAll
|
||||
bus=0
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=0
|
||||
pio_latency=30000
|
||||
platform=system.pc
|
||||
size=16777216
|
||||
|
|
@ -1256,7 +1309,7 @@ speaker=system.pc.south_bridge.speaker
|
|||
[system.pc.south_bridge.cmos]
|
||||
type=Cmos
|
||||
children=int_pin
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
int_pin=system.pc.south_bridge.cmos.int_pin
|
||||
pio_addr=9223372036854775920
|
||||
pio_latency=100000
|
||||
|
|
@ -1269,7 +1322,7 @@ type=X86IntSourcePin
|
|||
|
||||
[system.pc.south_bridge.dma1]
|
||||
type=I8237
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
pio_addr=9223372036854775808
|
||||
pio_latency=100000
|
||||
system=system
|
||||
|
|
@ -1316,7 +1369,7 @@ SubClassCode=1
|
|||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
|
||||
|
|
@ -1348,7 +1401,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1368,7 +1421,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
@ -1451,7 +1504,7 @@ number=12
|
|||
[system.pc.south_bridge.io_apic]
|
||||
type=I82094AA
|
||||
apic_id=1
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
external_int_pic=system.pc.south_bridge.pic1
|
||||
int_latency=1000
|
||||
pio_addr=4273995776
|
||||
|
|
@ -1463,7 +1516,7 @@ pio=system.iobus.master[10]
|
|||
[system.pc.south_bridge.keyboard]
|
||||
type=I8042
|
||||
children=keyboard_int_pin mouse_int_pin
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
command_port=9223372036854775908
|
||||
data_port=9223372036854775904
|
||||
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
|
|
@ -1482,7 +1535,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pic1]
|
||||
type=I8259
|
||||
children=output
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
mode=I8259Master
|
||||
output=system.pc.south_bridge.pic1.output
|
||||
pio_addr=9223372036854775840
|
||||
|
|
@ -1497,7 +1550,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pic2]
|
||||
type=I8259
|
||||
children=output
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
mode=I8259Slave
|
||||
output=system.pc.south_bridge.pic2.output
|
||||
pio_addr=9223372036854775968
|
||||
|
|
@ -1512,7 +1565,7 @@ type=X86IntSourcePin
|
|||
[system.pc.south_bridge.pit]
|
||||
type=I8254
|
||||
children=int_pin
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
int_pin=system.pc.south_bridge.pit.int_pin
|
||||
pio_addr=9223372036854775872
|
||||
pio_latency=100000
|
||||
|
|
@ -1524,7 +1577,7 @@ type=X86IntSourcePin
|
|||
|
||||
[system.pc.south_bridge.speaker]
|
||||
type=PcSpeaker
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
i8254=system.pc.south_bridge.pit
|
||||
pio_addr=9223372036854775905
|
||||
pio_latency=100000
|
||||
|
|
@ -1536,17 +1589,22 @@ type=SimpleDRAM
|
|||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -1557,8 +1615,7 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.smbios_table]
|
||||
type=X86SMBiosSMBiosTable
|
||||
|
|
@ -1583,8 +1640,7 @@ version=
|
|||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -1592,3 +1648,7 @@ width=8
|
|||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@ warn: Reading current count from inactive timer.
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
hack: be nice to actually delete the event here
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -27,7 +27,7 @@ Built 1 zonelists. Total pages: 30613
|
|||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 1999.988 MHz processor.
|
||||
time.c: Detected 1999.986 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
|
|
@ -43,7 +43,7 @@ ACPI: Core revision 20070126
|
|||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812471
|
||||
result 7812464
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
|
|
|
|||
|
|
@ -13,28 +13,28 @@ boot_osflags=a
|
|||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
hypervisor_addr=1099243257856
|
||||
hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin
|
||||
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
|
||||
hypervisor_desc=system.hypervisor_desc
|
||||
hypervisor_desc_addr=133446500352
|
||||
hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin
|
||||
hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
mem_ranges=1048576:68157439 2147483648:2415919103
|
||||
memories=system.hypervisor_desc system.nvram system.physmem1 system.physmem0 system.partition_desc system.rom
|
||||
memories=system.rom system.physmem1 system.hypervisor_desc system.physmem0 system.nvram system.partition_desc
|
||||
num_work_ids=16
|
||||
nvram=system.nvram
|
||||
nvram_addr=133429198848
|
||||
nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1
|
||||
nvram_bin=/dist/m5/system/binaries/nvram1
|
||||
openboot_addr=1099243716608
|
||||
openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin
|
||||
openboot_bin=/dist/m5/system/binaries/openboot_new.bin
|
||||
partition_desc=system.partition_desc
|
||||
partition_desc_addr=133445976064
|
||||
partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin
|
||||
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
|
||||
readfile=tests/halt.sh
|
||||
reset_addr=1099243192320
|
||||
reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin
|
||||
reset_bin=/dist/m5/system/binaries/reset_new.bin
|
||||
rom=system.rom
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -140,7 +140,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2
|
||||
image_file=/dist/m5/system/disks/disk.s10hw2
|
||||
read_only=true
|
||||
|
||||
[system.hypervisor_desc]
|
||||
|
|
|
|||
|
|
@ -14,6 +14,14 @@ warn: rounding error > tolerance
|
|||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 3 2013 21:18:30
|
||||
gem5 started Mar 3 2013 22:32:14
|
||||
gem5 compiled Sep 22 2013 06:07:13
|
||||
gem5 started Sep 22 2013 06:07:33
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
Global frequency set at 2000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.233778 # Nu
|
|||
sim_ticks 4467555024 # Number of ticks simulated
|
||||
final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1777607 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1778305 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3563977 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 572484 # Number of bytes of host memory used
|
||||
host_seconds 1253.53 # Real time elapsed on the host
|
||||
host_inst_rate 3036891 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3038085 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6088754 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 524036 # Number of bytes of host memory used
|
||||
host_seconds 733.74 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
|
||||
|
|
@ -19,20 +19,22 @@ system.hypervisor_desc.bw_read::cpu.data 7517 # To
|
|||
system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
|
||||
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
|
||||
system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
|
||||
|
|
@ -81,6 +83,20 @@ system.physmem0.bw_write::total 6894251 # Wr
|
|||
system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
|
||||
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
|
||||
system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
|
||||
|
|
@ -89,22 +105,6 @@ system.partition_desc.bw_read::cpu.data 2169 # To
|
|||
system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 5163367605 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 11533814443 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,6 +30,11 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -121,11 +128,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +138,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +152,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -431,10 +445,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -445,12 +459,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -500,16 +523,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -528,9 +559,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -539,10 +570,14 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -576,6 +616,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 01:31:22
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:20:51
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -25,4 +25,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 26780899500 because target called exit()
|
||||
Exiting @ tick 26877484000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
|
@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
|
@ -120,9 +129,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -131,11 +140,16 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 20:04:57
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:18:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,12 +81,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -110,12 +125,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -165,17 +189,26 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -192,9 +225,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -203,11 +236,16 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 20:06:05
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 09:24:43
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -88,9 +97,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -99,11 +108,16 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-at
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 15:49:24
|
||||
gem5 started Jan 23 2013 16:10:07
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:07:13
|
||||
gem5 started Sep 22 2013 06:07:55
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,22 +81,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -101,12 +116,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
|
|
@ -119,10 +143,10 @@ size=64
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -133,17 +157,26 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -160,9 +193,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -171,11 +204,16 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-ti
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 15:49:24
|
||||
gem5 started Jan 23 2013 16:04:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:07:13
|
||||
gem5 started Sep 22 2013 06:07:47
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,9 +30,14 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -113,6 +120,11 @@ workload=system.cpu.workload
|
|||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
|
|
@ -121,11 +133,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +143,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +157,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -430,10 +450,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -444,15 +464,24 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -472,16 +501,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -492,16 +522,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -520,9 +558,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -531,10 +569,14 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -568,6 +615,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 15:13:59
|
||||
gem5 started Mar 27 2013 00:35:52
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:21:20
|
||||
gem5 started Sep 22 2013 06:21:35
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -18,6 +18,7 @@ All Rights Reserved.
|
|||
nodes : 500
|
||||
active arcs : 1905
|
||||
simplex iterations : 1502
|
||||
info: Increasing stack size by one page.
|
||||
flow value : 4990014995
|
||||
new implicit arcs : 23867
|
||||
active arcs : 25772
|
||||
|
|
@ -25,4 +26,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 66015916000 because target called exit()
|
||||
Exiting @ tick 65501881000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
children=apic_clk_domain dtb interrupts isa itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -63,6 +72,11 @@ workload=system.cpu.workload
|
|||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -97,7 +112,8 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
|
|
@ -112,9 +128,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -123,10 +139,14 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:21:20
|
||||
gem5 started Sep 22 2013 06:52:30
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -59,12 +65,17 @@ workload=system.cpu.workload
|
|||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,12 +86,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -109,15 +130,24 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -137,16 +167,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -157,16 +188,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -185,9 +224,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -196,10 +235,14 @@ simpoint=55300000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:21:20
|
||||
gem5 started Sep 22 2013 06:32:00
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,6 +30,11 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -121,11 +128,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +138,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +152,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -431,10 +445,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -445,12 +459,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -500,16 +523,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -528,9 +559,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -539,10 +570,14 @@ simpoint=114600000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -576,6 +616,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 01:41:39
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 07:58:36
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -69,4 +69,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 199986318000 because target called exit()
|
||||
Exiting @ tick 202349747500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
|
@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
|
@ -120,9 +129,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -131,11 +140,16 @@ simpoint=114600000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-ato
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 20:09:03
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 09:00:02
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,12 +81,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -110,12 +125,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -165,17 +189,26 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -192,9 +225,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -203,11 +236,16 @@ simpoint=114600000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-tim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 20:10:40
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:48:54
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,9 +30,14 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -113,6 +120,11 @@ workload=system.cpu.workload
|
|||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BranchPredictor
|
||||
BTBEntries=4096
|
||||
|
|
@ -121,11 +133,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +143,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +157,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -430,10 +450,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -444,15 +464,24 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -472,16 +501,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -492,16 +522,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -520,9 +558,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -531,10 +569,14 @@ simpoint=114600000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -568,6 +615,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,15 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 18 2013 13:37:41
|
||||
gem5 started Apr 18 2013 14:16:02
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:21:20
|
||||
gem5 started Sep 22 2013 07:10:19
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *********info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
****************************************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
|
@ -25,6 +24,7 @@ Processing sentences in batch mode
|
|||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -81,4 +81,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 434543595000 because target called exit()
|
||||
Exiting @ tick 458201684000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
children=apic_clk_domain dtb interrupts isa itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -63,6 +72,11 @@ workload=system.cpu.workload
|
|||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -97,7 +112,8 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
|
|
@ -112,9 +128,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -123,10 +139,14 @@ simpoint=114600000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:21:20
|
||||
gem5 started Sep 22 2013 06:21:35
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -59,12 +65,17 @@ workload=system.cpu.workload
|
|||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,12 +86,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -109,15 +130,24 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clock=8000
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
|
@ -137,16 +167,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -157,16 +188,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -185,9 +224,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -196,10 +235,14 @@ simpoint=114600000000
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 06:21:20
|
||||
gem5 started Sep 22 2013 06:48:16
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,6 +30,11 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
|
|
@ -36,7 +42,7 @@ activity=0
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=2
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
div16Latency=1
|
||||
div16RepeatRate=1
|
||||
|
|
@ -66,6 +72,7 @@ multRepeatRate=1
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
stageTracing=false
|
||||
stageWidth=4
|
||||
switched_out=false
|
||||
|
|
@ -84,11 +91,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -96,10 +101,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -110,22 +115,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -136,12 +150,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -154,10 +177,10 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -168,17 +191,26 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -195,7 +227,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -206,11 +238,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -218,27 +255,38 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
addr_mapping=openmap
|
||||
activation_limit=4
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:33:34
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 09:53:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -13,4 +11,4 @@ info: Increasing stack size by one page.
|
|||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.133333
|
||||
Exiting @ tick 139846906500 because target called exit()
|
||||
Exiting @ tick 139916242500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,6 +30,11 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -121,11 +128,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +138,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +152,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
|
@ -422,10 +436,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -436,12 +450,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -454,10 +477,10 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -468,16 +491,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -496,7 +527,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -507,10 +538,14 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -544,6 +584,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:39
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 09:53:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -13,4 +11,4 @@ info: Increasing stack size by one page.
|
|||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.066667
|
||||
Exiting @ tick 77333664500 because target called exit()
|
||||
Exiting @ tick 77521581000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -88,7 +97,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -99,11 +108,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 14:04:20
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 09:53:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,22 +81,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -101,12 +116,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -119,10 +143,10 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -133,17 +157,26 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -160,7 +193,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -171,11 +204,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:49:24
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 09:53:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,6 +30,11 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -121,11 +128,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +138,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +152,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -431,10 +445,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -445,12 +459,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -500,16 +523,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -528,7 +559,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -539,10 +570,14 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -576,6 +616,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 03:18:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:27:24
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -15,4 +15,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.060000
|
||||
Exiting @ tick 68258363000 because target called exit()
|
||||
Exiting @ tick 68375005500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
|
@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
|
@ -120,7 +129,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -131,11 +140,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 20:20:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 09:21:07
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,12 +81,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -110,12 +125,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -165,17 +189,26 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -192,7 +225,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -203,11 +236,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 20:24:50
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:19:15
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,6 +30,11 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -121,11 +128,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +138,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +152,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
|
@ -422,10 +436,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -436,12 +450,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -454,10 +477,10 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -468,16 +491,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -496,7 +527,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -507,10 +538,14 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -544,6 +584,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 09:53:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -1387,4 +1385,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 626014950000 because target called exit()
|
||||
Exiting @ tick 631883288500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -88,7 +97,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -99,11 +108,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 14:44:11
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 09:53:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -52,6 +57,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -75,22 +81,31 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -101,12 +116,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
|
|
@ -119,10 +143,10 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -133,17 +157,26 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -160,7 +193,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -171,11 +204,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:29:25
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 24 2013 03:08:53
|
||||
gem5 started Sep 28 2013 09:53:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,6 +30,11 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
|
|
@ -43,7 +49,7 @@ backComSize=5
|
|||
branchPred=system.cpu.branchPred
|
||||
cachePorts=200
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
@ -92,6 +98,7 @@ renameToFetchDelay=1
|
|||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
|
|
@ -121,11 +128,9 @@ RASSize=16
|
|||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
|
|
@ -133,10 +138,10 @@ predType=tournament
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -147,12 +152,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
|
|
@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
|
@ -431,10 +445,10 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
|
@ -445,12 +459,21 @@ prefetcher=Null
|
|||
response_latency=2
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=2
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
|
|
@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
|
@ -500,16 +523,24 @@ prefetcher=Null
|
|||
response_latency=20
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
hit_latency=20
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -528,7 +559,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -539,10 +570,14 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
addr_mapping=RaBaChCo
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
devices_per_rank=8
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
|
|
@ -576,6 +616,9 @@ tWTR=7500
|
|||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 02:55:03
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:57:23
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -1387,4 +1387,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 627426486000 because target called exit()
|
||||
Exiting @ tick 640648369500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -29,12 +30,16 @@ work_end_exit_count=0
|
|||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -53,6 +58,10 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
|
|
@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
|
|||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
|
@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
|
|||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clock=500
|
||||
clk_domain=system.cpu_clk_domain
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
|
@ -120,7 +129,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -131,11 +140,16 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clk_domain=system.clk_domain
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
|
|||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue