fbc1feb39a
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
173 lines
3.3 KiB
INI
173 lines
3.3 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
full_system=false
|
|
time_sync_enable=false
|
|
time_sync_period=100000000000
|
|
time_sync_spin_threshold=100000000
|
|
|
|
[system]
|
|
type=System
|
|
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|
boot_osflags=a
|
|
cache_line_size=64
|
|
clk_domain=system.clk_domain
|
|
init_param=0
|
|
kernel=
|
|
load_addr_mask=1099511627775
|
|
mem_mode=atomic
|
|
mem_ranges=
|
|
memories=system.physmem
|
|
num_work_ids=16
|
|
readfile=
|
|
symbolfile=
|
|
work_begin_ckpt_count=0
|
|
work_begin_cpu_id_exit=-1
|
|
work_begin_exit_count=0
|
|
work_cpus_ckpt_count=0
|
|
work_end_ckpt_count=0
|
|
work_end_exit_count=0
|
|
work_item_id=-1
|
|
system_port=system.membus.slave[0]
|
|
|
|
[system.clk_domain]
|
|
type=SrcClockDomain
|
|
clock=1000
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.cpu]
|
|
type=AtomicSimpleCPU
|
|
children=dtb interrupts isa itb tracer workload
|
|
checker=Null
|
|
clk_domain=system.cpu_clk_domain
|
|
cpu_id=0
|
|
do_checkpoint_insts=true
|
|
do_quiesce=true
|
|
do_statistics_insts=true
|
|
dtb=system.cpu.dtb
|
|
fastmem=false
|
|
function_trace=false
|
|
function_trace_start=0
|
|
interrupts=system.cpu.interrupts
|
|
isa=system.cpu.isa
|
|
itb=system.cpu.itb
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
numThreads=1
|
|
profile=0
|
|
progress_interval=0
|
|
simpoint_interval=100000000
|
|
simpoint_profile=false
|
|
simpoint_profile_file=simpoint.bb.gz
|
|
simpoint_start_insts=
|
|
simulate_data_stalls=false
|
|
simulate_inst_stalls=false
|
|
switched_out=false
|
|
system=system
|
|
tracer=system.cpu.tracer
|
|
width=1
|
|
workload=system.cpu.workload
|
|
dcache_port=system.membus.slave[2]
|
|
icache_port=system.membus.slave[1]
|
|
|
|
[system.cpu.dtb]
|
|
type=ArmTLB
|
|
children=walker
|
|
size=64
|
|
walker=system.cpu.dtb.walker
|
|
|
|
[system.cpu.dtb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.membus.slave[4]
|
|
|
|
[system.cpu.interrupts]
|
|
type=ArmInterrupts
|
|
|
|
[system.cpu.isa]
|
|
type=ArmISA
|
|
fpsid=1090793632
|
|
id_isar0=34607377
|
|
id_isar1=34677009
|
|
id_isar2=555950401
|
|
id_isar3=17899825
|
|
id_isar4=268501314
|
|
id_isar5=0
|
|
id_mmfr0=3
|
|
id_mmfr1=0
|
|
id_mmfr2=19070976
|
|
id_mmfr3=4027589137
|
|
id_pfr0=49
|
|
id_pfr1=1
|
|
midr=890224640
|
|
|
|
[system.cpu.itb]
|
|
type=ArmTLB
|
|
children=walker
|
|
size=64
|
|
walker=system.cpu.itb.walker
|
|
|
|
[system.cpu.itb.walker]
|
|
type=ArmTableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
num_squash_per_cycle=2
|
|
sys=system
|
|
port=system.membus.slave[3]
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
|
|
[system.cpu.workload]
|
|
type=LiveProcess
|
|
cmd=parser 2.1.dict -batch
|
|
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
|
egid=100
|
|
env=
|
|
errout=cerr
|
|
euid=100
|
|
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
|
gid=100
|
|
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
|
max_stack_size=67108864
|
|
output=cout
|
|
pid=100
|
|
ppid=99
|
|
simpoint=114600000000
|
|
system=system
|
|
uid=100
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.membus]
|
|
type=CoherentBus
|
|
clk_domain=system.clk_domain
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=8
|
|
master=system.physmem.port
|
|
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
|
|
|
[system.physmem]
|
|
type=SimpleMemory
|
|
bandwidth=73.000000
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
in_addr_map=true
|
|
latency=30000
|
|
latency_var=0
|
|
null=false
|
|
range=0:134217727
|
|
port=system.membus.master[0]
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
voltage=1.000000
|
|
|