Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
This commit is contained in:
Andreas Hansson
parent
1c321b8847
commit
54227f9e57
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,14 +1,14 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.274137 # Number of seconds simulated
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sim_ticks 274137453500 # Number of ticks simulated
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final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.271545 # Number of seconds simulated
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sim_ticks 271544682500 # Number of ticks simulated
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final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 134061 # Simulator instruction rate (inst/s)
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host_op_rate 134061 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 61063086 # Simulator tick rate (ticks/s)
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host_mem_usage 219148 # Number of bytes of host memory used
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host_seconds 4489.41 # Real time elapsed on the host
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host_inst_rate 105483 # Simulator instruction rate (inst/s)
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host_op_rate 105483 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 47591638 # Simulator tick rate (ticks/s)
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host_mem_usage 219440 # Number of bytes of host memory used
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host_seconds 5705.72 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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sim_ops 601856964 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
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@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data 25316 # Nu
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system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 114518787 # DTB read hits
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system.cpu.dtb.read_hits 114517787 # DTB read hits
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system.cpu.dtb.read_misses 2631 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 114521418 # DTB read accesses
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system.cpu.dtb.write_hits 39662426 # DTB write hits
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system.cpu.dtb.read_accesses 114520418 # DTB read accesses
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system.cpu.dtb.write_hits 39661840 # DTB write hits
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system.cpu.dtb.write_misses 2302 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 39664728 # DTB write accesses
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system.cpu.dtb.data_hits 154181213 # DTB hits
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system.cpu.dtb.write_accesses 39664142 # DTB write accesses
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system.cpu.dtb.data_hits 154179627 # DTB hits
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system.cpu.dtb.data_misses 4933 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 154186146 # DTB accesses
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system.cpu.itb.fetch_hits 25086764 # ITB hits
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system.cpu.dtb.data_accesses 154184560 # DTB accesses
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system.cpu.itb.fetch_hits 25070818 # ITB hits
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system.cpu.itb.fetch_misses 22 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 25086786 # ITB accesses
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system.cpu.itb.fetch_accesses 25070840 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 548274908 # number of cpu cycles simulated
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system.cpu.numCycles 543089366 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits
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system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File
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system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 36895090 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 49414915 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 541552617 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
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system.cpu.regfile_manager.intRegFileAccesses 1005407463 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 155050348 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed.
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system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 255071199 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 155051796 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 2591546 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 36349330 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.threadCycles 538349706 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed.
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system.cpu.activity 89.213788 # Percentage of cycles cpu is active
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system.cpu.timesIdled 387700 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 53984537 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 489104829 # Number of cycles cpu stages are processed.
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system.cpu.activity 90.059732 # Percentage of cycles cpu is active
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system.cpu.comLoads 114514042 # Number of Load instructions committed
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system.cpu.comStores 39451321 # Number of Store instructions committed
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system.cpu.comBranches 62547159 # Number of Branches instructions committed
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@ -114,144 +114,144 @@ system.cpu.committedInsts 601856964 # Nu
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system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
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system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.cpi 0.902356 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.cpi_total 0.902356 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.108210 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.ipc_total 1.108210 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 204234221 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 338855145 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 62.393994 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 232262845 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 310826521 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 57.233034 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 201309957 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 341779409 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 62.932444 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 431519146 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 111570220 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 20.543621 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 196111910 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 346977456 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 63.889569 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 30 # number of replacements
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system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use
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system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks.
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system.cpu.icache.tagsinuse 729.073717 # Cycle average of tags in use
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system.cpu.icache.total_refs 25069794 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks.
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system.cpu.icache.avg_refs 29321.396491 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits
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system.cpu.icache.overall_hits::total 25085741 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
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system.cpu.icache.overall_misses::total 1021 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses
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system.cpu.icache.occ_blocks::cpu.inst 729.073717 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.355993 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.355993 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 25069794 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 25069794 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 25069794 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 25069794 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 25069794 # number of overall hits
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system.cpu.icache.overall_hits::total 25069794 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses
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system.cpu.icache.overall_misses::total 1022 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 56347500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 56347500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 56347500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 56347500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 56347500 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 56347500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 25070816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25070816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25070816 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25070816 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25070816 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25070816 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55134.540117 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55134.540117 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55134.540117 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46510500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46510500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46510500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54398.245614 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54398.245614 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4094.014631 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 152406162 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 152406041 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1559322 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles
|
||||
system.cpu.dcache.avg_refs 334.668062 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 268976000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.014631 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999515 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999515 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38285655 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38285655 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 152406162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 152406162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 152406162 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 152406162 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1165666 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1165666 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1559201 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1559201 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1559201 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1559201 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5490501500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5490501500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16777875500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 16777875500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22268377000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22268377000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22268377000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22268377000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363
|
|||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13951.748891 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13951.748891 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14393.381552 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 14393.381552 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436902 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911503 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 911503 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1103806 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1103806 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1103806 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1103806 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
|
|
@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395605000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395605000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3804662000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3804662000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6200267000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6200267000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6200267000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6200267000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11904.692097 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11904.692097 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14969.377919 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14969.377919 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 917 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 22852.343306 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21651.877416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 719.990292 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 480.475597 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.660763 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021972 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014663 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.697398 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits
|
||||
|
|
@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total 26157 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 215882000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 261384000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220308500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1220308500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45502000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1436190500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1481692500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45502000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1436190500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1481692500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
|
||||
|
|
@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855
|
|||
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083387 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54104.637337 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52398.543689 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52687.764564 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57572.584450 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57572.584450 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total 26157
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35251500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165390500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200642000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 961154000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 961154000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35251500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1126544500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1161796000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35251500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1126544500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1161796000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41916.171225 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.325243 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40443.862125 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.764109 # Number of seconds simulated
|
||||
sim_ticks 764109115000 # Number of ticks simulated
|
||||
final_tick 764109115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.762398 # Number of seconds simulated
|
||||
sim_ticks 762397656000 # Number of ticks simulated
|
||||
final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2465110 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2465110 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3129668646 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 218984 # Number of bytes of host memory used
|
||||
host_seconds 244.15 # Real time elapsed on the host
|
||||
host_inst_rate 1514073 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1917939864 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219440 # Number of bytes of host memory used
|
||||
host_seconds 397.51 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25315 # Nu
|
|||
system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 883 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 65582 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2120325 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2185908 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 65582 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 65582 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 73958 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 73958 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 73958 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 65582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2120325 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2259866 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 1528218230 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1524795312 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 601856964 # Number of instructions committed
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu
|
|||
system.cpu.num_load_insts 114516673 # Number of load instructions
|
||||
system.cpu.num_store_insts 39453623 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1528218230 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1524795312 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.tagsinuse 673.286058 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 673.286058 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.328753 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.328753 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
|
||||
|
|
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n
|
|||
system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 795 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44165000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44165000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44165000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44165000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44165000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44165000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
|
||||
|
|
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
|
|||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55553.459119 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55553.459119 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795
|
|||
system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41780000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 41780000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41780000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 41780000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41780000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 41780000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.128141 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 590218000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.128141 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
|
||||
|
|
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n
|
|||
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2991812000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2991812000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4452609000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4452609000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7444421000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7444421000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7444421000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7444421000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16347.173333 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16347.173333 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2388116000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2388116000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3690120000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3690120000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078236000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6078236000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078236000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6078236000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 903 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22839.375690 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21645.673483 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 668.235332 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 525.466875 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.660574 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.020393 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.016036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.697002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.795271 # Number of seconds simulated
|
||||
sim_ticks 795270546000 # Number of ticks simulated
|
||||
final_tick 795270546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.793710 # Number of seconds simulated
|
||||
sim_ticks 793709507000 # Number of ticks simulated
|
||||
final_tick 793709507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1274959 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1346403 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1783406999 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227740 # Number of bytes of host memory used
|
||||
host_seconds 445.93 # Real time elapsed on the host
|
||||
host_inst_rate 1083083 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1143775 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1512037928 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233820 # Number of bytes of host memory used
|
||||
host_seconds 524.93 # Real time elapsed on the host
|
||||
sim_insts 568539335 # Number of instructions simulated
|
||||
sim_ops 600398272 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 27110 # Nu
|
|||
system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 49171 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2181698 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2230868 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 49171 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 49171 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 244888 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 244888 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 244888 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 49171 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2181698 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2475756 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 49267 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2185989 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2235256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 49267 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 49267 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 245369 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 245369 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 245369 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 49267 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2185989 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2480625 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1590541092 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1587419014 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 568539335 # Number of instructions committed
|
||||
|
|
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 219173606 # nu
|
|||
system.cpu.num_load_insts 148952593 # Number of load instructions
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1590541092 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1587419014 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 12 # number of replacements
|
||||
system.cpu.icache.tagsinuse 577.715333 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 577.773227 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 577.715333 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.282088 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.282088 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 577.773227 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits
|
||||
|
|
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n
|
|||
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 643 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34792000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34792000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34792000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34792000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34021000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34021000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34021000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34021000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34021000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34021000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
|
||||
|
|
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
|
|||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54108.864697 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54108.864697 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54108.864697 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54108.864697 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52909.797823 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52909.797823 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52909.797823 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52909.797823 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643
|
|||
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32863000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32863000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32863000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32863000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32863000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32863000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51108.864697 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51108.864697 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 433468 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.191707 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.242161 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 547974000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.191707 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999559 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999559 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 529482000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.242161 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
|
||||
|
|
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n
|
|||
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2866972000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2866972000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4400884000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4400884000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7267856000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7267856000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7267856000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7267856000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2675478000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2675478000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4151654000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4151654000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6827132000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6827132000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6827132000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6827132000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.953302 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.953302 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17763.550059 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17763.550059 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16609.812507 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16609.812507 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14095.113162 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14095.113162 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16757.568174 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 16757.568174 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15602.590707 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15602.590707 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564
|
|||
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2297524000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2297524000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3657640000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3657640000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5955164000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5955164000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5955164000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5955164000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295846000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295846000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5952004000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5952004000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5952004000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5952004000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.953302 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.953302 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14763.550059 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14763.550059 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12095.113162 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12095.113162 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 3963 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21579.150724 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 21582.814171 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 20939.895204 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 130.071130 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 509.184390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.639035 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003969 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.658543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 20943.692003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 130.073000 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 509.049168 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.639151 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015535 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.658655 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits
|
||||
|
|
@ -323,16 +323,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 611 #
|
|||
system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 27721 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257140000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 288912000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257320000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 289092000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1409720000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1441492000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1409900000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1441672000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1409720000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1441492000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1409900000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1441672000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -358,16 +358,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.400404 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52032.397408 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52006.493272 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52006.493272 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -390,16 +390,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 611
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197980000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222420000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1108840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084580000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1109020000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1108840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084580000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1109020000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -412,16 +412,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40036.400404 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40032.397408 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.063178 # Number of seconds simulated
|
||||
sim_ticks 2063177737000 # Number of ticks simulated
|
||||
final_tick 2063177737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.061067 # Number of seconds simulated
|
||||
sim_ticks 2061066683000 # Number of ticks simulated
|
||||
final_tick 2061066683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1527975 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1532517 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2122729697 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231576 # Number of bytes of host memory used
|
||||
host_seconds 971.95 # Real time elapsed on the host
|
||||
host_inst_rate 1352034 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1356054 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1876383782 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222536 # Number of bytes of host memory used
|
||||
host_seconds 1098.43 # Real time elapsed on the host
|
||||
sim_insts 1485108088 # Number of instructions simulated
|
||||
sim_ops 1489523282 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory
|
||||
|
|
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26134 # Nu
|
|||
system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 31858 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 810680 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 842537 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 31858 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 31858 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 78264 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 78264 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 78264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 31858 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 31890 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 811510 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 843400 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 31890 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 31890 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 78344 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 78344 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 78344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 31890 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 811510 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 921744 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 4126355474 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4122133366 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1485108088 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365766 # nu
|
|||
system.cpu.num_load_insts 402515345 # Number of load instructions
|
||||
system.cpu.num_store_insts 166850421 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4126355474 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4122133366 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 118 # number of replacements
|
||||
system.cpu.icache.tagsinuse 906.409378 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 906.468708 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 906.409378 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 906.468708 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n
|
|||
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1107 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58777000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 58777000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 58777000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 57527000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 57527000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 57527000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 57527000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 57527000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 57527000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
|
|||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53095.754291 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53095.754291 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53095.754291 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53095.754291 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51966.576332 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 51966.576332 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 51966.576332 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 51966.576332 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107
|
|||
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55456000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 55456000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55456000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 55456000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55456000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 55456000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55313000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 55313000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55313000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 55313000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55313000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 55313000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50095.754291 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50095.754291 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49966.576332 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49966.576332 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 449125 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.205181 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.236029 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 588931000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.205181 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 559332000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.236029 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
|
||||
|
|
@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n
|
|||
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888728000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2888728000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554574000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4554574000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4294542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6989368000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6989368000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6989368000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6989368000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14929.907073 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14929.907073 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17535.937596 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17535.937596 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16423.371741 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16423.371741 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.767141 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.767141 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15421.783087 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15421.783087 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214
|
|||
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2308270000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2308270000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775390000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775390000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6083660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6083660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6083660000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6083660000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11929.907073 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11929.907073 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14535.937596 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14535.937596 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2614 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22185.384813 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 22187.209427 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 20828.536507 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 857.441709 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 499.406597 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.677044 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 20830.496331 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 857.499465 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 499.213631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.635696 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.026169 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015235 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.677100 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits
|
||||
|
|
@ -292,17 +292,17 @@ system.cpu.l2cache.demand_misses::total 27161 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 27161 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53404000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53406000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 275652000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 275654000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 53404000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 53406000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1412372000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 53404000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1412374000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 53406000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1412372000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1412374000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -327,17 +327,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.059783 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.947420 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.377287 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.073635 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.073635 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -359,17 +359,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27161
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41082000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212042000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41082000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1086440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41080000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1086442000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41082000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1086440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1086442000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.947420 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.377287 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.801980 # Number of seconds simulated
|
||||
sim_ticks 1801979679000 # Number of ticks simulated
|
||||
final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.800193 # Number of seconds simulated
|
||||
sim_ticks 1800193072000 # Number of ticks simulated
|
||||
final_tick 1800193072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 528145 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 973136 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1081454463 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274856 # Number of bytes of host memory used
|
||||
host_seconds 1666.26 # Real time elapsed on the host
|
||||
host_inst_rate 480678 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 885676 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 983283018 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228792 # Number of bytes of host memory used
|
||||
host_seconds 1830.80 # Real time elapsed on the host
|
||||
sim_insts 880025278 # Number of instructions simulated
|
||||
sim_ops 1621493926 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
|
||||
|
|
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26287 # Nu
|
|||
system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 25643 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 933622 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 959265 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 25643 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 25643 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 89146 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 89146 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 89146 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 25643 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 934549 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 89235 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 89235 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 89235 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 934549 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1049452 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 3603959358 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3600386144 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 880025278 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228178 # nu
|
|||
system.cpu.num_load_insts 419042121 # Number of load instructions
|
||||
system.cpu.num_store_insts 188186057 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3603959358 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3600386144 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 4 # number of replacements
|
||||
system.cpu.icache.tagsinuse 660.169550 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 660.197374 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 660.169550 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 660.197374 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n
|
|||
system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 722 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40521000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 40521000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 40521000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39710000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 39710000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 39710000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 39710000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 39710000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 39710000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
|
|||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56123.268698 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56123.268698 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56123.268698 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56123.268698 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722
|
|||
system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 38355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38355000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 38355000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38355000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 38355000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53123.268698 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53123.268698 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.884130 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.905905 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 788810000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.884130 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 771462000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.905905 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n
|
|||
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2948308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2948308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4362877000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4362877000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7311185000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4104707000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4104707000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6851259000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6851259000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6851259000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6851259000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.305251 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.305251 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17827.890423 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17827.890423 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16539.346406 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16539.346406 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16772.938273 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 16772.938273 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15498.902834 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15498.902834 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048
|
|||
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2356330000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2356330000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3628711000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3628711000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5985041000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5985041000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5985041000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5985041000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615263000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615263000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967163000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5967163000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967163000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5967163000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11941.305251 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11941.305251 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14827.890423 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14827.890423 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14772.938273 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14772.938273 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2581 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22161.850174 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 22163.399604 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21018.400685 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 596.832055 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 546.617434 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.676326 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21020.012941 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 596.858262 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 546.528401 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.641480 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.018215 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.676373 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits
|
||||
|
|
@ -272,14 +272,14 @@ system.cpu.l2cache.overall_misses::total 27009 # nu
|
|||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1142440000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1142440000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143021000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1143021000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1366924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1404468000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1367505000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1405049000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1366924000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1404468000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1367505000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1405049000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -307,14 +307,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.061000 #
|
|||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.445152 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.445152 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52021.511348 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52021.511348 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -339,14 +339,14 @@ system.cpu.l2cache.overall_mshr_misses::total 27009
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201560000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 878800000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 878800000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879381000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879381000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1051480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1080360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052061000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1080941000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1051480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1080360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052061000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1080941000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -361,14 +361,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40026.445152 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40026.445152 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.148268 # Number of seconds simulated
|
||||
sim_ticks 148267705000 # Number of ticks simulated
|
||||
final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.147136 # Number of seconds simulated
|
||||
sim_ticks 147135976000 # Number of ticks simulated
|
||||
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1153616 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1161887 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1888384270 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 360564 # Number of bytes of host memory used
|
||||
host_seconds 78.52 # Real time elapsed on the host
|
||||
host_inst_rate 1039833 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1047288 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1689137215 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 366884 # Number of bytes of host memory used
|
||||
host_seconds 87.11 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91226312 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 36992 # Nu
|
|||
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 249495 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6372042 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6621536 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 249495 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 249495 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 249495 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6372042 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6621536 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 251414 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6421054 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6672467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 251414 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 251414 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 296535410 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 294271952 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90576861 # Number of instructions committed
|
||||
|
|
@ -89,18 +89,18 @@ system.cpu.num_mem_refs 27318810 # nu
|
|||
system.cpu.num_load_insts 22573966 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 296535410 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 294271952 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 2 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.369252 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.369252 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.249204 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.249204 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
|
||||
|
|
@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n
|
|||
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 599 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32709000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32709000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32709000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32709000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32709000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32709000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32063000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32063000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32063000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32063000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32063000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32063000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
|
||||
|
|
@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006
|
|||
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54606.010017 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54606.010017 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54606.010017 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54606.010017 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599
|
|||
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 30912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30912000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 30912000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30912000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 30912000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51606.010017 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51606.010017 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3568.972050 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 54491057000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3568.972050 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.871331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.871331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
|
||||
|
|
@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n
|
|||
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12648933000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12648933000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1288595000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1288595000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13937528000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13937528000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13937528000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13937528000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701
|
|||
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14051.419202 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14051.419202 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27646.913686 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27646.913686 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14720.698607 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14720.698607 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798
|
|||
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9948366000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9948366000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148768000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148768000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11097134000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11097134000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11097134000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11097134000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11051.419202 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11051.419202 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24646.913686 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24646.913686 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9602.986186 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8914.312589 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 495.421771 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 193.251826 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.272043 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.015119 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.293060 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.362482 # Number of seconds simulated
|
||||
sim_ticks 362481563000 # Number of ticks simulated
|
||||
final_tick 362481563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.361489 # Number of seconds simulated
|
||||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1415125 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1415183 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2103788292 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 363728 # Number of bytes of host memory used
|
||||
host_seconds 172.30 # Real time elapsed on the host
|
||||
host_inst_rate 1171246 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1171295 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1736457304 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354676 # Number of bytes of host memory used
|
||||
host_seconds 208.18 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
|
|
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 56256 # Nu
|
|||
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 724963126 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 722977060 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 243825150 # Number of instructions committed
|
||||
|
|
@ -47,18 +47,18 @@ system.cpu.num_mem_refs 105711441 # nu
|
|||
system.cpu.num_load_insts 82803521 # Number of load instructions
|
||||
system.cpu.num_store_insts 22907920 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 724963126 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 722977060 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 25 # number of replacements
|
||||
system.cpu.icache.tagsinuse 725.564713 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 725.564713 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
|
||||
|
|
@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n
|
|||
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
|
||||
|
|
@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
|
|||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55933.106576 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55933.106576 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882
|
|||
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46687000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46687000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46687000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46687000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46687000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46687000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3563.804941 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 134384267000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3563.804941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
||||
|
|
@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
|
|||
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12510586000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12510586000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14664.344320 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14664.344320 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -217,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
|
|||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9832015000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9832015000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1127418000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1127418000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 89000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 89000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10959433000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10959433000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10959433000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10959433000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -237,30 +237,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9744.633464 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8861.505031 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 738.799835 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 144.328599 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.297383 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.368209 # Number of seconds simulated
|
||||
sim_ticks 368209206000 # Number of ticks simulated
|
||||
final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.365994 # Number of seconds simulated
|
||||
sim_ticks 365994481000 # Number of ticks simulated
|
||||
final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 501886 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 883741 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1169699500 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 408944 # Number of bytes of host memory used
|
||||
host_seconds 314.79 # Real time elapsed on the host
|
||||
host_inst_rate 452383 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 796575 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1047986231 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 363904 # Number of bytes of host memory used
|
||||
host_seconds 349.24 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192463 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
|
||||
|
|
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 29370 # Nu
|
|||
system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5104924 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5245366 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5104924 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5284822 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 736418412 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 731988962 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988548 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 122219135 # nu
|
|||
system.cpu.num_load_insts 90779384 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439751 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 736418412 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 731988962 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.tagsinuse 665.897748 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 665.897748 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n
|
|||
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 45336000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 45336000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 45336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
|
|||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56108.910891 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56108.910891 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56108.910891 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56108.910891 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808
|
|||
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42912000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42912000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42912000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42912000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53108.910891 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53108.910891 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.463619 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126234066000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.463619 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
|
|||
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27487330000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 27487330000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2708348000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2708348000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14018.998123 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14018.998123 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25524.206241 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25524.206241 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14609.664370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14609.664370 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
|
|||
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21605170000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21605170000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2390019500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2390019500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23995189500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23995189500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23995189500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23995189500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386364000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386364000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23968690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968690000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23968690000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11018.998123 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11018.998123 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22524.192104 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22524.192104 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.741681 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.741681 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1081 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 19722.099231 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 19679.255550 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 19370.045173 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 209.723718 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 142.330341 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.601871 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 19326.193704 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 210.694953 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 142.366893 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.589789 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.006430 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004345 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.600563 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits
|
||||
|
|
@ -272,14 +272,14 @@ system.cpu.l2cache.overall_misses::total 30178 # nu
|
|||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509433500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1509433500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509435000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1509435000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1527269500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1569285500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1527271000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1569287000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1527269500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1569285500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1527271000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1569287000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -307,14 +307,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.014595 #
|
|||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.016295 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.016295 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.067971 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.067971 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.977533 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52001.027238 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.977533 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52001.027238 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.720346 # Number of seconds simulated
|
||||
sim_ticks 720345914000 # Number of ticks simulated
|
||||
final_tick 720345914000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.717833 # Number of seconds simulated
|
||||
sim_ticks 717832876000 # Number of ticks simulated
|
||||
final_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1112468 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1253563 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1586896277 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231144 # Number of bytes of host memory used
|
||||
host_seconds 453.93 # Real time elapsed on the host
|
||||
host_inst_rate 1074460 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1210735 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1527332222 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237040 # Number of bytes of host memory used
|
||||
host_seconds 469.99 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 150998 # Nu
|
|||
system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 247614 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 13415599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13663213 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 247614 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 247614 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 9127171 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 9127171 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 9127171 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 247614 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 13415599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 22790384 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1440691828 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1435665752 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504986853 # Number of instructions committed
|
||||
|
|
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 182890034 # nu
|
|||
system.cpu.num_load_insts 126029555 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1440691828 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1435665752 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tagsinuse 983.378720 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 983.378720 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.480165 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.480165 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
|
||||
|
|
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
|
|||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 279753000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 279753000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 279753000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 279753000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 279753000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 279753000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
|
||||
|
|
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
|
|||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24282.006770 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24282.006770 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24282.006770 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24282.006770 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
|
|||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 245190000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 245190000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 245190000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 245190000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 245190000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 245190000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21282.006770 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21282.006770 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4065.381389 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11899663000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4065.381389 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.992525 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.992525 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
|
|
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n
|
|||
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13181704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 13181704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327564000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9327564000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22509268000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22509268000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22509268000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22509268000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399
|
|||
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16842.227384 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 16842.227384 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26181.900859 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26181.900859 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19763.730137 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19763.730137 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918
|
|||
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10833730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10833730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8258784000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8258784000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19092514000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 19092514000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19092514000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 19092514000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10613061000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10613061000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257505000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257505000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870566000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 18870566000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870566000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 18870566000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13842.227384 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13842.227384 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23181.900859 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23181.900859 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13560.279202 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13560.279202 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.310784 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.310784 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 122482 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 26939.836590 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 26931.505779 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 344531371000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 23226.765026 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 246.719769 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 3466.351794 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.708825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.007529 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.105785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.822139 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.warmup_cycle 343812481000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 23220.335885 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 246.652044 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 3464.517849 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.708628 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.007527 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.105729 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.821884 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits
|
||||
|
|
@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 153785 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 153785 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144924000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480244000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2625168000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371652000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5371652000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7851896000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7996820000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144924000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7851896000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7996820000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144931000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480793000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2625724000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371655000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5371655000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144931000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7852448000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7997379000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144931000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7852448000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7997379000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.133675 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.511661 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52011.510158 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.013390 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.029041 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.029041 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52003.634945 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52003.634945 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 153785
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111480000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1907880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019360000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6039920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6151400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6039920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6151400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111487000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1908429000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019916000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132043000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132043000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111487000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6040472000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6151959000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111487000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6040472000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6151959000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.511661 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40011.510158 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.013390 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.029041 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.029041 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.652607 # Number of seconds simulated
|
||||
sim_ticks 1652606827000 # Number of ticks simulated
|
||||
final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.649901 # Number of seconds simulated
|
||||
sim_ticks 1649900881000 # Number of ticks simulated
|
||||
final_tick 1649900881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 548890 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1014960 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1097019218 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278012 # Number of bytes of host memory used
|
||||
host_seconds 1506.45 # Real time elapsed on the host
|
||||
host_inst_rate 669860 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1238647 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1336598464 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232964 # Number of bytes of host memory used
|
||||
host_seconds 1234.40 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988700 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
|
||||
|
|
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 427498 # Nu
|
|||
system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 74904 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 16582737 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 16657641 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 74904 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 74904 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 12551348 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 12551348 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 12551348 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 74904 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 16582737 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 29208989 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3305213654 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3299801762 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877110 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262341 # nu
|
|||
system.cpu.num_load_insts 384102156 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3305213654 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3299801762 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 881.283724 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 881.283724 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430314 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430314 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n
|
|||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 117690500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 117690500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 117690500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 117690500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 117690500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 117690500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003
|
|||
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42925.373134 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42925.373134 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41823.205402 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 41823.205402 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 41823.205402 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 41823.205402 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
|
|||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112350000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 112350000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112350000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 112350000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112350000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 112350000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112062500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 112062500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112062500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 112062500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112062500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 112062500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39823.205402 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39823.205402 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4086.427569 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.427569 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997663 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997663 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n
|
|||
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31594062000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31594062000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100972000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19100972000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 50695034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 50695034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 50695034000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 50695034000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723
|
|||
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19314.579481 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19314.579481 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25147.278154 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25147.278154 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21146.621663 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21146.621663 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18289.803139 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 18289.803139 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24146.535465 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24146.535465 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 20129.394256 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 20129.394256 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458
|
|||
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28182031000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 28182031000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17519463000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17519463000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45701494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 45701494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45701494000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 45701494000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139234000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139234000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518884000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518884000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45658118000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 45658118000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45658118000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 45658118000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16314.578323 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16314.578323 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.803139 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.803139 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.535465 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.535465 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 403150 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 29110.547277 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.warmup_cycle 772497646000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21034.967888 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 79.712550 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7995.866840 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.641936 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.244014 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.888383 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits
|
||||
|
|
@ -272,17 +272,17 @@ system.cpu.l2cache.demand_misses::total 429429 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 429429 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100412000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313120000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11413532000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916779000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10916779000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 100412000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22229899000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22330311000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 100412000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22229899000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22330311000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100418500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313280000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11413698500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916780000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10916780000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 100418500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22230060000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22330478500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 100418500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22230060000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22330478500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -307,17 +307,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.170322 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.014290 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.014290 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.006986 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.006986 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.366132 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.735429 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.758573 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.019053 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.019053 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.397039 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.397039 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -339,17 +339,17 @@ system.cpu.l2cache.demand_mshr_misses::total 429429
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77246000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702551000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779797000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17099920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17177160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17099920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17177160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77246000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17100071000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17177317000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77246000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17100071000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17177317000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -361,17 +361,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.107198 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.694061 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.715291 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.141187 # Number of seconds simulated
|
||||
sim_ticks 141187061500 # Number of ticks simulated
|
||||
final_tick 141187061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.141181 # Number of seconds simulated
|
||||
sim_ticks 141180939500 # Number of ticks simulated
|
||||
final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 158597 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 158597 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56167220 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225028 # Number of bytes of host memory used
|
||||
host_seconds 2513.69 # Real time elapsed on the host
|
||||
host_inst_rate 88431 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 88431 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31316360 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225476 # Number of bytes of host memory used
|
||||
host_seconds 4508.22 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214592 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1519913 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1799145 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3319058 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1519913 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1519913 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1519913 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1799145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3319058 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -35,18 +35,18 @@ system.cpu.dtb.read_hits 94755019 # DT
|
|||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94755040 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73522100 # DTB write hits
|
||||
system.cpu.dtb.write_hits 73522102 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73522135 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168277119 # DTB hits
|
||||
system.cpu.dtb.write_accesses 73522137 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168277121 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168277175 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 49112134 # ITB hits
|
||||
system.cpu.itb.fetch_misses 88783 # ITB misses
|
||||
system.cpu.dtb.data_accesses 168277177 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 49111833 # ITB hits
|
||||
system.cpu.itb.fetch_misses 88782 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 49200917 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 49200615 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 282374124 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 282361880 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 53870034 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 30921446 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 16037248 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 33426490 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 15653868 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 46.830726 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 29683710 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24186324 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280818505 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 440154364 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119907678 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 220104159 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100457715 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168700471 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14475138 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 1561451 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 16036589 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 28550962 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 35.966517 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 205751085 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 2124334 # Number of Multipy Operations Executed
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168700458 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 281932231 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 9236 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13499283 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 268874841 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.219363 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.223370 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -107,72 +107,72 @@ system.cpu.committedInsts 398664595 # Nu
|
|||
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.708300 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.708300 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.411831 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.411831 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78560366 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 203813758 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.178624 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 108887705 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 173486419 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.438497 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 104664774 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177709350 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 62.934007 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 183592728 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98781396 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 34.982453 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 92681683 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189692441 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.177700 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1973 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1829.856986 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 49107743 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3900 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12591.728974 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1974 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1829.856986 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.893485 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.893485 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49107743 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 49107743 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 49107743 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 49107743 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 49107743 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 49107743 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4390 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4390 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4390 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4390 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4390 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4390 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 220305000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 220305000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 220305000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 220305000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 220305000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 220305000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 49112133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 49112133 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 49112133 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 49112133 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 49112133 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 49112133 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 49107443 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4389 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50183.371298 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 50183.371298 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 50183.371298 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 50183.371298 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49040.669856 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49040.669856 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49040.669856 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 490 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 490 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 490 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 490 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 490 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3900 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3900 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3900 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3900 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3900 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3900 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190927000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 190927000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190927000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 190927000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190927000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 190927000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 488 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 488 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 488 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 488 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 488 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190519000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 190519000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190519000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 190519000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190519000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 190519000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48955.641026 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48955.641026 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.502948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48838.502948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3284.708505 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168261813 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3284.744401 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168261808 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40525.484827 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40525.483622 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3284.708505 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.801931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.801931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3284.744401 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.801940 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.801940 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73508552 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73508552 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168261813 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168261813 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168261813 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168261813 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73508547 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73508547 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168261808 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168261808 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168261808 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168261808 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 12177 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 12177 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 13405 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 13405 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 13405 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 13405 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 68612500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 68612500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 712613500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 712613500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 781226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 781226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 781226000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 781226000 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 12182 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 12182 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 13410 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 13410 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 13410 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 13410 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65498000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 65498000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 641953000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 641953000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 707451000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 707451000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 707451000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 707451000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -261,32 +261,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000080
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55873.371336 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55873.371336 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58521.269607 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 58521.269607 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 58278.701977 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 58278.701977 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53337.133550 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 53337.133550 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52696.847808 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52696.847808 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 86009500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 85964000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1905 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 45149.343832 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 45078.133193 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8975 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 8975 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 9253 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 9253 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 9253 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 9253 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8980 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 8980 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 9258 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 9258 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 9258 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 9258 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
|
|
@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48743500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48743500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 176149500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 176149500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224893000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 224893000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224893000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 224893000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48495500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48495500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 175965000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 175965000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224460500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 224460500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224460500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 224460500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51308.947368 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51308.947368 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55012.336040 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55012.336040 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51047.894737 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51047.894737 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54954.715803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54954.715803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3900.249221 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3900.293758 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.159839 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.495467 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2902.223601 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.530153 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.502388 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2902.254610 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.536760 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088569 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088570 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119026 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 547 # number of ReadReq hits
|
||||
system.cpu.l2cache.occ_percent::total 0.119028 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 670 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 547 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 730 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 547 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 730 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 731 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses
|
||||
|
|
@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 7322 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7322 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180755000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45853500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 226608500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 171775500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 171775500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 180755000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 217629000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 398384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 180755000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 217629000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 398384000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 181079500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 181079500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 218267500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 399347000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4847 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 3900 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 8052 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 3900 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 8052 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859744 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.861770 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859744 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.909339 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859744 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909339 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53908.440203 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55647.451456 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54251.496289 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54618.600954 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54618.600954 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54409.177820 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54409.177820 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54540.699262 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 7322
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139951500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35886500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175838000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133424000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133424000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139951500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169310500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 309262000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139951500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169310500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 309262000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 140250000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176303500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133849000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140250000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 310152500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 310152500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861770 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909339 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909339 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41739.188786 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43551.577670 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42096.720134 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42424.165342 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42424.165342 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.567366 # Number of seconds simulated
|
||||
sim_ticks 567365869000 # Number of ticks simulated
|
||||
final_tick 567365869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.567335 # Number of seconds simulated
|
||||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2066411 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2066411 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2940844836 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224004 # Number of bytes of host memory used
|
||||
host_seconds 192.93 # Real time elapsed on the host
|
||||
host_inst_rate 1259990 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1259990 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1793077476 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225476 # Number of bytes of host memory used
|
||||
host_seconds 316.40 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 361530 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447711 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809241 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361530 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361530 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361530 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447711 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809241 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 361550 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447735 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809285 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361550 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361550 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 1134731738 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1134670186 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664609 # Number of instructions committed
|
||||
|
|
@ -79,18 +79,18 @@ system.cpu.num_mem_refs 168275276 # nu
|
|||
system.cpu.num_load_insts 94754511 # Number of load instructions
|
||||
system.cpu.num_store_insts 73520765 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1134731738 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1134670186 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1795.107538 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1795.138964 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1795.107538 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.876517 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.876517 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
|
||||
|
|
@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n
|
|||
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3673 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 186108000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 186108000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 186108000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 186108000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 186108000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 186108000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
|
||||
|
|
@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009
|
|||
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50669.207732 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 50669.207732 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 50669.207732 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 50669.207732 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673
|
|||
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 175089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 175089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 175089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47669.207732 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47669.207732 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3288.859436 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3288.859436 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802944 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802944 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
|
||||
|
|
@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n
|
|||
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 48094000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 48094000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 176797000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 176797000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 224891000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 224891000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 224891000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 224891000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50625.263158 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50625.263158 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55214.553404 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55214.553404 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54164.499037 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54164.499037 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45244000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45244000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167191000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167191000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212435000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 212435000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212435000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 212435000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47625.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47625.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52214.553404 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52214.553404 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3772.396394 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 371.526936 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2770.408528 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 630.460931 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.084546 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.115124 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.525920 # Number of seconds simulated
|
||||
sim_ticks 525920061000 # Number of ticks simulated
|
||||
final_tick 525920061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.525834 # Number of seconds simulated
|
||||
sim_ticks 525834342000 # Number of ticks simulated
|
||||
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 787177 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1006377 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1517904458 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 235608 # Number of bytes of host memory used
|
||||
host_seconds 346.48 # Real time elapsed on the host
|
||||
host_inst_rate 739511 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 945437 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1425757824 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241188 # Number of bytes of host memory used
|
||||
host_seconds 368.81 # Real time elapsed on the host
|
||||
sim_insts 272739283 # Number of instructions simulated
|
||||
sim_ops 348687122 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 166976 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 317493 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 513903 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 831396 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 317493 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 317493 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 317493 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 513903 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 831396 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 1051840122 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1051668684 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739283 # Number of instructions committed
|
||||
|
|
@ -89,18 +89,18 @@ system.cpu.num_mem_refs 177024356 # nu
|
|||
system.cpu.num_load_insts 94648757 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1051840122 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1765.965460 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1765.965460 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.862288 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.862288 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
|
||||
|
|
@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n
|
|||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 328087000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 328087000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 328087000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 328087000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 328087000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 328087000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses
|
||||
|
|
@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045
|
|||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21027.174261 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21027.174261 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21027.174261 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21027.174261 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603
|
|||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281278000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281278000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281278000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281278000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281278000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281278000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18027.174261 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18027.174261 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3078.361570 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3078.361570 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.751553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.751553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
||||
|
|
@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 4478 # n
|
|||
system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4478 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80120000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 80120000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 160192000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 160192000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 240312000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 240312000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 240312000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 240312000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49887.920299 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49887.920299 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55777.158774 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55777.158774 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53665.029031 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53665.029031 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4478
|
|||
system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75302000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75302000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151576000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151576000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226878000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 226878000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 226878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46887.920299 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46887.920299 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52777.158774 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52777.158774 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3487.655618 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 341.607182 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2408.352970 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 737.695465 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.073497 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.106435 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.813572 # Number of seconds simulated
|
||||
sim_ticks 2813572242000 # Number of ticks simulated
|
||||
final_tick 2813572242000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.811836 # Number of seconds simulated
|
||||
sim_ticks 2811836424000 # Number of ticks simulated
|
||||
final_tick 2811836424000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1893151 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1893151 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2651343461 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227888 # Number of bytes of host memory used
|
||||
host_seconds 1061.19 # Real time elapsed on the host
|
||||
host_inst_rate 1325085 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1325085 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1854626286 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228472 # Number of bytes of host memory used
|
||||
host_seconds 1516.12 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475279 # Nu
|
|||
system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 54069 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 33558000 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 33612069 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 54069 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 54069 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1521721 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1521721 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1521721 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 54069 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 33558000 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 35133790 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 54103 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 33578716 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 33632818 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 54103 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 54103 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1522660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1522660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1522660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 54103 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 33578716 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 35155479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 39 # Number of system calls
|
||||
system.cpu.numCycles 5627144484 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5623672848 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2008987605 # Number of instructions committed
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu
|
|||
system.cpu.num_load_insts 511488910 # Number of load instructions
|
||||
system.cpu.num_store_insts 210809477 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5627144484 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5623672848 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 9046 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1478.417406 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1478.427768 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1478.417406 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.721883 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.721883 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1478.427768 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.721889 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.721889 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
|
||||
|
|
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n
|
|||
system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10596 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 248319000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 248319000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 248319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 248319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 248319000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 248319000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 237582000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 237582000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 237582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 237582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 237582000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 237582000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses
|
||||
|
|
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005
|
|||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23435.164213 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23435.164213 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22421.857305 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22421.857305 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596
|
|||
system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216531000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 216531000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216531000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 216531000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216531000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 216531000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.192384 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.209846 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1063975000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.192384 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999803 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999803 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.209846 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999807 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999807 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
|
||||
|
|
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n
|
|||
system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1530144 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567803000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 79567803000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3816006000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3816006000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 83383809000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 83383809000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 83383809000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 83383809000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78109548000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78109548000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 81853590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 81853590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 81853590000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 81853590000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54494.092713 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54494.092713 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53566.024227 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 53566.024227 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53494.043698 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53494.043698 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144
|
|||
system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193227000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193227000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600150000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600150000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793377000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 78793377000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793377000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 78793377000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1479705 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 32703.875584 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 32704.499819 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 3255.326122 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 33.503711 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 29415.045751 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.099345 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 3254.482584 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 33.474832 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 29416.542403 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.099319 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.897676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.998043 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.897722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.998062 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.369932 # Number of seconds simulated
|
||||
sim_ticks 2369931974000 # Number of ticks simulated
|
||||
final_tick 2369931974000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.368273 # Number of seconds simulated
|
||||
sim_ticks 2368273403000 # Number of ticks simulated
|
||||
final_tick 2368273403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 844398 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1145486 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1448435887 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232760 # Number of bytes of host memory used
|
||||
host_seconds 1636.20 # Real time elapsed on the host
|
||||
host_inst_rate 821983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1115078 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1408999350 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241788 # Number of bytes of host memory used
|
||||
host_seconds 1680.82 # Real time elapsed on the host
|
||||
sim_insts 1381604339 # Number of instructions simulated
|
||||
sim_ops 1874244941 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475585 # Nu
|
|||
system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 60950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 39848165 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 39909115 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 60950 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 60950 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1785003 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1785003 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1785003 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 60950 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 39848165 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41694118 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 60993 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 39876072 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 39937065 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 60993 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 60993 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1786253 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1786253 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1786253 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 60993 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 39876072 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41723318 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1411 # Number of system calls
|
||||
system.cpu.numCycles 4739863948 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4736546806 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1381604339 # Number of instructions committed
|
||||
|
|
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 908382479 # nu
|
|||
system.cpu.num_load_insts 631387181 # Number of load instructions
|
||||
system.cpu.num_store_insts 276995298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4739863948 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4736546806 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 18364 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1392.322496 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1392.329214 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1392.322496 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.679845 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.679845 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1392.329214 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.679848 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.679848 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
|
||||
|
|
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 19803 # n
|
|||
system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 19803 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 372133000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 372133000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 372133000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 372133000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 372133000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 372133000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 352238000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 352238000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 352238000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 352238000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 352238000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 352238000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses
|
||||
|
|
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000014
|
|||
system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18791.748725 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18791.748725 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18791.748725 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18791.748725 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 17787.102964 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 17787.102964 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 19803
|
|||
system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312724000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 312724000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312724000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 312724000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312724000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 312724000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312632000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 312632000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312632000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 312632000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312632000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 312632000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15791.748725 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15791.748725 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1529557 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.950469 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.965929 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1004561000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.950469 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999744 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999744 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.965929 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999748 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999748 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
|
||||
|
|
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n
|
|||
system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650958000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 79650958000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794840000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3794840000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 83445798000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 83445798000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 83445798000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 83445798000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78190013000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78190013000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 81912059000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 81912059000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 81912059000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 81912059000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709
|
|||
system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.849009 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.849009 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.247595 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.247595 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54409.829342 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54409.829342 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53409.773267 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53409.773267 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653
|
|||
system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268339000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268339000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576500000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576500000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844839000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 78844839000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844839000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 78844839000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.849009 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.849009 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.247595 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.247595 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1478696 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 32689.689328 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 32690.092056 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 3194.581985 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 32.931287 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 29462.176056 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.097491 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 3194.112587 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 32.917167 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 29463.062302 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.097477 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.899114 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.997610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.899141 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.997622 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits
|
||||
|
|
@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 1477842 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1475585 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1477842 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117364000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117369000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73293584000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 73410948000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 73410953000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 117364000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 117369000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 76730420000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 76847784000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 117364000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 76847789000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 117369000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 76730420000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 76847784000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 76847789000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.951325 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.215330 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.003542 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.215330 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.003383 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.215330 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.003383 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1477842
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1475585 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1477842 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90285000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56379680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469965000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90285000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59023400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 59113680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 59113685000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90285000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59023400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 59113680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 59113685000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,39 +1,39 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.047911 # Number of seconds simulated
|
||||
sim_ticks 47910588500 # Number of ticks simulated
|
||||
final_tick 47910588500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.046793 # Number of seconds simulated
|
||||
sim_ticks 46793182500 # Number of ticks simulated
|
||||
final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 102205 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 102205 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55429613 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227308 # Number of bytes of host memory used
|
||||
host_seconds 864.35 # Real time elapsed on the host
|
||||
host_inst_rate 59681 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 59681 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31612654 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227600 # Number of bytes of host memory used
|
||||
host_seconds 1480.20 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10272960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10788288 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10272832 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10787712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 514880 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 514880 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 8052 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 160515 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 8045 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 160513 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 168558 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10756036 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 214419408 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 225175443 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10756036 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10756036 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 154921913 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 154921913 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 154921913 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10756036 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 214419408 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 380097356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 11003312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 219536938 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 230540250 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 11003312 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 11003312 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 158621397 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 158621397 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 158621397 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 11003312 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 219536938 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 389161648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -42,18 +42,18 @@ system.cpu.dtb.read_hits 20277225 # DT
|
|||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20367373 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14736863 # DTB write hits
|
||||
system.cpu.dtb.write_hits 14736820 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14744115 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35014088 # DTB hits
|
||||
system.cpu.dtb.write_accesses 14744072 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35014045 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35111488 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12475946 # ITB hits
|
||||
system.cpu.itb.fetch_misses 12952 # ITB misses
|
||||
system.cpu.dtb.data_accesses 35111445 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12477645 # ITB hits
|
||||
system.cpu.itb.fetch_misses 12958 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 12488898 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 12490603 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 95821178 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 93586366 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 12442338 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 5025331 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 16200752 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 5042995 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 18829185 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 12442057 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 5026145 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 16204746 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 5047870 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 31.128154 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 8471214 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10358543 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74332888 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 31.150565 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 8475762 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10353423 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74332851 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126652138 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 65238 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126652101 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 65265 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 292868 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14120784 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35064786 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4680831 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 234000 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4914831 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 8857404 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 35.686517 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44775821 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 292895 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14120054 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35064610 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4681911 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 233734 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4915645 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 8856618 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 35.692355 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44775927 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 78582835 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 78075293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 467389 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 25530263 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 70290915 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 73.356346 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 311800 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 23300937 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 70285429 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 75.102210 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 20276638 # Number of Load instructions committed
|
||||
system.cpu.comStores 14613377 # Number of Store instructions committed
|
||||
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
||||
|
|
@ -114,144 +114,144 @@ system.cpu.committedInsts 88340673 # Nu
|
|||
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 1.084678 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 1.059380 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 1.084678 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.921933 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 1.059380 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.943948 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.921933 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 42394050 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 53427128 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 55.757119 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 53163082 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42658096 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 44.518442 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 52694545 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43126633 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 45.007413 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 73699998 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22121180 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 23.085899 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 49718969 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46102209 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 48.112755 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 85335 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1885.674638 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 0.943948 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 40161098 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 53425268 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 57.086593 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 50931554 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42654812 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 45.578019 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 50461046 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43125320 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 46.080772 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 71466223 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22120143 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 23.636074 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 47482076 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46104290 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 49.263896 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 85221 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1887.407088 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12359392 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 87267 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.627328 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1885.674638 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12357256 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12357256 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12357256 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12357256 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12357256 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 118639 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 118639 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 118639 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 118639 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081863500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2081863500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2081863500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2081863500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2081863500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2081863500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12475895 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12475895 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12475895 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009509 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009509 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.884760 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 17547.884760 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 17547.884760 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 17547.884760 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1887.407088 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.921585 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.921585 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12359392 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12359392 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12359392 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12359392 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12359392 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12359392 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 118206 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 118206 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 118206 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 118206 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 118206 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 118206 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1871587000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1871587000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1871587000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1871587000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1871587000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1871587000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12477598 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12477598 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12477598 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12477598 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12477598 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12477598 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15833.265655 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15833.265655 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15833.265655 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 1025000 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 105 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 11204.761905 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 10904.255319 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31258 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 31258 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 31258 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 31258 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 31258 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 31258 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87381 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 87381 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 87381 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364888000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1364888000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364888000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1364888000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364888000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1364888000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.963150 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.963150 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30939 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30939 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30939 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30939 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30939 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87267 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 87267 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 87267 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 87267 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 87267 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 87267 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1309592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1309592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1309592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1309592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1309592500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1309592500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006994 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006994 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006994 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15006.732213 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15006.732213 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200251 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4073.238819 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4072.865489 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34126021 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4073.238819 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180530 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13945417 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13945417 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34125947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34125947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34125947 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34125947 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96108 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96108 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 667960 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 667960 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 764068 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 764068 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4228645000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 42089863000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 42089863000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 46318508000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 46318508000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 46318508000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 46318508000 # number of overall miss cycles
|
||||
system.cpu.dcache.avg_refs 167.000352 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 486992000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4072.865489 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.994352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.994352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180532 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180532 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13945489 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13945489 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34126021 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34126021 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34126021 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34126021 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96106 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96106 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 667888 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 667888 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 763994 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 763994 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 763994 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 763994 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3881207000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3881207000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 34562623000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 34562623000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 38443830000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 38443830000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 38443830000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 38443830000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015
|
|||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045709 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045709 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.886669 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.886669 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63012.550153 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 63012.550153 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60620.923792 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60620.923792 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045704 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045704 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.021897 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.021897 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40384.648201 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40384.648201 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51749.130094 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51749.130094 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 6946123500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 6260683500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 55940.882990 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 50440.975999 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 165805 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35341 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35341 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524380 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 524380 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 559721 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 559721 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 559721 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 559721 # number of overall MSHR hits
|
||||
system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 165811 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35339 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35339 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524308 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 524308 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 559647 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 559647 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 559647 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 559647 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
||||
|
|
@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347
|
|||
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7870166500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7870166500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9807011500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9807011500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9807011500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9807011500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1916080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1916080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7177771000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7177771000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9093851000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9093851000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9093851000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9093851000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -318,98 +318,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54813.807633 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54813.807633 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31531.587868 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31531.587868 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49991.440312 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49991.440312 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 136141 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 28773.050902 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 146499 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 167004 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.877219 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 136130 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 28810.787246 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 146402 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 166994 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.876690 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 25287.699561 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1723.905670 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1761.445671 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.771719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.052609 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.053755 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.878084 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79329 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 31110 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 110439 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 165805 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 165805 # number of Writeback hits
|
||||
system.cpu.l2cache.occ_blocks::writebacks 25348.854435 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1730.144008 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1731.788804 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.773586 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.052800 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.052850 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.879235 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79222 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 31112 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 110334 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 165811 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 165811 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12722 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12722 # number of ReadExReq hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_hits::cpu.data 43832 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 123161 # number of overall hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_misses::total 131048 # number of ReadExReq misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_misses::cpu.data 160515 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 168567 # number of overall misses
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6840080000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6840080000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 427362500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8381082500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8808445000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 427362500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8381082500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8808445000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 87381 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 147958 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 165805 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 165805 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 87381 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 79222 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 43834 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 123056 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 79222 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 43834 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 123056 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 8045 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 29466 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 37511 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 131047 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 131047 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 8045 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 160513 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 168558 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 8045 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 160513 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 168558 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 427506500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1540658500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1968165000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6905208500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6905208500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 427506500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8445867000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8873373500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 427506500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8445867000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8873373500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 87267 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 147845 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 165811 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 165811 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 87267 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
|
||||
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|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 87381 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 291614 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 87267 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 291728 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092148 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486439 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.253579 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 291614 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092188 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486414 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.253718 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911511 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911511 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092148 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.785502 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.577822 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092148 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.785502 # miss rate for overall accesses
|
||||
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|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53075.322901 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52295.873350 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52463.152003 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52195.226177 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52195.226177 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52254.860085 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52254.860085 # average overall miss latency
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092188 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.785492 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.578018 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092188 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.785492 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.578018 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53139.403356 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52285.973665 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52469.009091 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52692.610285 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52692.610285 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53139.403356 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52617.962408 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52642.849939 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53139.403356 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52617.962408 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52642.849939 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -420,50 +420,50 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 115975 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 115975 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8052 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29467 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 37519 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131048 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 131048 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8052 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 160515 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 168567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8052 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 160515 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 168567 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329154000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181438500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1510592500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5255819000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5255819000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329154000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6437257500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6766411500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329154000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6437257500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6766411500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486439 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253579 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8045 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29466 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 37511 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131047 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 131047 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8045 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 160513 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 168558 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8045 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 160513 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 168558 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329317000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181708500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1511025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5272374500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5272374500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329317000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6454083000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6783400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329317000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6454083000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6783400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486414 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253718 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.577822 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40106.060375 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40106.060375 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.578018 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.578018 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40934.369173 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40104.136971 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40282.197222 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40232.698955 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40232.698955 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.134581 # Number of seconds simulated
|
||||
sim_ticks 134581343000 # Number of ticks simulated
|
||||
final_tick 134581343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.133756 # Number of seconds simulated
|
||||
sim_ticks 133756135000 # Number of ticks simulated
|
||||
final_tick 133756135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1566292 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1566291 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2386143258 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226128 # Number of bytes of host memory used
|
||||
host_seconds 56.40 # Real time elapsed on the host
|
||||
host_inst_rate 1270571 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1270570 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1923763163 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227600 # Number of bytes of host memory used
|
||||
host_seconds 69.53 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160477 # Nu
|
|||
system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3606087 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 76314649 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 79920736 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3606087 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3606087 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 55142264 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 55142264 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 55142264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3606087 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 76314649 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 135063001 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 3628335 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 76785472 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 80413807 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3628335 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3628335 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 55482464 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 55482464 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 55482464 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3628335 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 76785472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 135896271 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 269162686 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 267512270 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 88340673 # Number of instructions committed
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu
|
|||
system.cpu.num_load_insts 20366786 # Number of load instructions
|
||||
system.cpu.num_store_insts 14620629 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 269162686 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 267512270 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1871.699205 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1871.674409 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1871.699205 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.913916 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.913916 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1871.674409 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.913904 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.913904 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
|
||||
|
|
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n
|
|||
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 76436 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1390813000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1390813000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1390813000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1390813000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1390813000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1390813000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312229000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1312229000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1312229000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1312229000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1312229000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1312229000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
|
||||
|
|
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864
|
|||
system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18195.784709 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18195.784709 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18195.784709 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18195.784709 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17167.682767 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 17167.682767 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 17167.682767 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 17167.682767 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436
|
|||
system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1161505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1161505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1161505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1161505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1161505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1161505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159357000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1159357000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159357000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1159357000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159357000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1159357000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15195.784709 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15195.784709 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15167.682767 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15167.682767 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.801621 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4078.879185 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 947396000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.801621 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995801 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995801 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.879185 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995820 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995820 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
|
||||
|
|
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n
|
|||
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2092728000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2092728000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513894000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7513894000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9606622000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9606622000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9606622000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9606622000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2026896000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2026896000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7369702000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7369702000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9396598000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9396598000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9396598000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9396598000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34439.127143 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34439.127143 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52333.184750 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52333.184750 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47012.009161 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47012.009161 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33355.758154 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 33355.758154 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51328.908329 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51328.908329 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45984.212896 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45984.212896 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344
|
|||
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910430000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910430000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7083160000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7083160000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8993590000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8993590000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8993590000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8993590000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905364000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905364000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082546000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082546000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8987910000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987910000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8987910000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31439.127143 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31439.127143 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49333.184750 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49333.184750 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31355.758154 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31355.758154 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.908329 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.908329 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 135625 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 29002.571879 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 29005.267541 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 25772.303239 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1646.708734 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1583.559905 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.786508 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.050254 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.048326 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.885088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 25782.627688 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1648.153103 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1574.486750 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.786823 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.050298 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.048050 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.885171 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 68853 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 31317 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 100170 # number of ReadReq hits
|
||||
|
|
@ -304,17 +304,17 @@ system.cpu.l2cache.demand_misses::total 168060 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 7583 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 160477 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 168060 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394316000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531348000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1925664000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813456000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6813456000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 394316000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8344804000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8739120000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 394316000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8344804000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8739120000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394391000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531428000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1925819000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813468000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6813468000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 394391000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8344896000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8739287000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 394391000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8344896000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8739287000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -339,17 +339,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.598547 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099207 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.785328 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.598547 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.890545 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.716561 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.185569 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.091583 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.091583 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.993693 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.993693 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -371,17 +371,17 @@ system.cpu.l2cache.demand_mshr_misses::total 168060
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 160477 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 168060 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1177960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6722400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419080000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6722400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303395000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1178040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481435000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241132000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241132000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303395000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419172000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6722567000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303395000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419172000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6722567000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.484630 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269909 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -393,17 +393,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.598547
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.598547 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.890545 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.716561 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40004.185569 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.091583 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.091583 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.133513 # Number of seconds simulated
|
||||
sim_ticks 133513136000 # Number of ticks simulated
|
||||
final_tick 133513136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.132746 # Number of seconds simulated
|
||||
sim_ticks 132746076000 # Number of ticks simulated
|
||||
final_tick 132746076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 903503 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1281191 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1714129830 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 235208 # Number of bytes of host memory used
|
||||
host_seconds 77.89 # Real time elapsed on the host
|
||||
host_inst_rate 594787 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 843423 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1121948184 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240564 # Number of bytes of host memory used
|
||||
host_seconds 118.32 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 99791654 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 125054 # Nu
|
|||
system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2050195 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 59945083 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 61995278 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2050195 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2050195 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 40470864 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 40470864 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 40470864 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2050195 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 59945083 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 102466142 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 2062042 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 60291470 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 62353512 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2062042 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2062042 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 40704721 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 40704721 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 40704721 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2062042 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 60291470 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 103058233 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 267026272 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 265492152 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70373628 # Number of instructions committed
|
||||
|
|
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu
|
|||
system.cpu.num_load_insts 27307108 # Number of load instructions
|
||||
system.cpu.num_store_insts 20555739 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 267026272 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 265492152 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1735.470121 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1736.430287 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1735.470121 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.847398 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.847398 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1736.430287 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.847866 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.847866 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits
|
||||
|
|
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n
|
|||
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 18908 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 445311000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 445311000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 445311000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 445311000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 445311000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 445311000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 425522000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 425522000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 425522000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 425522000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 425522000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 425522000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses
|
||||
|
|
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242
|
|||
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23551.459700 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23551.459700 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23551.459700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23551.459700 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22504.865665 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22504.865665 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22504.865665 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22504.865665 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908
|
|||
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 388587000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 388587000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 388587000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 388587000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 388587000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 388587000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387706000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 387706000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387706000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 387706000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387706000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 387706000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20551.459700 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20551.459700 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20504.865665 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20504.865665 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.664624 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4076.962537 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1111220000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.664624 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.962537 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
|
||||
|
|
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n
|
|||
system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 159998 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1699159000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1699159000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5797120000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5797120000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7496279000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7496279000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7496279000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7496279000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1642566000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1642566000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689754000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5689754000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7332320000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7332320000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7332320000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7332320000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405
|
|||
system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32080.183514 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32080.183514 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54162.493460 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54162.493460 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 46852.329404 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 46852.329404 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31011.705622 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 31011.705622 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53159.372898 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53159.372898 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45827.572845 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45827.572845 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998
|
|||
system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1540261000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1540261000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5476024000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5476024000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7016285000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7016285000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7016285000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7016285000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536634000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536634000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475690000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475690000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012324000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7012324000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012324000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7012324000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.183514 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29080.183514 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51162.493460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51162.493460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29011.705622 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29011.705622 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.372898 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.372898 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 96735 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 28857.116422 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 28875.776749 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 26427.849240 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 949.438432 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1479.828749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.806514 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.028975 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.045161 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.880649 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 26451.163706 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 950.000997 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1474.612046 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.807225 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.028992 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.045002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.881219 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits
|
||||
|
|
@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 129331 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 129331 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222404000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181076000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1403480000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321732000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5321732000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 222404000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6502808000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6725212000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 222404000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6502808000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6725212000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222488000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181138000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1403626000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321748000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5321748000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 222488000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6502886000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6725374000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 222488000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6502886000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6725374000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.722899 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52019.639935 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.729714 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.409411 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.156340 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.156340 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52001.252600 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52001.252600 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 129331
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908520000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093640000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093640000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5173240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171080000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5173240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171164000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908582000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079746000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093656000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093656000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171164000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002238000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5173402000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171164000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002238000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5173402000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40019.639935 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.729714 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.409411 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.156340 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.156340 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.204097 # Number of seconds simulated
|
||||
sim_ticks 204097178000 # Number of ticks simulated
|
||||
final_tick 204097178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.202343 # Number of seconds simulated
|
||||
sim_ticks 202342809000 # Number of ticks simulated
|
||||
final_tick 202342809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1441199 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1459859 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2188591939 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238748 # Number of bytes of host memory used
|
||||
host_seconds 93.26 # Real time elapsed on the host
|
||||
host_inst_rate 1232815 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1248778 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1856050290 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230736 # Number of bytes of host memory used
|
||||
host_seconds 109.02 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory
|
||||
|
|
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 123533 # Nu
|
|||
system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3261505 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 38736998 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 41998503 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3261505 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3261505 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 25974764 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 25974764 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 25974764 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3261505 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 38736998 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67973267 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 3289783 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 39072859 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 42362642 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3289783 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3289783 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 26199972 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 26199972 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 26199972 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3289783 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 39072859 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 68562614 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 408194356 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 404685618 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 134398962 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160248 # nu
|
|||
system.cpu.num_load_insts 37275867 # Number of load instructions
|
||||
system.cpu.num_store_insts 20884381 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 408194356 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 404685618 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tagsinuse 2004.409949 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 2004.814192 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 145330286000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 2004.409949 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.978716 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.978716 # Average percentage of cache occupancy
|
||||
system.cpu.icache.warmup_cycle 144074079000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 2004.814192 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.978913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n
|
|||
system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 187024 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 3060544000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 3060544000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 3060544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 3060544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 3060544000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 3060544000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2868177000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2868177000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2868177000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2868177000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2868177000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2868177000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390
|
|||
system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16364.445205 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16364.445205 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16364.445205 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16364.445205 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15335.876679 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15335.876679 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15335.876679 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15335.876679 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024
|
|||
system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2499472000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2499472000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2499472000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2499472000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2499472000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2499472000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494129000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2494129000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494129000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2494129000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494129000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2494129000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13364.445205 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13364.445205 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.876679 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.876679 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4087.413116 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4087.652500 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 812030000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4087.413116 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997904 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4087.652500 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
|
||||
|
|
@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n
|
|||
system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 150663 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1571682000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1571682000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5728295000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5728295000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 430000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 430000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7299977000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7299977000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7299977000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7299977000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1523847000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1523847000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5622992000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5622992000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7146839000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7146839000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7146839000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7146839000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34543.220730 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34543.220730 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54470.113347 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54470.113347 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28666.666667 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 28666.666667 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 48452.353929 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 48452.353929 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33491.878942 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 33491.878942 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53468.791602 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53468.791602 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47435.926538 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47435.926538 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663
|
|||
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1435185000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1435185000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412803000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412803000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 385000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 385000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6847988000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6847988000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6847988000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6847988000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432849000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432849000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845513000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6845513000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845513000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6845513000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31543.220730 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31543.220730 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51470.113347 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51470.113347 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25666.666667 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25666.666667 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31491.878942 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31491.878942 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 101560 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 29278.942435 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 29290.996090 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 24760.228137 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 3263.271559 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1255.442739 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.755622 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.099587 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.038313 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.893522 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 24775.786415 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 3266.546663 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1248.663012 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.756097 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.099687 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.038106 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.893890 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits
|
||||
|
|
@ -292,17 +292,17 @@ system.cpu.l2cache.demand_misses::total 133934 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 10401 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 123533 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 133934 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540852000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154296000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1695148000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540875000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154340000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1695215000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5269420000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5269420000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 540852000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6423716000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6964568000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 540852000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6423716000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6964568000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 540875000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6423760000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6964635000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 540875000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6423760000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6964635000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -327,17 +327,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.396604 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.055613 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.819848 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.396604 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.211326 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.982161 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.055278 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.500246 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.500246 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -359,17 +359,17 @@ system.cpu.l2cache.demand_mshr_misses::total 133934
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10401 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 123533 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 133934 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1303960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416063000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887964000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1304027000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4053400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4053400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5357360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5357360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416063000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941364000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5357427000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416063000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941364000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5357427000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.487879 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.140197 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.396604
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.396604 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.211326 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.982161 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.055278 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,59 +1,59 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.996063 # Number of seconds simulated
|
||||
sim_ticks 996062814500 # Number of ticks simulated
|
||||
final_tick 996062814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.983203 # Number of seconds simulated
|
||||
sim_ticks 983202553500 # Number of ticks simulated
|
||||
final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 142352 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 142352 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 77916645 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219096 # Number of bytes of host memory used
|
||||
host_seconds 12783.70 # Real time elapsed on the host
|
||||
host_inst_rate 94547 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 94547 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 51082649 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219392 # Number of bytes of host memory used
|
||||
host_seconds 19247.29 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 137579648 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 137634624 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 137579776 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 137634752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 67105024 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 67105024 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2149682 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2150541 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 138123466 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 138178659 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 67370273 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 67370273 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 67370273 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 138123466 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 205548932 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.data 2149684 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2150543 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 55915 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 139930247 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 139986162 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55915 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55915 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 68251540 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 68251540 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 68251540 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55915 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 139930247 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 208237702 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444620890 # DTB read hits
|
||||
system.cpu.dtb.read_hits 444615529 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449517968 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160920434 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 449512607 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160920414 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162621738 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605541324 # DTB hits
|
||||
system.cpu.dtb.write_accesses 162621718 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605535943 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 612139706 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 232151959 # ITB hits
|
||||
system.cpu.dtb.data_accesses 612134325 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 232170189 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 232151981 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 232170211 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 1992125630 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1966405108 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 253784019 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 139998376 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 232594122 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 138120343 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 328916467 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 253806684 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 140065896 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 232656738 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 138122512 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1669698372 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.BTBHitPct 59.367510 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 175157469 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 153758998 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1669786412 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3045900989 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3045989029 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 651085046 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617993265 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 121277812 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139625100 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 650997764 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617989099 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 121287494 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 12179944 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 133467438 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 81732764 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 62.020127 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139628962 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 1749884347 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 1746556255 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7972692 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 415154081 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1576971549 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.160246 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7516835 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 389335212 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1577069896 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 80.200661 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 444595663 # Number of Load instructions committed
|
||||
system.cpu.comStores 160728502 # Number of Store instructions committed
|
||||
system.cpu.comBranches 214632552 # Number of Branches instructions committed
|
||||
|
|
@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu
|
|||
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 1.094707 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 1.080573 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 1.094707 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.913487 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 1.080573 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.925435 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.913487 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 801360547 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1190765083 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 59.773594 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1059717687 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 932407943 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 46.804676 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1018191600 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 48.889187 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1582470698 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.563710 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 969332524 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1022793106 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.341797 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 0.925435 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 775560339 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1190844769 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.559483 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1034052370 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 932352738 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 47.414072 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 992429233 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 973975875 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.530784 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1556696076 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409709032 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.835434 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 943449824 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1022955284 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 52.021594 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 666.783134 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 666.559426 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 232169108 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270278.356228 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 666.783134 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 232150871 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 232150871 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 232150871 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 232150871 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 232150871 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1085 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1085 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1085 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1085 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1085 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60468000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 60468000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 60468000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 60468000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 60468000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 60468000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 232151956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 232151956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 232151956 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 232151956 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 232151956 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 232151956 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 666.559426 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325468 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325468 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 232169108 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 232169108 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 232169108 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 232169108 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 232169108 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 232169108 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1077 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1077 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1077 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1077 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1077 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1077 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58736500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 58736500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 58736500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 58736500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 58736500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 58736500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 232170185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 232170185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 232170185 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 232170185 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 232170185 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 232170185 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55730.875576 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55730.875576 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55730.875576 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55730.875576 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54537.140204 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54537.140204 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54537.140204 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 114500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 22900 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 218 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 218 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47379000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 47379000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47379000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 47379000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47379000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 47379000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47121000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 47121000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47121000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 47121000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47121000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 47121000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55155.995343 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55155.995343 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54855.646100 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54855.646100 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107311 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.354222 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 595073825 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111407 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.310860 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.354222 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437271433 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437271433 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 157802392 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 157802392 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 595073825 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 595073825 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 595073825 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 595073825 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7324230 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7324230 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2926110 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2926110 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 10250340 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 10250340 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 10250340 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 10250340 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 166497124500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 166497124500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 130098294500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 130098294500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 296595419000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 296595419000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 296595419000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 296595419000 # number of overall miss cycles
|
||||
system.cpu.dcache.replacements 9107371 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.143149 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 595063275 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111467 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.309272 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12675157000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.143149 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996617 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996617 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 157791841 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 157791841 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 595063275 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 595063275 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 595063275 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 595063275 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2936661 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2936661 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 10260890 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 10260890 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 10260890 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 10260890 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 153812326500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 153812326500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 102755788500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 102755788500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 256568115000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 256568115000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 256568115000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 256568115000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165
|
|||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018205 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.018205 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.372481 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.372481 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44461.176955 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 44461.176955 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28935.178638 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28935.178638 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 78626000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 8150818500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 14909 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5273.727279 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 39101.656496 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018271 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.018271 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.016951 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.016951 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016951 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016951 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21000.480255 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21000.480255 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34990.687893 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34990.687893 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3389635 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3389635 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036985 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1036985 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1138933 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1138933 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1138933 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1138933 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889125 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111407 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111407 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111407 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111407 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938792000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938792000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71755618500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 71755618500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212694410500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 212694410500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212694410500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 212694410500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3389692 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101949 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 101949 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047474 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1047474 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1149423 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1149423 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1149423 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1149423 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889187 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889187 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111467 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111467 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111467 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111467 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137359214000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137359214000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55152222500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 55152222500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192511436500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 192511436500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192511436500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 192511436500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -318,149 +318,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.440450 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.440450 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37983.520678 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37983.520678 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.815942 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.815942 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29193.628000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29193.628000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2133758 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30551.128505 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8448354 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 30529.573479 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8448408 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.905040 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 184403463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14423.846214 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 34.322158 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 16092.960133 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 5860989 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5860989 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3389635 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3389635 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 6961725 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 6961725 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 6961725 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 6961725 # number of overall hits
|
||||
system.cpu.l2cache.avg_refs 3.905065 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 182812071500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14439.033310 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 34.753993 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 16055.786176 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.440644 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001061 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.489984 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.931689 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3389692 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3389692 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1100796 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1100796 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 6961783 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 6961783 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 6961783 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 6961783 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1361711 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 788830 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 788830 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1360851 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1361710 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 788833 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 788833 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2149682 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 2150541 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2149684 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 2150543 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2149682 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2150541 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46160000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71427566000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 71473726000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42035467500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 42035467500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46160000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 113463033500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 113509193500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46160000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 113463033500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 113509193500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2149684 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2150543 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46256500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71433605500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 71479862000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42030855000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 42030855000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46256500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 113464460500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 113510717000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46256500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 113464460500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 113510717000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3389635 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3389635 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889566 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889566 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221838 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222697 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3389692 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3389692 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889629 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889629 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111407 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112266 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111467 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112326 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111407 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112266 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111467 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112326 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417466 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.417466 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417454 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.417454 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.235933 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.236005 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.235933 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.236005 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52487.387313 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52488.175538 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53288.373287 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53288.373287 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52781.692374 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52781.692374 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 3730000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53849.243306 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52491.863915 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52492.720183 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53282.323382 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53282.323382 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 540500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 142 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26267.605634 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12869.047619 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1048516 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1048516 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 1048517 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1048517 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360852 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1361711 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788830 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 788830 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360851 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1361710 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788833 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 788833 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2149682 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 2150541 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2149684 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 2150543 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2149682 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2150541 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35698000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54782223000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54817921000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32465310500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32465310500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35698000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87247533500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 87283231500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35698000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87247533500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 87283231500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2149684 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2150543 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35788000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54811327000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54847115000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32423383500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32423383500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35788000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87234710500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 87270498500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35788000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87234710500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 87270498500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417466 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417466 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417454 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417454 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.236005 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40255.827232 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40256.648437 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41156.282723 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41156.282723 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41662.398137 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40277.243431 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40278.117220 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41102.975535 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41102.975535 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.642008 # Number of seconds simulated
|
||||
sim_ticks 2642007987000 # Number of ticks simulated
|
||||
final_tick 2642007987000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.631385 # Number of seconds simulated
|
||||
sim_ticks 2631384990000 # Number of ticks simulated
|
||||
final_tick 2631384990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1913242 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1913242 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2777698581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217920 # Number of bytes of host memory used
|
||||
host_seconds 951.15 # Real time elapsed on the host
|
||||
host_inst_rate 1011793 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1011793 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1463043658 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219388 # Number of bytes of host memory used
|
||||
host_seconds 1798.57 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2149692 # Nu
|
|||
system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 19428 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52074138 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52093565 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19428 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19428 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 25399469 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 25399469 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 25399469 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19428 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52074138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 77493034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 19506 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52284363 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52303869 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19506 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19506 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 25502008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 25502008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 25502008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19506 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52284363 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 77805877 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 5284015974 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5262769980 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1819780127 # Number of instructions committed
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu
|
|||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5284015974 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5262769980 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 612.519467 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 612.470356 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 612.519467 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.299082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.299082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 612.470356 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.299058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.299058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
|
||||
|
|
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n
|
|||
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 802 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 45149000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 45149000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 45149000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 45149000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 45149000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 45149000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44120000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44120000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44120000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44120000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44120000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44120000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
|
||||
|
|
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56295.511222 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56295.511222 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56295.511222 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56295.511222 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55012.468828 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55012.468828 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802
|
|||
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42743000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42743000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42743000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42743000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42743000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42743000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42516000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42516000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42516000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42516000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42516000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42516000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53295.511222 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53295.511222 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4079.366966 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4079.313701 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 40989979000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4079.366966 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995939 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995939 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 40977019000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4079.313701 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995926 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995926 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
||||
|
|
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n
|
|||
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 158759423000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 158759423000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 59584620000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 59584620000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 218344043000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 218344043000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 218344043000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 218344043000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151059345000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151059345000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57691387000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57691387000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 208750732000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 208750732000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 208750732000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 208750732000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053
|
|||
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21981.490261 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21981.490261 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31537.600830 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31537.600830 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23962.951838 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23962.951838 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20915.353925 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22910.099439 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22910.099439 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734
|
|||
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137092181000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137092181000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53916660000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53916660000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191008841000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191008841000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191008841000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191008841000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136614517000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 136614517000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912747000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912747000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190527264000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 190527264000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 190527264000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18981.490261 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18981.490261 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28537.600830 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28537.600830 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18915.353925 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18915.353925 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.529714 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.529714 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2133721 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30166.534681 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 30159.988647 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 498438853000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14372.614424 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 37.649566 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15756.270691 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.438617 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001149 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.480843 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.920610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.warmup_cycle 496965874000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14375.657027 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 37.778500 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15746.553119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.438710 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001153 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.480547 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.920410 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits
|
||||
|
|
@ -301,17 +301,17 @@ system.cpu.l2cache.demand_misses::total 2150494 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2149692 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2150494 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41704000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70765916000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 70807620000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018068000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41018068000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 41704000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 111783984000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 111825688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 41704000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 111783984000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 111825688000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41714000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70776793000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 70818507000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018317000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41018317000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 41714000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 111795110000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 111836824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 41714000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 111795110000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 111836824000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -336,17 +336,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.235993 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52012.468828 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.992605 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52007.995241 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.315666 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.315666 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52005.178345 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52005.178345 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -368,17 +368,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2150494
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54435320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54467400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552360000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552360000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85987680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 86019760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85987680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 86019760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32090000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54446197000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54478287000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552609000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552609000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32090000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85998806000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 86030896000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32090000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85998806000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 86030896000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -390,17 +390,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.315666 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.315666 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.409361 # Number of seconds simulated
|
||||
sim_ticks 2409361491000 # Number of ticks simulated
|
||||
final_tick 2409361491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.399400 # Number of seconds simulated
|
||||
sim_ticks 2399400439000 # Number of ticks simulated
|
||||
final_tick 2399400439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1043020 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1164020 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1633141547 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227940 # Number of bytes of host memory used
|
||||
host_seconds 1475.29 # Real time elapsed on the host
|
||||
host_inst_rate 994913 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1110332 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1551375376 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233816 # Number of bytes of host memory used
|
||||
host_seconds 1546.63 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1717270334 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2153435 # Nu
|
|||
system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16363 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 57201811 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 57218174 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16363 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16363 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27899999 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27899999 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27899999 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16363 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 57201811 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 85118173 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 16431 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 57439283 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 57455713 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16431 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16431 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 28015825 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 28015825 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 28015825 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16431 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 57439283 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 85471539 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 4818722982 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4798800878 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1538759601 # Number of instructions committed
|
||||
|
|
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 660773815 # nu
|
|||
system.cpu.num_load_insts 485926769 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4818722982 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4798800878 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 7 # number of replacements
|
||||
system.cpu.icache.tagsinuse 515.026762 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 514.980115 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 515.026762 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.251478 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.251478 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 514.980115 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.251455 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.251455 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
|
||||
|
|
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n
|
|||
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 638 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34951000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34951000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34951000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34951000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34951000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34951000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34189000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34189000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34189000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34189000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34189000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34189000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
|
||||
|
|
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54782.131661 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54782.131661 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54782.131661 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54782.131661 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53587.774295 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53587.774295 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53587.774295 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53587.774295 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638
|
|||
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33037000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 33037000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33037000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 33037000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33037000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 33037000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32913000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32913000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32913000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32913000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32913000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32913000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51782.131661 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51782.131661 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51587.774295 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51587.774295 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4083.605959 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4083.564925 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 25924036000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4083.605959 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996974 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996974 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 25914432000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4083.564925 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996964 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996964 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
|
||||
|
|
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n
|
|||
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 158944725000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 158944725000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 59599499000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 59599499000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 218544224000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 218544224000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 218544224000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 218544224000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151247261000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151247261000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57698979000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57698979000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 208946240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 208946240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 208946240000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 208946240000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917
|
|||
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21995.960608 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21995.960608 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31548.331550 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31548.331550 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23975.706608 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23975.706608 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20930.727931 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20930.727931 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30542.312438 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30542.312438 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22922.746048 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22922.746048 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236
|
|||
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137266464000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137266464000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53932052000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53932052000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191198516000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191198516000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191198516000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191198516000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136795087000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 136795087000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53920681000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53920681000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190715768000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 190715768000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190715768000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 190715768000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18995.960608 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18995.960608 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28548.331550 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28548.331550 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.727931 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.727931 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28542.312438 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28542.312438 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2138446 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30629.012311 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 30623.782374 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 437178443000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14783.850246 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 15.711580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15829.450485 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.451167 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000479 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.483076 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.934723 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.warmup_cycle 435858689000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14787.769987 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 15.768959 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15820.243429 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.451287 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.482796 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.934564 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits
|
||||
|
|
@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 2154051 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70949164000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 70981196000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41029456000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41029456000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 111978620000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 112010652000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 111978620000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 112010652000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32055000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70952200000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 70984255000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41030322000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41030322000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32055000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 111982522000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 112014577000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32055000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 111982522000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 112014577000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.236297 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52037.337662 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.225142 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.240988 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.097553 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.097553 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52001.822148 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52001.822148 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2154051
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54576280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54600920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86137400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 86162040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86137400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 86162040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24663000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54579316000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54603979000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561986000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561986000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24663000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86141302000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 86165965000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24663000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86141302000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 86165965000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40037.337662 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.225142 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.240988 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.097553 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.097553 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.901049 # Number of seconds simulated
|
||||
sim_ticks 5901048883000 # Number of ticks simulated
|
||||
final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 5.891582 # Number of seconds simulated
|
||||
sim_ticks 5891581948000 # Number of ticks simulated
|
||||
final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 582820 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 908086 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1143336514 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274832 # Number of bytes of host memory used
|
||||
host_seconds 5161.25 # Real time elapsed on the host
|
||||
host_inst_rate 701685 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1374310212 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228764 # Number of bytes of host memory used
|
||||
host_seconds 4286.94 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862594 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
|
||||
|
|
@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 2172556 # Nu
|
|||
system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 11802097766 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 11783163896 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713082 # nu
|
|||
system.cpu.num_load_insts 1239184745 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528337 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11802097766 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 11783163896 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 10 # number of replacements
|
||||
system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n
|
|||
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 675 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37868000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 37868000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 37868000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56100.740741 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56100.740741 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675
|
|||
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 35843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 35843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 35843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n
|
|||
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 159195313000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 59631053000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 59631053000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57741123000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57741123000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 209712206000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 209712206000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 209712206000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432
|
|||
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 24013.400892 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 24013.400892 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21040.321064 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21040.321064 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23013.238152 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23013.238152 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677
|
|||
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961572000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961572000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191488335000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191488335000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525383000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525383000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961469000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486852000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486852000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191486852000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.321064 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.321064 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.655440 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.655440 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2158210 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.941512 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.warmup_cycle 1315499445000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14663.466685 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 21.611649 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 16164.776461 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.447493 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000660 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.493310 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.941463 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits
|
||||
|
|
@ -269,17 +269,17 @@ system.cpu.l2cache.demand_misses::total 2173231 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 71936280000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071732000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41071732000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 112972912000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 113008012000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 112972912000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 113008012000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35105000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901183000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 71936288000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071782000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41071782000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 35105000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 112972965000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 113008070000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 35105000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 112972965000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 113008070000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -304,17 +304,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.238467 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52007.407407 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.002170 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.005783 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.063304 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.063304 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.026688 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.026688 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -336,17 +336,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2173231
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593640000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593640000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 86929240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 86929240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27005000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308603000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335608000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593690000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593690000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27005000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902293000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 86929298000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27005000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902293000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 86929298000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -358,17 +358,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.042012 # Number of seconds simulated
|
||||
sim_ticks 42012413000 # Number of ticks simulated
|
||||
final_tick 42012413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.042001 # Number of seconds simulated
|
||||
sim_ticks 42001440000 # Number of ticks simulated
|
||||
final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 107145 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 107145 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48980163 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222716 # Number of bytes of host memory used
|
||||
host_seconds 857.74 # Real time elapsed on the host
|
||||
host_inst_rate 75192 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 75192 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34364250 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223172 # Number of bytes of host memory used
|
||||
host_seconds 1222.24 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4256266 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3266082 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7522348 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4256266 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4256266 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4256266 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3266082 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7522348 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -43,10 +43,10 @@ system.cpu.dtb.data_hits 26498122 # DT
|
|||
system.cpu.dtb.data_misses 33 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 26498155 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 10034924 # ITB hits
|
||||
system.cpu.itb.fetch_hits 10035828 # ITB hits
|
||||
system.cpu.itb.fetch_misses 49 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 10034973 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 10035877 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 84024827 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 84002881 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 13564834 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 9782438 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 4497092 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 7991226 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 3849853 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 121 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 48.176000 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 5999065 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7565769 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73744929 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136320401 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38529057 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26768938 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3519911 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 976323 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4496234 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5744468 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 43.905525 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57470438 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26769096 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 83640241 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 11659 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7743859 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 76280968 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.783844 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.809399 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -107,144 +107,144 @@ system.cpu.committedInsts 91903056 # Nu
|
|||
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.914277 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.914277 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.093761 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.093761 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27805541 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 56219286 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.907946 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34577681 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49447146 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 58.848257 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 34047365 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49977462 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.479399 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65995198 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18029629 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.457502 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 30080947 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53943880 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.199930 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 8128 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.257079 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 10023168 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 10013 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1001.015480 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 8127 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.257079 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728641 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728641 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 10023168 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 10023168 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 10023168 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 10023168 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 10023168 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 10023168 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11752 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11752 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11752 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11752 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11752 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11752 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 302404500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 302404500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 302404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 302404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 302404500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 302404500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 10034920 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 10034920 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 10034920 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 10034920 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 10034920 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 10034920 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 10024070 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11754 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25732.173247 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25732.173247 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25732.173247 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25732.173247 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 91000 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 15166.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10013 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 10013 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 10013 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10013 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234933000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 234933000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234933000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 234933000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234933000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 234933000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23462.798362 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23462.798362 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.425760 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26491190 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11916.864597 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.425760 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.351911 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.351911 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995640 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995640 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26491190 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26491190 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26491190 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26491190 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 558 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 558 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26491189 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 6111 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 6111 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 6111 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 6111 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29911500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 29911500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 335932500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 335932500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 365844000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 365844000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 365844000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 365844000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 6112 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -261,32 +261,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000231
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53604.838710 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 53604.838710 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60495.678012 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60495.678012 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59866.470299 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59866.470299 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 41291000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 49928.657799 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3888 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3888 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3888 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3888 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
|
|
@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24206500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24206500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96919000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 96919000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121125500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 121125500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121125500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 121125500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50961.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50961.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55445.652174 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55445.652174 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2189.621103 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7286 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.219988 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.844366 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1820.786741 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 350.989996 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066822 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 7219 # number of ReadReq hits
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 7272 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 7219 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 7218 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7298 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 7219 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 7297 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 7218 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7298 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7297 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
|
||||
|
|
@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149287500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23083500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 172371000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94426500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 94426500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 149287500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 117510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 266797500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 149287500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 117510000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 266797500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10013 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 10488 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 10013 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 10012 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 12236 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 10013 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 12235 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 10012 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 12236 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279037 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 12235 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279065 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.306636 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.306665 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279037 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.403563 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279037 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.403563 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53431.460272 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54700.236967 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53597.947761 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54835.365854 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54835.365854 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54029.465371 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54029.465371 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115196500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17936000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133132500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73235000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73235000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115196500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91171000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 206367500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115196500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91171000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 206367500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306636 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.403563 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403563 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41229.957051 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42502.369668 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41396.921642 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42529.036005 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42529.036005 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.118780 # Number of seconds simulated
|
||||
sim_ticks 118779533000 # Number of ticks simulated
|
||||
final_tick 118779533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.118729 # Number of seconds simulated
|
||||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1503058 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1503057 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1942616372 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222720 # Number of bytes of host memory used
|
||||
host_seconds 61.14 # Real time elapsed on the host
|
||||
host_inst_rate 979371 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 979371 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1265246648 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223148 # Number of bytes of host memory used
|
||||
host_seconds 93.84 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1412230 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1155216 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2567446 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1412230 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1412230 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1412230 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1155216 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2567446 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 237559066 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 237458632 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903056 # Number of instructions committed
|
||||
|
|
@ -79,18 +79,18 @@ system.cpu.num_mem_refs 26497334 # nu
|
|||
system.cpu.num_load_insts 19996208 # Number of load instructions
|
||||
system.cpu.num_store_insts 6501126 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 237559066 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 237458632 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1417.992791 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1417.992791 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.692379 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.692379 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
|
||||
|
|
@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n
|
|||
system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 8510 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 229226000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 229226000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 229226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 229226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 229226000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 229226000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
|
||||
|
|
@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093
|
|||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 26936.075206 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 26936.075206 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510
|
|||
system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203696000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 203696000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203696000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 203696000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203696000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 203696000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.982871 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.982871 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
|
||||
|
|
@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n
|
|||
system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2223 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24380000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 24380000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 121176000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 121176000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 121176000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 121176000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54510.121457 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54510.121457 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22955000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22955000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114507000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 114507000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114507000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 114507000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2073.981313 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.795350 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1704.943449 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.242515 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.052031 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.063293 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.232090 # Number of seconds simulated
|
||||
sim_ticks 232089948000 # Number of ticks simulated
|
||||
final_tick 232089948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.232072 # Number of seconds simulated
|
||||
sim_ticks 232072304000 # Number of ticks simulated
|
||||
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1108463 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1213886 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1497086914 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230968 # Number of bytes of host memory used
|
||||
host_seconds 155.03 # Real time elapsed on the host
|
||||
host_inst_rate 603492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 660888 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 815011792 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237088 # Number of bytes of host memory used
|
||||
host_seconds 284.75 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 188185920 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu
|
|||
system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 476781 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 475402 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 952183 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 476781 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 476781 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 476781 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 475402 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 952183 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 464179896 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 464144608 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 171842483 # Number of instructions committed
|
||||
|
|
@ -89,18 +89,18 @@ system.cpu.num_mem_refs 42494119 # nu
|
|||
system.cpu.num_load_insts 29849484 # Number of load instructions
|
||||
system.cpu.num_store_insts 12644635 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 464179896 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 464144608 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1147.971530 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1147.971530 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.560533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.560533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
|
||||
|
|
@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n
|
|||
system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3051 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115332000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 115332000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses
|
||||
|
|
@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
|||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 37801.376598 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 37801.376598 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1363.590777 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.590777 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.332908 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.332908 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
|
||||
|
|
@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 1789 # n
|
|||
system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1789 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 36195000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 36195000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 61264000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 61264000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 97459000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 97459000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 97459000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 97459000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52532.656023 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 52532.656023 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54476.802683 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54476.802683 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1789
|
|||
system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34128000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34128000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92092000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 92092000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92092000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 92092000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49532.656023 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49532.656023 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 1675.633213 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 3.038052 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1169.018140 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 503.577021 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.051136 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.270629 # Number of seconds simulated
|
||||
sim_ticks 270628667000 # Number of ticks simulated
|
||||
final_tick 270628667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.270563 # Number of seconds simulated
|
||||
sim_ticks 270563082000 # Number of ticks simulated
|
||||
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1532509 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1532510 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2143977461 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 235212 # Number of bytes of host memory used
|
||||
host_seconds 126.23 # Real time elapsed on the host
|
||||
host_inst_rate 662631 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 662631 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 926794797 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226156 # Number of bytes of host memory used
|
||||
host_seconds 291.93 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
|
||||
|
|
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 230208 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 850642 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 372703 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1223344 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 850642 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 850642 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 850642 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 401 # Number of system calls
|
||||
system.cpu.numCycles 541257334 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 541126164 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 193444518 # Number of instructions committed
|
||||
|
|
@ -47,18 +47,18 @@ system.cpu.num_mem_refs 76733958 # nu
|
|||
system.cpu.num_load_insts 57735091 # Number of load instructions
|
||||
system.cpu.num_store_insts 18998867 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 541257334 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 541126164 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1591.550018 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1591.579171 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1591.550018 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
|
||||
|
|
@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n
|
|||
system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12288 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 323106000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 323106000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 323106000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
|
||||
|
|
@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064
|
|||
system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 26294.433594 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 26294.433594 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1237.179149 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1237.179149 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
|
||||
|
|
@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n
|
|||
system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1575 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27888000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 27888000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60312000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 60312000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 56000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 56000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 88200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -249,18 +249,18 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2678.289604 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2275.240623 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 403.048526 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.081735 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.250981 # Number of seconds simulated
|
||||
sim_ticks 250980994000 # Number of ticks simulated
|
||||
final_tick 250980994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.250954 # Number of seconds simulated
|
||||
sim_ticks 250953955000 # Number of ticks simulated
|
||||
final_tick 250953955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 540200 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 905422 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1026566177 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 281300 # Number of bytes of host memory used
|
||||
host_seconds 244.49 # Real time elapsed on the host
|
||||
host_inst_rate 366685 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 614596 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 696753053 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236244 # Number of bytes of host memory used
|
||||
host_seconds 360.18 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221362961 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
|
||||
|
|
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 181760 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 724198 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 483224 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1207422 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 724198 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 724198 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 724198 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 483224 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207422 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 501961988 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 501907910 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 132071193 # Number of instructions committed
|
||||
|
|
@ -47,18 +47,18 @@ system.cpu.num_mem_refs 77165302 # nu
|
|||
system.cpu.num_load_insts 56649586 # Number of load instructions
|
||||
system.cpu.num_store_insts 20515716 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 501961988 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 501907910 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1455.271959 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1455.296654 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1455.271959 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.710582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.710582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1455.296654 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
|
||||
|
|
@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n
|
|||
system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4694 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 185042500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 185042500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 185042500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 185042500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 185042500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 185042500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses
|
||||
|
|
@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027
|
|||
system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39421.069450 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 39421.069450 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 39421.069450 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 39421.069450 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694
|
|||
system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170929000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 170929000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170929000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 170929000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170929000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 170929000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.358756 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.358756 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1363.439047 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1363.457581 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.439047 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.332871 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.332871 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.457581 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits
|
||||
|
|
@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 1905 # n
|
|||
system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1905 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 88243000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 88243000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 106263000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 106263000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 106263000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 106263000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.785805 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.785805 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55781.102362 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55781.102362 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -205,12 +205,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1905
|
|||
system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83509000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83509000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100547500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 100547500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100547500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 100547500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -221,26 +221,26 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.785805 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.785805 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2058.146468 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2058.178702 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 0.021788 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1829.948778 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 228.175901 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1829.978594 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 228.178364 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.062810 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
|
||||
|
|
@ -265,17 +265,17 @@ system.cpu.l2cache.demand_misses::total 4735 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -300,17 +300,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.905063 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52003.273495 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52003.273495 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000022 # Number of seconds simulated
|
||||
sim_ticks 21979500 # Number of ticks simulated
|
||||
final_tick 21979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 21628500 # Number of ticks simulated
|
||||
final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 39186 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39182 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 134757534 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222636 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 48865 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 48859 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 165354272 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 218640 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu
|
|||
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 876453059 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 489183102 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1365636161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 876453059 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 876453059 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 876453059 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 489183102 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1365636161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 43960 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 43258 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 1606 # Number of BP lookups
|
||||
|
|
@ -90,12 +90,12 @@ system.cpu.execution_unit.executions 4463 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 12066 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 536 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 36556 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7404 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 16.842584 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7403 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 17.113597 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1183 # Number of Load instructions committed
|
||||
system.cpu.comStores 865 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
||||
|
|
@ -107,34 +107,34 @@ system.cpu.committedInsts 6390 # Nu
|
|||
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 6.879499 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 6.879499 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.145359 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.145359 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 39048 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 11.173794 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 40082 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 8.821656 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 39789 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 9.488171 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 42620 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.048226 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 39501 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4459 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 10.143312 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 138.677707 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 557 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 138.677707 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits
|
||||
|
|
@ -149,12 +149,12 @@ system.cpu.icache.demand_misses::cpu.inst 351 # n
|
|||
system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 351 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19781500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19781500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19781500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19781500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19781500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19781500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
|
||||
|
|
@ -167,12 +167,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.386564
|
|||
system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56357.549858 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56357.549858 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -193,34 +193,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302
|
|||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16493500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16493500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16493500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16493500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16493500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16493500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 102.489186 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 102.489186 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025022 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025022 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits
|
||||
|
|
@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n
|
|||
system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 348 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5918000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5918000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15290000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 15290000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21208000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21208000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21208000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21208000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -261,20 +261,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922
|
|||
system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60942.528736 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60942.528736 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1689000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
|
||||
|
|
@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5509500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5509500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9606000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9606000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9606000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9606000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -309,23 +309,23 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 194.900917 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.748296 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.152621 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy
|
||||
|
|
@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16152000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 21542000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16152000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9397500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 25549500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16152000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9397500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 25549500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12487000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4239000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16726000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3129500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3129500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12487000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7368500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19855500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12487000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7368500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19855500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000034 # Number of seconds simulated
|
||||
sim_ticks 34409000 # Number of ticks simulated
|
||||
final_tick 34409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 32544000 # Number of ticks simulated
|
||||
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 55813 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 55804 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 300451871 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222640 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 68117 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 68101 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 346770993 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 218620 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 517074021 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 312476387 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 829550408 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 517074021 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 517074021 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 517074021 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 312476387 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 829550408 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 68818 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 65088 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -79,18 +79,18 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 68818 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 65088 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 128.208060 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 128.208060 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.062602 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.062602 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
|
||||
|
|
@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n
|
|||
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 279 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
|
||||
|
|
@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587
|
|||
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 103.892123 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 103.892123 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025364 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025364 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
|
||||
|
|
@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n
|
|||
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 168 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 184.769601 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 128.220906 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.548695 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003913 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001726 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005639 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000007 # Number of seconds simulated
|
||||
sim_ticks 7252000 # Number of ticks simulated
|
||||
final_tick 7252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 7079000 # Number of ticks simulated
|
||||
final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 57662 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 57638 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 175044086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217908 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 8209 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 8209 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24342914 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 218360 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
|
||||
|
|
@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 12032 # Nu
|
|||
system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1659128516 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 750137893 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2409266409 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1659128516 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1659128516 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1659128516 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 750137893 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2409266409 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 712 # DTB read hits
|
||||
system.cpu.dtb.read_misses 13 # DTB read misses
|
||||
system.cpu.dtb.read_misses 34 # DTB read misses
|
||||
system.cpu.dtb.read_acv 1 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 725 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 368 # DTB write hits
|
||||
system.cpu.dtb.write_misses 15 # DTB write misses
|
||||
system.cpu.dtb.read_accesses 746 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 367 # DTB write hits
|
||||
system.cpu.dtb.write_misses 20 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 383 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 1080 # DTB hits
|
||||
system.cpu.dtb.data_misses 28 # DTB misses
|
||||
system.cpu.dtb.write_accesses 387 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 1079 # DTB hits
|
||||
system.cpu.dtb.data_misses 54 # DTB misses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1108 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 1014 # ITB hits
|
||||
system.cpu.dtb.data_accesses 1133 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 1015 # ITB hits
|
||||
system.cpu.itb.fetch_misses 30 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 1044 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 1045 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -60,183 +60,183 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 14505 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 14159 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 1131 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 573 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 253 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 782 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 218 # Number of BTB hits
|
||||
system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 211 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 6900 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 429 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 1183 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 857 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 264 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 948 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 1014 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 172 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 7341 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.939926 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.361375 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 6158 83.89% 83.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 50 0.68% 84.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 129 1.76% 86.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 101 1.38% 87.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 139 1.89% 89.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 62 0.84% 90.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 66 0.90% 91.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 61 0.83% 92.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 575 7.83% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 7341 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.077973 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.475698 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5395 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 291 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 1141 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 13 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 501 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 6151 # Number of instructions handled by decode
|
||||
system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 1148 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 501 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 5491 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 66 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 174 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1058 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 51 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 5908 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 4280 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6676 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6664 # Number of integer rename lookups
|
||||
system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 2512 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 145 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 5051 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 2503 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1510 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 7341 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.548427 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.241979 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 5680 77.37% 77.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 617 8.40% 85.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 387 5.27% 91.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 273 3.72% 94.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 198 2.70% 97.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 114 1.55% 99.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 56 0.76% 99.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 10 0.14% 99.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 6 0.08% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7341 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 2 4.88% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 17 41.46% 46.34% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 22 53.66% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 2876 71.44% 71.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 761 18.90% 90.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 388 9.64% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 4026 # Type of FU issued
|
||||
system.cpu.iq.rate 0.277559 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 41 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010184 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 15500 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 7558 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3688 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.FU_type_0::total 4054 # Type of FU issued
|
||||
system.cpu.iq.rate 0.286320 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 43 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 4060 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
|
|
@ -247,57 +247,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 501 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 5407 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 150 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 3874 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 726 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 152 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 350 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 1109 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 649 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 383 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.267080 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3756 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3694 # cumulative count of insts written-back
|
||||
system.cpu.iew.exec_nop 342 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 1134 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 652 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 387 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.275019 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3708 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1740 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2202 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers 2258 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.254671 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.790191 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 2822 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.225423 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 5956 87.08% 87.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 217 3.17% 90.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 318 4.65% 94.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 115 1.68% 96.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 67 0.98% 97.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 47 0.69% 98.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 32 0.47% 98.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 21 0.31% 99.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -308,69 +308,69 @@ system.cpu.commit.branches 396 # Nu
|
|||
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 71 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 11924 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 11305 # The number of ROB writes
|
||||
system.cpu.timesIdled 172 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7164 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 11671 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 11260 # The number of ROB writes
|
||||
system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.076665 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.076665 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.164564 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.164564 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4677 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2861 # number of integer regfile writes
|
||||
system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4712 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2874 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 94.201337 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 769 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 767 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.090426 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 94.201337 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.045997 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.045997 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 769 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 769 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 769 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 769 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 769 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 769 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 245 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 245 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 245 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 245 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 245 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 245 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 9112500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 9112500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 9112500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 9112500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 9112500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 9112500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1014 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1014 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1014 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1014 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241617 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.241617 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.241617 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.241617 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.241617 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.241617 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37193.877551 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 37193.877551 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 37193.877551 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 37193.877551 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 767 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 248 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1015 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1015 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1015 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244335 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.244335 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.244335 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.244335 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.244335 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.244335 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36354.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -379,94 +379,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 60 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 60 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 60 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6932500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 6932500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6932500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 6932500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6932500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 6932500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185404 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.185404 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.185404 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36875 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36875 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6948500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 6948500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6948500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 6948500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6948500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 6948500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 45.851495 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 774 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 45.970482 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 773 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.094118 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 45.851495 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.011194 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.011194 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 774 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 773 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 773 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 773 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 773 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 199 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4328500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4328500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3561500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3561500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7890000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7890000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7890000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7890000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 679 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 679 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 202 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4078500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4078500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3119500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3119500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7198000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7198000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7198000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7198000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 681 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 681 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 973 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 973 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 973 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 973 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173785 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.173785 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.204522 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.204522 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.204522 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.204522 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36682.203390 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 36682.203390 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43969.135802 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43969.135802 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 39648.241206 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 39648.241206 # average overall miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -475,14 +475,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
|
||||
|
|
@ -491,42 +491,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2511500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2511500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 981000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3492500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 3492500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3492500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 3492500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089838 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089838 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.087359 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.087359 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41172.131148 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41172.131148 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40875 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40875 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 123.109780 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 94.284624 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 28.825156 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002877 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000880 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.003757 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
|
||||
|
|
@ -538,17 +538,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6740500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2447000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 9187500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 950000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 6740500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3397000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 10137500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 6740500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3397000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 10137500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -571,17 +571,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35853.723404 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40114.754098 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36897.590361 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39583.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39583.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 37133.699634 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 37133.699634 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -601,17 +601,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6136500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2258000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8394500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 876000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 876000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6136500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3134000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9270500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6136500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3134000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9270500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -623,17 +623,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.957447 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37016.393443 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33712.851406 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 17541000 # Number of ticks simulated
|
||||
final_tick 17541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16524000 # Number of ticks simulated
|
||||
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 207586 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 207300 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1409208031 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 216876 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 93431 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 93371 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 598358642 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217312 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu
|
|||
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 594720940 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 299184767 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 893905707 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 594720940 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 594720940 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 594720940 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 299184767 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 893905707 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 35082 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 33048 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -79,18 +79,18 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 35082 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 33048 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 80.027768 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 80.050296 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 80.027768 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.039076 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.039076 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
|
||||
|
|
@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n
|
|||
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 163 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
|
||||
|
|
@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032
|
|||
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 47.439715 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 47.439715 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.011582 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.011582 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
|
||||
|
|
@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n
|
|||
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 82 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656
|
|||
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 107.121835 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 80.139278 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.982557 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.003269 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.003270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 27316000 # Number of ticks simulated
|
||||
final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 25969000 # Number of ticks simulated
|
||||
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 78983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 98109 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 472376751 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225996 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 147661 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 183366 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 839095918 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231680 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 4565 # Number of instructions simulated
|
||||
sim_ops 5672 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu
|
|||
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 527163567 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 292868648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 820032216 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 527163567 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 527163567 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 527163567 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 292868648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 820032216 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 54632 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 51938 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4565 # Number of instructions committed
|
||||
|
|
@ -89,18 +89,18 @@ system.cpu.num_mem_refs 2138 # nu
|
|||
system.cpu.num_load_insts 1200 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 54632 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 51938 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 114.832264 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 114.832264 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.056070 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.056070 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits
|
||||
|
|
@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n
|
|||
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 241 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses
|
||||
|
|
@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334
|
|||
system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53211.618257 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53211.618257 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 83.122861 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 83.122861 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020294 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020294 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
|
||||
|
|
@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n
|
|||
system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 141 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.068480
|
|||
system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 51234.042553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 51234.042553 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 154.336658 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 106.089659 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 48.246999 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003238 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001472 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004710 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000021 # Number of seconds simulated
|
||||
sim_ticks 20518000 # Number of ticks simulated
|
||||
final_tick 20518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000020 # Number of seconds simulated
|
||||
sim_ticks 20184000 # Number of ticks simulated
|
||||
final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 56112 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56102 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 197957466 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223380 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_inst_rate 50290 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50282 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 174536927 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219492 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu
|
|||
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 988790330 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 430451311 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1419241641 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 988790330 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 988790330 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 988790330 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 430451311 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1419241641 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1005152596 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 437574316 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1442726912 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1005152596 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1005152596 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1005152596 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 437574316 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1442726912 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
|
|
@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 41037 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 40369 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 1146 # Number of BP lookups
|
||||
|
|
@ -59,13 +59,13 @@ system.cpu.branch_predictor.RASInCorrect 32 # Nu
|
|||
system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5095 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 5096 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 8491 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 8492 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 1321 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 1320 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 2235 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -76,12 +76,12 @@ system.cpu.execution_unit.executions 3144 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 9756 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 35650 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 5387 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 13.127178 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 34984 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 5385 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 13.339444 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1163 # Number of Load instructions committed
|
||||
system.cpu.comStores 925 # Number of Store instructions committed
|
||||
system.cpu.comBranches 915 # Number of Branches instructions committed
|
||||
|
|
@ -93,72 +93,72 @@ system.cpu.committedInsts 5814 # Nu
|
|||
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 7.058308 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 6.943412 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 7.058308 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.141677 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 6.943412 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.144021 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.141677 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 37412 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.144021 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 36744 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 8.833492 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 38215 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 8.979663 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 37547 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 6.876721 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 2785 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 6.786558 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 39795 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 6.990513 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 37585 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 6.896381 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 39127 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.026537 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 38135 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 7.071667 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.utilization 3.076618 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 37465 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 7.193639 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.tagsinuse 147.247157 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 411 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 147.108411 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 410 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 147.247157 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.071898 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.071898 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 411 # number of overall hits
|
||||
system.cpu.icache.occ_blocks::cpu.inst 147.108411 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.071830 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.071830 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 410 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 344 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19614000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19614000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19614000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19614000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19614000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19614000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 755 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 755 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 755 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 755 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 755 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 755 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.455629 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.455629 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.455629 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.455629 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.455629 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.455629 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57017.441860 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 57017.441860 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 57017.441860 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 57017.441860 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19298000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19298000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19298000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19298000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19298000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19298000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.456233 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.456233 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56098.837209 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56098.837209 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56098.837209 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -179,34 +179,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319
|
|||
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17429500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17429500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17429500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17429500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17429500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17429500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.422517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.422517 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.422517 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54637.931034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54637.931034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17456000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17456000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17456000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17456000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17456000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17456000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54721.003135 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54721.003135 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 89.284631 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 89.235833 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 89.284631 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021798 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021798 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 89.235833 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021786 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021786 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits
|
||||
|
|
@ -223,14 +223,14 @@ system.cpu.dcache.demand_misses::cpu.data 254 # n
|
|||
system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 254 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5537500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5537500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10150000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10150000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15687500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 15687500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15687500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 15687500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5402500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5402500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9244000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9244000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14646500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14646500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14646500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14646500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -247,14 +247,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.121648
|
|||
system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60851.648352 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60851.648352 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62269.938650 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62269.938650 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61761.811024 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61761.811024 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59368.131868 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59368.131868 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56711.656442 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56711.656442 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -279,14 +279,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5138500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5138500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2913500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2913500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8052000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8052000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8052000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8052000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2905000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2905000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8016000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8016000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8016000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8016000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -295,26 +295,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59063.218391 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59063.218391 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57127.450980 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58347.826087 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58347.826087 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58747.126437 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58747.126437 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56960.784314 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56960.784314 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 204.307813 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 204.139180 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 148.858961 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 55.448851 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006235 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 148.719836 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 55.419344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004539 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006230 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17061000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5022000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 22083000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2843500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2843500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 17061000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7865500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24926500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 17061000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7865500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24926500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17110500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5017500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 22128000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2851000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2851000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 17110500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7868500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24979000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 17110500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7868500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24979000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53820.189274 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57724.137931 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54660.891089 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55754.901961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55754.901961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54783.516484 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54783.516484 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53976.340694 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57672.413793 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54772.277228 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55901.960784 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55901.960784 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54898.901099 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54898.901099 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -395,17 +395,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13201000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3966500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17167500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2221000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2221000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13201000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19388500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13201000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19388500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13248500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2227500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2227500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13248500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6190000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19438500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13248500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6190000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19438500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -417,17 +417,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.533123 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45591.954023 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42493.811881 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43549.019608 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43549.019608 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41793.375394 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45545.977011 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42601.485149 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43676.470588 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43676.470588 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
sim_ticks 12925500 # Number of ticks simulated
|
||||
final_tick 12925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 12603500 # Number of ticks simulated
|
||||
final_tick 12603500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52967 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52957 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 132735366 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224404 # Number of bytes of host memory used
|
||||
host_inst_rate 49943 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 49935 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 122043566 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220512 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
sim_insts 5156 # Number of instructions simulated
|
||||
sim_ops 5156 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21696 # Nu
|
|||
system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 480 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1678542416 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 698154810 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2376697226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1678542416 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1678542416 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1678542416 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 698154810 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2376697226 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1721426588 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 715991590 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2437418177 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1721426588 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1721426588 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1721426588 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 715991590 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2437418177 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
|
|
@ -46,101 +46,101 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 25852 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 25208 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 2052 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 1365 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2076 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 1377 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 1625 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 468 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1640 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 471 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 254 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.usedRAS 262 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 8806 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 12660 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2052 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 722 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 3113 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1287 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 809 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 12782 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2076 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 733 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 3147 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1298 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 705 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 1908 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13710 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.923414 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.233238 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 1923 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13341 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.958099 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.266693 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10597 77.29% 77.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1289 9.40% 86.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 106 0.77% 87.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 138 1.01% 88.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 293 2.14% 90.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 99 0.72% 91.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 151 1.10% 92.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 124 0.90% 93.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 913 6.66% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10194 76.41% 76.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1306 9.79% 86.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 106 0.79% 86.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 141 1.06% 88.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 294 2.20% 90.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 100 0.75% 91.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 154 1.15% 92.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 127 0.95% 93.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 919 6.89% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13710 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.079375 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.489711 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8966 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 966 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2934 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 143 # Number of times decode resolved a branch
|
||||
system.cpu.fetch.rateDist::total 13341 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.082355 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.507061 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8622 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 899 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2969 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 11758 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 11860 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 9155 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 277 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2801 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 144 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11265 # Number of instructions processed by rename
|
||||
system.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 13414 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13410 # Number of integer rename lookups
|
||||
system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 8807 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 544 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2833 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11360 # Number of instructions processed by rename
|
||||
system.cpu.rename.LSQFullEvents 96 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 13521 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13517 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 3481 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1172 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.rename.UndoneMaps 3542 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 277 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2388 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 8819 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8008 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 3225 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1836 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13710 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.584099 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.244040 # Number of insts issued each cycle
|
||||
system.cpu.iq.iqInstsAdded 8869 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8060 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 3246 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1840 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13341 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.604153 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.265993 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10210 74.47% 74.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1436 10.47% 84.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 842 6.14% 91.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 525 3.83% 94.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 351 2.56% 97.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 220 1.60% 99.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 85 0.62% 99.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 29 0.21% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9853 73.86% 73.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1401 10.50% 84.36% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 847 6.35% 90.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 533 4.00% 94.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 353 2.65% 97.35% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 227 1.70% 99.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 84 0.63% 99.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 29 0.22% 99.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13710 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13341 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available
|
||||
|
|
@ -176,113 +176,113 @@ system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4734 59.12% 59.12% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2177 27.19% 86.41% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1088 13.59% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4766 59.13% 59.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.19% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2195 27.23% 86.48% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1090 13.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8008 # Type of FU issued
|
||||
system.cpu.iq.rate 0.309763 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 8060 # Type of FU issued
|
||||
system.cpu.iq.rate 0.319740 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.018981 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 29921 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 12064 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7226 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.018859 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 29653 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 12136 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7261 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 8158 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 8210 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1209 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1225 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 247 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 10240 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 94 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1172 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 170 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 10299 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2388 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 7665 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2061 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 343 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 7692 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2065 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 368 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 1409 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3123 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1292 # Number of branches executed
|
||||
system.cpu.iew.exec_nop 1417 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3127 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1305 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1062 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.296495 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7314 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7228 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2794 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 3985 # num instructions consuming a value
|
||||
system.cpu.iew.exec_rate 0.305141 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7351 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7263 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2827 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 4035 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.279592 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.701129 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.288123 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.700620 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4420 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4478 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12917 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.450027 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.233846 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12537 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.463668 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.253066 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10496 81.26% 81.26% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1026 7.94% 89.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 636 4.92% 94.12% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 301 2.33% 96.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 148 1.15% 97.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 90 0.70% 98.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 76 0.59% 98.89% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 38 0.29% 99.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 106 0.82% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10143 80.90% 80.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 988 7.88% 88.79% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 634 5.06% 93.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 313 2.50% 96.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 148 1.18% 97.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 91 0.73% 98.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 75 0.60% 98.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 39 0.31% 99.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 106 0.85% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12917 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12537 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 5813 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -295,67 +295,67 @@ system.cpu.commit.int_insts 5111 # Nu
|
|||
system.cpu.commit.function_calls 87 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23031 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21266 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 22709 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21393 # The number of ROB writes
|
||||
system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 12142 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 11867 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5156 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
|
||||
system.cpu.cpi 5.013964 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.013964 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.199443 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.199443 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 10440 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5074 # number of integer regfile writes
|
||||
system.cpu.cpi 4.889061 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 4.889061 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.204538 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.204538 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 10482 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5097 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 150 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 151 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 17 # number of replacements
|
||||
system.cpu.icache.tagsinuse 161.949608 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1474 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 161.691170 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1486 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.309942 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.345029 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 161.949608 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.079077 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.079077 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1474 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 434 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15909000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15909000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15909000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15909000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15909000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1908 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1908 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1908 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1908 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227463 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.227463 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.227463 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.227463 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.227463 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.227463 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36656.682028 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36656.682028 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36656.682028 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36656.682028 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 161.691170 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.078951 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.078951 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1486 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1486 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1486 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1486 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1486 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1486 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 437 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15633000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15633000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15633000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15633000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15633000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15633000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1923 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1923 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1923 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1923 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1923 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227249 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.227249 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.227249 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.227249 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.227249 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.227249 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35773.455378 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 35773.455378 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 35773.455378 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 35773.455378 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -364,94 +364,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.179245 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.179245 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36308.479532 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36308.479532 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36308.479532 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36308.479532 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36308.479532 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36308.479532 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12431000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12431000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12431000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12431000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12431000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12431000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.177847 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.177847 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36347.953216 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36347.953216 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 90.879080 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 90.751581 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 17.070922 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 17.085106 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 90.879080 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.022187 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.022187 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1830 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1830 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2407 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 348 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 348 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 496 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5699000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5699000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13075000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 13075000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 18774000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 18774000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 18774000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 18774000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1978 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1978 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.occ_blocks::cpu.data 90.751581 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.022156 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.022156 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1833 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1833 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 576 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 576 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2409 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2409 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2409 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2409 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 498 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5432500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5432500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11660000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 11660000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 17092500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 17092500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 17092500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 17092500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1982 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2903 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2903 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2903 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2903 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074823 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.074823 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.170858 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.170858 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.170858 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.170858 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38506.756757 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 38506.756757 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37571.839080 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 37571.839080 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37850.806452 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37850.806452 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37850.806452 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37850.806452 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075177 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.075177 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377297 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.377297 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.171311 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.171311 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.171311 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.171311 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36459.731544 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 36459.731544 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33409.742120 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33409.742120 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 34322.289157 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 34322.289157 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -460,14 +460,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 298 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 298 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 357 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 357 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 357 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 357 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
|
||||
|
|
@ -476,42 +476,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
|
|||
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5913000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5913000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045501 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045501 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3834500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3834500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2072000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2072000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5906500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5906500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5906500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5906500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045409 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045409 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.048570 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.048570 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.048504 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.048504 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42605.555556 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42605.555556 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40627.450980 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40627.450980 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 221.306774 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 220.970580 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 164.083724 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 57.223050 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005007 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001746 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006754 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 163.825301 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 57.145280 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001744 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
|
|
@ -529,17 +529,17 @@ system.cpu.l2cache.demand_misses::total 480 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 480 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12053000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3723500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 15776500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12053000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 5721500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17774500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12053000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 5721500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17774500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3740000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 15824000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2020500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2020500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 5760500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17844500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12084000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 5760500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17844500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -562,17 +562,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993789 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35554.572271 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41372.222222 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36775.058275 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 37030.208333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 37030.208333 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35646.017699 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41555.555556 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36885.780886 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39617.647059 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39617.647059 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 37176.041667 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 37176.041667 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -592,17 +592,17 @@ system.cpu.l2cache.demand_mshr_misses::total 480
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10969500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3448000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14417500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10969500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5287500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10969500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5287500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16257000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11000500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14466000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1861500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1861500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11000500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5327000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16327500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11000500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5327000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16327500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -614,17 +614,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32358.407080 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38311.111111 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33607.226107 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32449.852507 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38505.555556 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33720.279720 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 33399000 # Number of ticks simulated
|
||||
final_tick 33399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000032 # Number of seconds simulated
|
||||
sim_ticks 31633000 # Number of ticks simulated
|
||||
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 212162 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 212025 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1217250605 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223376 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_inst_rate 284864 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 284628 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1547353604 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219460 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu
|
|||
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 439 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 576783736 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 264439055 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 841222791 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 576783736 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 576783736 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 576783736 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 264439055 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 841222791 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
|
|
@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 66798 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 63266 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5814 # Number of instructions committed
|
||||
|
|
@ -65,18 +65,18 @@ system.cpu.num_mem_refs 2089 # nu
|
|||
system.cpu.num_load_insts 1163 # Number of load instructions
|
||||
system.cpu.num_store_insts 926 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 66798 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 63266 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.tagsinuse 133.141027 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 132.545353 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5513 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 133.141027 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.065010 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.065010 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
|
||||
|
|
@ -89,12 +89,12 @@ system.cpu.icache.demand_misses::cpu.inst 303 # n
|
|||
system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 303 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses
|
||||
|
|
@ -107,12 +107,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052098
|
|||
system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 87.742269 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 87.742269 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021421 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021421 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
|
||||
|
|
@ -171,14 +171,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n
|
|||
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 138 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -195,14 +195,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066092
|
|||
system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 188.881290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 134.495649 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 54.385641 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004104 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001660 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18878500 # Number of ticks simulated
|
||||
final_tick 18878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 18570500 # Number of ticks simulated
|
||||
final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 36734 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36730 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 130153209 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229488 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 42410 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42404 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 147804999 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221464 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
|
||||
|
|
@ -19,35 +19,35 @@ system.physmem.bytes_inst_read::total 18496 # Nu
|
|||
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 979738856 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 454273380 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1434012236 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 979738856 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 979738856 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 979738856 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 454273380 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1434012236 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 995988261 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 461807706 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1457795967 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 995988261 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 995988261 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 995988261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 461807706 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1457795967 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 37758 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 37142 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 1630 # Number of BP lookups
|
||||
system.cpu.branch_predictor.lookups 1632 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBLookups 1167 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 37.596567 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.BTBHitPct 37.532134 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 1125 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5623 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9611 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 1685 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 1682 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 1483 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 3966 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 10163 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 9963 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 500 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 31528 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6230 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 16.499815 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 471 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 30915 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6227 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 16.765387 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 715 # Number of Load instructions committed
|
||||
system.cpu.comStores 673 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1115 # Number of Branches instructions committed
|
||||
|
|
@ -75,72 +75,72 @@ system.cpu.committedInsts 5327 # Nu
|
|||
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 7.088042 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 6.972405 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 7.088042 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.141083 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 6.972405 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.143423 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.141083 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 33195 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4563 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 12.084856 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34564 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 8.459134 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 34714 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.143423 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32576 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4566 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 12.293361 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33943 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3199 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 8.612891 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 34098 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 8.061868 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 36776 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 8.195574 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 36160 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.600773 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 34592 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 3166 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 8.384978 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.utilization 2.643907 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 33973 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 8.532120 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 136.498326 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 829 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 136.328432 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 828 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2.845361 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 136.498326 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.066650 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.066650 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 829 # number of overall hits
|
||||
system.cpu.icache.occ_blocks::cpu.inst 136.328432 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.066567 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.066567 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 828 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 828 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 828 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 828 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 828 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 828 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19654500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19654500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19654500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19654500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19654500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19654500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1179 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1179 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1179 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1179 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.296862 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.296862 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.296862 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.296862 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.296862 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.296862 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56155.714286 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56155.714286 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56155.714286 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56155.714286 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19327000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19327000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19327000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19327000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19327000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19327000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297114 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.297114 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.297114 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.297114 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.297114 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.297114 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55220 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55220 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55220 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55220 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -161,34 +161,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
|
|||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15991000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15991000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15991000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15991000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15991000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15991000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.246819 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.246819 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.246819 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54951.890034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54951.890034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54951.890034 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54951.890034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54951.890034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54951.890034 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15994000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15994000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15994000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54962.199313 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54962.199313 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 82.673308 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 82.607202 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 82.673308 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020184 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020184 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 82.607202 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020168 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020168 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits
|
||||
|
|
@ -205,14 +205,14 @@ system.cpu.dcache.demand_misses::cpu.data 343 # n
|
|||
system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 343 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3569000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3569000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 17304500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 17304500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20873500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20873500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20873500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20873500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3485500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3485500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15720000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 15720000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 19205500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 19205500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 19205500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 19205500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -229,20 +229,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.247118
|
|||
system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58508.196721 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58508.196721 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61363.475177 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61363.475177 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60855.685131 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60855.685131 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60855.685131 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60855.685131 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57139.344262 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 57139.344262 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55744.680851 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55744.680851 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 2306500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 51255.555556 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
||||
|
|
@ -261,14 +261,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
|||
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3064500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3064500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3073000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3073000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4525000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4525000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7589500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7589500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7589500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7589500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7598000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7598000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7598000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7598000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -277,26 +277,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56907.407407 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56907.407407 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55864.197531 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55864.197531 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56218.518519 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56218.518519 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56218.518519 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56218.518519 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 162.089529 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 161.896728 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 136.006338 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.083191 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004151 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000796 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004947 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 135.841585 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.055143 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004146 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000795 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004941 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
|
|
@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15654000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2985000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18639000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4433500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4433500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15654000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7418500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23072500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15654000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7418500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23072500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15675500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3006500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18682000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4441500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4441500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15675500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7448000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23123500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15675500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7448000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23123500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54166.089965 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56320.754717 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54734.567901 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54734.567901 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54544.917258 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54544.917258 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54240.484429 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56726.415094 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54625.730994 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54833.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54833.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 54665.484634 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 54665.484634 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14482000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3454500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3454500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5797500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17936500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5797500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17936500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2365000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14525000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5827500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17987500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5827500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17987500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42003.460208 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44207.547170 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42345.029240 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42076.124567 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44622.641509 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42470.760234 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42746.913580 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42746.913580 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000030 # Number of seconds simulated
|
||||
sim_ticks 29527000 # Number of ticks simulated
|
||||
final_tick 29527000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 27800000 # Number of ticks simulated
|
||||
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 69145 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69130 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 383102769 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229488 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 251441 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 251244 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1310200039 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220428 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
|
||||
|
|
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 16320 # Nu
|
|||
system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 552714465 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 290446032 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 843160497 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 552714465 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 552714465 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 552714465 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 290446032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 843160497 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 59054 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 55600 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5327 # Number of instructions committed
|
||||
|
|
@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1401 # nu
|
|||
system.cpu.num_load_insts 723 # Number of load instructions
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 59054 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 55600 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 117.127109 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 117.043638 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 117.127109 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.057191 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.057191 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
|
||||
|
|
@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n
|
|||
system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 257 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
|
||||
|
|
@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850
|
|||
system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55673.151751 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55673.151751 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 82.138993 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 82.138993 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020053 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020053 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
|
||||
|
|
@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n
|
|||
system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 135 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2982000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2982000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4536000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4536000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7518000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55688.888889 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55688.888889 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 142.279716 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 116.596239 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 25.683477 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004342 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000030 # Number of seconds simulated
|
||||
sim_ticks 29676000 # Number of ticks simulated
|
||||
final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28356000 # Number of ticks simulated
|
||||
final_tick 28356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72347 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 131001 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 398795084 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269536 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 134366 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 243261 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 707485860 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226568 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9746 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
|
||||
|
|
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 14528 # Nu
|
|||
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 489553848 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 288987734 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 778541582 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 489553848 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 489553848 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 489553848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 288987734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 778541582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 512343067 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 302440401 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 814783467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 512343067 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 512343067 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 512343067 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 302440401 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 814783467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 59352 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 56712 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
|
|
@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1986 # nu
|
|||
system.cpu.num_load_insts 1052 # Number of load instructions
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 59352 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 56712 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 105.746399 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 105.556077 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 105.746399 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.051634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.051634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 105.556077 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.051541 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.051541 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
|
||||
|
|
@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n
|
|||
system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 228 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
|
||||
|
|
@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033212
|
|||
system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 80.866493 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 80.800961 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 80.866493 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.019743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.019743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 80.800961 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.019727 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.019727 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
|
||||
|
|
@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n
|
|||
system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 134 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067472
|
|||
system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 134.266314 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 134.040949 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 105.749768 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 28.516546 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003227 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000870 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004097 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 105.564188 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 28.476761 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 25614500 # Number of ticks simulated
|
||||
final_tick 25614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000025 # Number of seconds simulated
|
||||
sim_ticks 25317500 # Number of ticks simulated
|
||||
final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72825 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 72819 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 123010334 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229416 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_inst_rate 47783 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 47781 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 79779918 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220364 # Number of bytes of host memory used
|
||||
host_seconds 0.32 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
|
||||
|
|
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 19072 # Nu
|
|||
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 744578266 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 344804700 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1089382967 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 744578266 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 744578266 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 744578266 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 344804700 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1089382967 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 51230 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 50636 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 5020 # Number of BP lookups
|
||||
|
|
@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 11058 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 22262 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 524 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 33874 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 17356 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 33.878587 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 17355 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 34.274034 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 2225 # Number of Load instructions committed
|
||||
system.cpu.comStores 1448 # Number of Store instructions committed
|
||||
system.cpu.comBranches 3358 # Number of Branches instructions committed
|
||||
|
|
@ -75,36 +75,36 @@ system.cpu.committedInsts 15162 # Nu
|
|||
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 3.378842 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 3.378842 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.295959 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.295959 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 38098 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 37504 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 25.633418 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 42042 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 17.934804 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 42414 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 17.208667 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 48346 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 47752 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 5.629514 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 41913 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 9317 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 18.186609 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 41318 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 164.536889 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 164.702089 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2586 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 164.536889 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.080340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.080340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 164.702089 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.080421 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits
|
||||
|
|
@ -117,12 +117,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n
|
|||
system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 369 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20585000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 20585000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 20585000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 20585000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 20585000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 20585000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20235000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 20235000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 20235000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 20235000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 20235000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses
|
||||
|
|
@ -135,12 +135,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.124873
|
|||
system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55785.907859 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55785.907859 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55785.907859 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55785.907859 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54837.398374 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54837.398374 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -161,34 +161,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301
|
|||
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16326500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16326500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16326500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16326500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16326500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16326500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16329000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16329000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16329000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16329000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16329000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16329000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54240.863787 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54240.863787 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.169435 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54249.169435 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 96.547387 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 96.602865 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 96.547387 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.023571 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.023571 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 96.602865 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.023585 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.023585 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits
|
||||
|
|
@ -207,14 +207,14 @@ system.cpu.dcache.demand_misses::cpu.data 359 # n
|
|||
system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 359 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3488000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3488000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18458000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 18458000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21946000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21946000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21946000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21946000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3411000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3411000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16758500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 16758500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20169500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20169500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20169500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20169500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -233,20 +233,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097900
|
|||
system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61322.259136 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61130.919220 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61130.919220 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58810.344828 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58810.344828 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55676.079734 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55676.079734 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 2258500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 50188.888889 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
||||
|
|
@ -265,14 +265,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2987500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2987500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4730000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4730000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7717500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7717500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7717500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7717500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2994500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2994500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7727500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7727500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7727500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7727500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -281,26 +281,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55647.058824 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55682.352941 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 195.042677 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 163.928542 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.114135 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005952 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15989500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2926500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18916000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4635000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4635000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15989500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7561500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23551000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15989500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7561500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23551000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16005500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18945500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4645500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4645500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16005500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7585500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23591000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16005500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7585500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23591000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53476.588629 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53738.636364 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 53892.448513 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 53892.448513 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53530.100334 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53822.443182 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54652.941176 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54652.941176 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 53983.981693 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 53983.981693 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12379500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2285000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14664500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3604000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3604000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12379500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5889000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12379500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5889000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18268500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12396000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2298500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14694500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3614500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12396000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18309000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12396000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18309000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -403,17 +403,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41403.010033 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43113.207547 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41660.511364 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42400 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42400 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41745.738636 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42523.529412 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42523.529412 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000043 # Number of seconds simulated
|
||||
sim_ticks 43106000 # Number of ticks simulated
|
||||
final_tick 43106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000041 # Number of seconds simulated
|
||||
sim_ticks 41368000 # Number of ticks simulated
|
||||
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 377775 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 377609 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1073121241 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229408 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 652409 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 651936 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1777530278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220352 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
|
||||
|
|
@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 412749965 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 204890270 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 617640236 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 412749965 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 412749965 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 412749965 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 204890270 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 617640236 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 86212 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 82736 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 15162 # Number of instructions committed
|
||||
|
|
@ -47,18 +47,18 @@ system.cpu.num_mem_refs 3683 # nu
|
|||
system.cpu.num_load_insts 2231 # Number of load instructions
|
||||
system.cpu.num_store_insts 1452 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 86212 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 82736 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 152.957781 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 152.957781 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.074686 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.074686 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
|
||||
|
|
@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n
|
|||
system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 280 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
|
||||
|
|
@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411
|
|||
system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 97.669722 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 97.669722 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.023845 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.023845 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
|
||||
|
|
@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n
|
|||
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 138 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2968000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2968000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4760000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4760000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633
|
|||
system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 183.688794 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 152.283537 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.405257 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000958 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005606 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
|
|||
Loading…
Reference in a new issue