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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
Andreas Hansson 54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width 
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
2012-10-15 08:09:54 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.624688 # Number of seconds simulated
sim_ticks 2624688029000 # Number of ticks simulated
final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 388710 # Simulator instruction rate (inst/s)
host_op_rate 494628 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16947208284 # Simulator tick rate (ticks/s)
host_mem_usage 385844 # Number of bytes of host memory used
host_seconds 154.87 # Real time elapsed on the host
sim_insts 60201138 # Number of instructions simulated
sim_ops 76605123 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory
system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14996726 # DTB read hits
system.cpu.dtb.read_misses 7357 # DTB read misses
system.cpu.dtb.write_hits 11231612 # DTB write hits
system.cpu.dtb.write_misses 2211 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 15004083 # DTB read accesses
system.cpu.dtb.write_accesses 11233823 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26228338 # DTB hits
system.cpu.dtb.misses 9568 # DTB misses
system.cpu.dtb.accesses 26237906 # DTB accesses
system.cpu.itb.inst_hits 61495107 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 61499578 # ITB inst accesses
system.cpu.itb.hits 61495107 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61499578 # DTB accesses
system.cpu.numCycles 5249376058 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60201138 # Number of instructions committed
system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2139913 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls
system.cpu.num_int_insts 68872510 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read
system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27395681 # number of memory refs
system.cpu.num_load_insts 15660705 # Number of load instructions
system.cpu.num_store_insts 11734976 # Number of store instructions
system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles
system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles
system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.871278 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
system.cpu.icache.replacements 855878 # number of replacements
system.cpu.icache.tagsinuse 510.920723 # Cycle average of tags in use
system.cpu.icache.total_refs 60638717 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 856390 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.807362 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.920723 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 60638717 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60638717 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60638717 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60638717 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60638717 # number of overall hits
system.cpu.icache.overall_hits::total 60638717 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 856390 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 856390 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 856390 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses
system.cpu.icache.overall_misses::total 856390 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856390 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 856390 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 856390 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852692500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9852692500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852692500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9852692500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852692500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9852692500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.913065 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.913065 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 627202 # number of replacements
system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use
system.cpu.dcache.total_refs 23656924 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627714 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.687425 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13196261 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13196261 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23170044 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23170044 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23170044 # number of overall hits
system.cpu.dcache.overall_hits::total 23170044 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368703 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368703 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 619213 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619213 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619213 # number of overall misses
system.cpu.dcache.overall_misses::total 619213 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201080500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency
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system.cpu.dcache.writebacks::total 595968 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
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system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 619213 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency
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system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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