54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
613 lines
70 KiB
Plaintext
613 lines
70 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000020 # Number of seconds simulated
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sim_ticks 19879000 # Number of ticks simulated
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final_tick 19879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 39676 # Simulator instruction rate (inst/s)
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host_op_rate 39674 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 54630622 # Simulator tick rate (ticks/s)
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host_mem_usage 221392 # Number of bytes of host memory used
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host_seconds 0.36 # Real time elapsed on the host
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sim_insts 14436 # Number of instructions simulated
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sim_ops 14436 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30784 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 481 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1078525077 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 470043765 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1548568841 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1078525077 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1078525077 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1078525077 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 470043765 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1548568841 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 39759 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 6854 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 4554 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1112 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 4710 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 2490 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 477 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 12088 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 31936 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 6854 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 2967 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 9404 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 3148 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 7222 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 741 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 5545 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 31399 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.017102 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.199996 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 21995 70.05% 70.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4682 14.91% 84.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 472 1.50% 86.46% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 410 1.31% 87.77% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 687 2.19% 89.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 719 2.29% 92.25% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 235 0.75% 93.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 265 0.84% 93.84% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1934 6.16% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 31399 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.172389 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.803240 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 12738 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 7939 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 8587 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 195 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1940 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 29749 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 1940 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 13426 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 7130 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 8156 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 488 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 27133 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 140 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 24210 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 50486 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 50486 # Number of integer rename lookups
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system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 10391 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 723 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 2887 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 3597 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 2432 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 22935 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 673 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 21597 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 91 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 8291 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 5610 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 198 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 31399 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.687824 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.304127 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 22002 70.07% 70.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 3599 11.46% 81.53% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 2373 7.56% 89.09% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 1680 5.35% 94.44% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 925 2.95% 97.39% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 497 1.58% 98.97% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 251 0.80% 99.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 55 0.18% 99.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 31399 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 47 27.33% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 27 15.70% 43.02% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 98 56.98% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 15947 73.84% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 3395 15.72% 89.56% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 2255 10.44% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 21597 # Type of FU issued
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system.cpu.iq.rate 0.543198 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 172 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.007964 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 74856 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 31925 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 19878 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 21769 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 1372 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 984 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewSquashCycles 1940 # Number of cycles IEW is squashing
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system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking
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system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
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system.cpu.iew.iewDispatchedInsts 24765 # Number of instructions dispatched to IQ
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system.cpu.iew.iewDispSquashedInsts 456 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispLoadInsts 3597 # Number of dispatched load instructions
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system.cpu.iew.iewDispStoreInsts 2432 # Number of dispatched store instructions
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system.cpu.iew.iewDispNonSpecInsts 673 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
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system.cpu.iew.predictedTakenIncorrect 268 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 979 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 1247 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewExecutedInsts 20456 # Number of executed instructions
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system.cpu.iew.iewExecLoadInsts 3252 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 1141 # Number of squashed instructions skipped in execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.iew.exec_nop 1157 # number of nop insts executed
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system.cpu.iew.exec_refs 5386 # number of memory reference insts executed
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system.cpu.iew.exec_branches 4298 # Number of branches executed
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system.cpu.iew.exec_stores 2134 # Number of stores executed
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system.cpu.iew.exec_rate 0.514500 # Inst execution rate
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system.cpu.iew.wb_sent 20129 # cumulative count of insts sent to commit
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system.cpu.iew.wb_count 19878 # cumulative count of insts written-back
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system.cpu.iew.wb_producers 9203 # num instructions producing a value
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system.cpu.iew.wb_consumers 11321 # num instructions consuming a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_rate 0.499962 # insts written-back per cycle
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system.cpu.iew.wb_fanout 0.812914 # average fanout of values written-back
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitSquashedInsts 9531 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1112 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 29476 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.514385 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.202047 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 22110 75.01% 75.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 4076 13.83% 88.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1418 4.81% 93.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 772 2.62% 96.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 337 1.14% 97.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 264 0.90% 98.31% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 327 1.11% 99.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 72 0.24% 99.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 100 0.34% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 29476 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 15162 # Number of instructions committed
|
|
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 3673 # Number of memory references committed
|
|
system.cpu.commit.loads 2225 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 3358 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 187 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 100 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 53246 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 51332 # The number of ROB writes
|
|
system.cpu.timesIdled 190 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 8360 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 14436 # Number of Instructions Simulated
|
|
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
|
|
system.cpu.cpi 2.754156 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.754156 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.363088 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.363088 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 32578 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 18091 # number of integer regfile writes
|
|
system.cpu.misc_regfile_reads 7032 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 199.192019 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 5061 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 15.017804 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 199.192019 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.097262 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.097262 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 5061 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 5061 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 5061 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 5061 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 5061 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 5061 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 484 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 484 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 484 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 484 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 484 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 484 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16465500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 16465500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 16465500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 16465500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 16465500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 16465500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5545 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 5545 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 5545 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 5545 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 5545 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 5545 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087286 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.087286 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.087286 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.087286 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.087286 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.087286 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34019.628099 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 34019.628099 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 34019.628099 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 34019.628099 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12143500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12143500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12143500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060775 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.060775 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.060775 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36034.124629 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36034.124629 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 103.051665 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 4061 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 27.815068 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 103.051665 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.025159 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.025159 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3022 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 3022 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 4055 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 4055 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 4055 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 4055 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 530 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4244000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4244000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15546000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 15546000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 19790000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 19790000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 19790000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 19790000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3143 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3143 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 4585 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 4585 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 4585 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 4585 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038498 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.038498 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.115594 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.115594 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.115594 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.115594 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35074.380165 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 35074.380165 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38009.779951 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38009.779951 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 37339.622642 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 37339.622642 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 384 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 384 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 384 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 384 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2501000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2501000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3322000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3322000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5823000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5823000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5823000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5823000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020045 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020045 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.031843 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.031843 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39698.412698 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39698.412698 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40024.096386 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40024.096386 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 234.574534 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 198.449350 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 36.125184 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.006056 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001102 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.007159 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 481 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2437500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 14242000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3238000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3238000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 11804500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 5675500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 17480000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 11804500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 5675500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 17480000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 400 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.995000 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995859 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995859 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35237.313433 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38690.476190 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35783.919598 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39012.048193 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39012.048193 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 36340.956341 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 36340.956341 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10738000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2244000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12982000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2981500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2981500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10738000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5225500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 15963500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10738000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5225500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 15963500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995000 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995859 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995859 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32053.731343 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35619.047619 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32618.090452 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35921.686747 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35921.686747 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|