54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
640 lines
72 KiB
Plaintext
640 lines
72 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000007 # Number of seconds simulated
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sim_ticks 7079000 # Number of ticks simulated
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final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 8209 # Simulator instruction rate (inst/s)
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host_op_rate 8209 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 24342914 # Simulator tick rate (ticks/s)
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host_mem_usage 218360 # Number of bytes of host memory used
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host_seconds 0.29 # Real time elapsed on the host
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sim_insts 2387 # Number of instructions simulated
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sim_ops 2387 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
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system.physmem.bytes_read::total 17472 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 712 # DTB read hits
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system.cpu.dtb.read_misses 34 # DTB read misses
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system.cpu.dtb.read_acv 1 # DTB read access violations
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system.cpu.dtb.read_accesses 746 # DTB read accesses
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system.cpu.dtb.write_hits 367 # DTB write hits
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system.cpu.dtb.write_misses 20 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 387 # DTB write accesses
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system.cpu.dtb.data_hits 1079 # DTB hits
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system.cpu.dtb.data_misses 54 # DTB misses
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system.cpu.dtb.data_acv 1 # DTB access violations
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system.cpu.dtb.data_accesses 1133 # DTB accesses
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system.cpu.itb.fetch_hits 1015 # ITB hits
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system.cpu.itb.fetch_misses 30 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 1045 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numCycles 14159 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 1131 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 1148 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 1058 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 4054 # Type of FU issued
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system.cpu.iq.rate 0.286320 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 43 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 342 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 1134 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 652 # Number of branches executed
|
|
system.cpu.iew.exec_stores 387 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.275019 # Inst execution rate
|
|
system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 3708 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1740 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2258 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
|
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 709 # Number of memory references committed
|
|
system.cpu.commit.loads 415 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 396 # Number of branches committed
|
|
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 71 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 11671 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 11260 # The number of ROB writes
|
|
system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
|
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
|
system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 4712 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2874 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 767 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 767 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 248 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1015 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1015 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1015 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244335 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.244335 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.244335 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.244335 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.244335 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.244335 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36354.838710 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 60 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 60 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 60 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6948500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 6948500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6948500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 6948500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6948500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 6948500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185222 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 45.970482 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 773 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 9.094118 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 773 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 773 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 773 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 773 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 202 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4078500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4078500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3119500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 3119500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 7198000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 7198000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 7198000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 7198000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 681 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 681 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|