54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
428 lines
48 KiB
Plaintext
428 lines
48 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.717833 # Number of seconds simulated
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sim_ticks 717832876000 # Number of ticks simulated
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final_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1074460 # Simulator instruction rate (inst/s)
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host_op_rate 1210735 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1527332222 # Simulator tick rate (ticks/s)
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host_mem_usage 237040 # Number of bytes of host memory used
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host_seconds 469.99 # Real time elapsed on the host
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sim_insts 504986853 # Number of instructions simulated
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sim_ops 569034839 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9842240 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6574720 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 548 # Number of system calls
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system.cpu.numCycles 1435665752 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 504986853 # Number of instructions committed
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system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 19311615 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
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system.cpu.num_int_insts 470727695 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read
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system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 182890034 # number of memory refs
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system.cpu.num_load_insts 126029555 # Number of load instructions
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system.cpu.num_store_insts 56860479 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1435665752 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 9788 # number of replacements
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system.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use
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system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits
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system.cpu.icache.overall_hits::total 516599855 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
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system.cpu.icache.overall_misses::total 11521 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 1134822 # number of replacements
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system.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use
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system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits
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system.cpu.dcache.overall_hits::total 176840704 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
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system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1061444 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10613061000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10613061000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257505000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257505000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870566000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 18870566000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870566000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 18870566000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13560.279202 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13560.279202 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.310784 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.310784 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 122482 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 26931.505779 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 343812481000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 23220.335885 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 246.652044 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 3464.517849 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.708628 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.007527 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.105729 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.821884 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1061444 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1061444 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 252959 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 252959 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 8734 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 987920 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 996654 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 8734 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 987920 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 996654 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2787 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 47697 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 50484 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 103301 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 103301 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2787 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 150998 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 153785 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 153785 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144931000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480793000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2625724000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371655000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5371655000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 144931000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7852448000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 7997379000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 144931000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7852448000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 7997379000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1061444 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1061444 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.241906 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.063568 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.289960 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.289960 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.241906 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.132580 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.133675 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.511661 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52011.510158 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.013390 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.029041 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.029041 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52003.634945 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52003.634945 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 102730 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 102730 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2787 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 47697 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 50484 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103301 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 103301 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2787 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 150998 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 153785 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111487000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1908429000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019916000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132043000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132043000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111487000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6040472000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6151959000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111487000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6040472000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6151959000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.289960 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.289960 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.511661 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40011.510158 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.013390 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.029041 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.029041 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|