stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
This commit is contained in:
Andreas Hansson
parent
ac515d7a9b
commit
5a15909bac
89 changed files with 43891 additions and 43912 deletions
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@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
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system.cpu.num_busy_cycles 294271952 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 2 # number of replacements
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system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use
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system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy
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system.cpu.icache.tags.replacements 2 # number of replacements
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system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
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@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.replacements 0 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits
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@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 942702 # number of replacements
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system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
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system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
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system.cpu.dcache.tags.replacements 942702 # number of replacements
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system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks.
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system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
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@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
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system.cpu.num_busy_cycles 722977060 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 25 # number of replacements
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system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use
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system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy
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system.cpu.icache.tags.replacements 25 # number of replacements
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system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
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@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.replacements 0 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
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@ -279,15 +279,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 935475 # number of replacements
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system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use
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system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy
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system.cpu.dcache.tags.replacements 935475 # number of replacements
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system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
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system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
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@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu
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system.cpu.num_busy_cycles 731978130 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 24 # number of replacements
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system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use
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system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
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system.cpu.icache.tags.replacements 24 # number of replacements
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system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
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@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 318 # number of replacements
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system.cpu.l2cache.tagsinuse 20041.899765 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.replacements 318 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
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@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 2062733 # number of replacements
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system.cpu.dcache.tagsinuse 4076.488619 # Cycle average of tags in use
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system.cpu.dcache.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 1434732024 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tagsinuse 982.663229 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
|
||||
|
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 109895 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 27243.192324 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1668833 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 141072 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 11.829654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.831396 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 109895 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits
|
||||
|
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 3295745698 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
|
||||
|
|
@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 348459 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 29286.402664 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.893750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 348459 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits
|
||||
|
|
@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4086.415783 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743930 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.139913 # Number of seconds simulated
|
||||
sim_ticks 139912878500 # Number of ticks simulated
|
||||
final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.139916 # Number of seconds simulated
|
||||
sim_ticks 139916242500 # Number of ticks simulated
|
||||
final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 81894 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 81894 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 28740964 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231128 # Number of bytes of host memory used
|
||||
host_seconds 4868.07 # Real time elapsed on the host
|
||||
host_inst_rate 84616 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29697100 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231112 # Number of bytes of host memory used
|
||||
host_seconds 4711.44 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7328 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 139912806500 # Total gap between requests
|
||||
system.physmem.totGap 139916169000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -219,14 +219,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% #
|
|||
system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 37727500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 39772250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 36640000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 98463750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5148.40 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13436.65 # Average bank access latency per request
|
||||
system.physmem.totBankLat 98628750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5427.44 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13459.16 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 23585.05 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 23886.60 # Average memory access latency
|
||||
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -239,8 +239,8 @@ system.physmem.readRowHits 6626 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 19092904.82 # Average gap between requests
|
||||
system.membus.throughput 3352029 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 19093363.67 # Average gap between requests
|
||||
system.membus.throughput 3351948 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
|
||||
|
|
@ -251,39 +251,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992
|
|||
system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 468992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 53489761 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 53489675 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 94754611 # DTB read hits
|
||||
system.cpu.dtb.read_hits 94754653 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94754632 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521122 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 94754674 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521120 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73521157 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275733 # DTB hits
|
||||
system.cpu.dtb.write_accesses 73521155 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275773 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168275789 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611325 # ITB hits
|
||||
system.cpu.dtb.data_accesses 168275829 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611327 # ITB hits
|
||||
system.cpu.itb.fetch_misses 44520 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 48655845 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 48655847 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -297,18 +297,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 279825758 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 279832486 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631956 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828437 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484572 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -319,12 +319,12 @@ system.cpu.execution_unit.executions 205475782 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7883 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13519017 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306741 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.168773 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.166455 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -336,112 +336,112 @@ system.cpu.committedInsts 398664595 # Nu
|
|||
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.424689 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78078009 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747749 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.097633 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107174029 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.699727 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102610556 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215202 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.330554 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 181081179 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744579 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.287880 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90357849 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467909 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1830.982662 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 48606794 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12453.700743 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1830.982662 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.894035 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.894035 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606794 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606794 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606794 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606794 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606794 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606794 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4531 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 268165000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 268165000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 268165000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 268165000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 268165000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 268165000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611325 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611325 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611325 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611325 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611325 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611325 # number of overall (read+write) accesses
|
||||
system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606795 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4532 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59184.506731 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 59184.506731 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 326 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 108.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 110 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 628 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 628 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 629 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 629 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 629 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 629 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234852500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 234852500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234852500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 234852500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234852500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 234852500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 236384250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 236384250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60172.303356 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60172.303356 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
|
|
@ -457,23 +457,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.554458 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2908.829780 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.591520 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119231 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
|
||||
|
|
@ -498,17 +498,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 225463500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58932500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 284396000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 213301500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 213301500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 225463500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 272234000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 497697500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 225463500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 272234000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 497697500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 226995250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59463500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 286458750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214640250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 214640250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 226995250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 274103750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 501099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 226995250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 274103750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 501099000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -533,17 +533,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67122.208991 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71520.024272 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67988.524982 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67822.416534 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67822.416534 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67917.235262 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67917.235262 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67578.222685 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72164.441748 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68481.651924 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68248.092210 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68248.092210 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -563,17 +563,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183879500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 48740750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 232620250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174684500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174684500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183879500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 223425250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 407304750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183879500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 223425250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 407304750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 224736750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -585,51 +585,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54742.334028 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59151.395631 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55610.865408 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55543.561208 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55543.561208 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54994.417982 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3284.992544 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168254254 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40523.664258 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3284.992544 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802000 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802000 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501073 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501073 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254254 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254254 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254254 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254254 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254256 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19656 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19656 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20964 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20964 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20964 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20964 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 84017000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 84017000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1065172500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1065172500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1149189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1149189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1149189500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1149189500 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20962 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -646,19 +646,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64233.180428 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 64233.180428 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54190.705128 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54190.705128 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28818 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 562 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.277580 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -666,12 +666,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu
|
|||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16454 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16454 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16812 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16812 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16812 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16812 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
|
|
@ -680,14 +680,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -696,14 +696,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 1134670186 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1795.138964 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
|
||||
|
|
@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.148270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
|
||||
|
|
@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
|
||||
|
|
@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
|
||||
|
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 9046 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 9046 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
|
||||
|
|
@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 442570 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 442570 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits
|
||||
|
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 4652237184 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 18364 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1392.317060 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 18364 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
|
||||
|
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 441378 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 474121 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.325596 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.997708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 441378 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits
|
||||
|
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1529557 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 1529557 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 267269454 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
|
||||
|
|
@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 131235 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163291 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.869760 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.937769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 131235 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits
|
||||
|
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 265378090 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits
|
||||
|
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 94693 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 94693 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits
|
||||
|
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -73,15 +73,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 404484520 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits
|
||||
|
|
@ -151,19 +151,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 98540 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 129534 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.751918 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.941490 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 98540 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits
|
||||
|
|
@ -289,15 +289,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 5246772452 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
|
||||
|
|
@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926937 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 1926937 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits
|
||||
|
|
@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 4782410230 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 7 # number of replacements
|
||||
system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
|
||||
|
|
@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926075 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 1926075 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits
|
||||
|
|
@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 10 # number of replacements
|
||||
system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
|
||||
|
|
@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926197 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 1926197 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
|
||||
|
|
@ -290,15 +290,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.041671 # Number of seconds simulated
|
||||
sim_ticks 41671058000 # Number of ticks simulated
|
||||
final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.041672 # Number of seconds simulated
|
||||
sim_ticks 41671895000 # Number of ticks simulated
|
||||
final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79080 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79080 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35856814 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228800 # Number of bytes of host memory used
|
||||
host_seconds 1162.15 # Real time elapsed on the host
|
||||
host_inst_rate 84546 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84546 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38336000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228812 # Number of bytes of host memory used
|
||||
host_seconds 1087.02 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 41670985500 # Total gap between requests
|
||||
system.physmem.totGap 41671821000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -213,14 +213,14 @@ system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% #
|
|||
system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 21938250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 20561250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 64198750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4442.74 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13000.96 # Average bank access latency per request
|
||||
system.physmem.totBankLat 64336250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4163.88 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13028.81 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 22443.70 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 22192.69 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -233,8 +233,8 @@ system.physmem.readRowHits 4578 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 8438838.70 # Average gap between requests
|
||||
system.membus.throughput 7583969 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 8439007.90 # Average gap between requests
|
||||
system.membus.throughput 7583816 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
|
|
@ -245,39 +245,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032
|
|||
system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 316032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 13412467 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 13412627 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 19996249 # DTB read hits
|
||||
system.cpu.dtb.read_hits 19996270 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 19996259 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501862 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 19996280 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501863 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6501885 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498111 # DTB hits
|
||||
system.cpu.dtb.write_accesses 6501886 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498133 # DTB hits
|
||||
system.cpu.dtb.data_misses 33 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 26498144 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9957259 # ITB hits
|
||||
system.cpu.dtb.data_accesses 26498166 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956949 # ITB hits
|
||||
system.cpu.itb.fetch_misses 49 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 9957308 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 9956998 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -291,34 +291,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 83342117 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 83343791 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058018 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521724 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722400 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469281 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799226 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 82971475 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10802 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7733735 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75608382 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.720496 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.717920 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -330,72 +330,72 @@ system.cpu.committedInsts 91903056 # Nu
|
|||
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.906848 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.906848 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102720 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.102720 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27661043 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55681074 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.810247 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34090230 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251887 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.096035 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33490685 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851432 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.815414 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65315589 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026528 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.629554 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29482268 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859849 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.625007 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 7633 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.272065 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945862 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 9518 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.952931 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.272065 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728648 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728648 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945862 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945862 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945862 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945862 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945862 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945862 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11397 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11397 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11397 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11397 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11397 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11397 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 317452000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 317452000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 317452000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 317452000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 317452000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 317452000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9957259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9957259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9957259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9957259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9957259 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9957259 # number of overall (read+write) accesses
|
||||
system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945551 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11398 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9956949 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9956949 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27853.996666 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27853.996666 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -404,83 +404,83 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9518 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 9518 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 9518 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 9518 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9518 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9518 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260091000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 260091000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260091000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 260091000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260091000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 260091000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1878 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1878 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1878 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1878 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1878 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1878 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 259449500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 259449500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 259449500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 259449500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 259449500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 259449500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27326.223997 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27326.223997 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 18196610 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 9993 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 9993 # Transaction distribution
|
||||
system.cpu.toL2Bus.throughput 18199316 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19036 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19040 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 23589 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 23593 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 758272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 758272 # Total data (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 758400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6031000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 14277000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 14868500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2189.717368 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6791 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.069165 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.843612 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1820.867359 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.006398 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6724 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6777 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 6724 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 6803 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 6724 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 6803 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 6805 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
|
||||
|
|
@ -492,52 +492,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183057000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30189500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 213246500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114689000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 114689000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 183057000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 144878500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 327935500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 183057000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 144878500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 327935500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9518 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 182392000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29940500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 212332500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115205000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 115205000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 182392000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 145145500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 327537500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 182392000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 145145500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 327537500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9993 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 9518 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 11741 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 9518 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 11741 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293549 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.321825 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293549 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.420577 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293549 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420577 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65517.895490 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71539.099526 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66307.991294 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66602.206736 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66602.206736 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66410.591333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66410.591333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -557,73 +557,73 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 148372000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24939500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 173311500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93717750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93717750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 148372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118657250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 267029250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 148372000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118657250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 267029250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321825 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.420577 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420577 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53103.793844 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59098.341232 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53890.391791 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54423.780488 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54423.780488 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.455577 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488507 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.657670 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.455577 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492885 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492885 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488507 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488507 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488507 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488507 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488508 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8218 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8218 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8794 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8794 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8794 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8794 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38984000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 38984000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 463524000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 463524000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 502508000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 502508000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 502508000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 502508000 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8793 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -640,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000332
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67680.555556 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67680.555556 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56403.504502 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -660,12 +660,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu
|
|||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
|
|
@ -674,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -690,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 237458632 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
|
||||
|
|
@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
|
||||
|
|
@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 464144608 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
|
||||
|
|
@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
|
||||
|
|
@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 541126164 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1591.579171 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
|
||||
|
|
@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
|
||||
|
|
@ -274,15 +274,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 2 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -69,15 +69,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 501907914 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1455.296642 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
|
||||
|
|
@ -147,19 +147,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2058.178686 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
|
||||
|
|
@ -283,15 +283,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1363.457571 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 77195831 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40522.745932 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,43 +1,43 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.829331 # Number of seconds simulated
|
||||
sim_ticks 1829330593000 # Number of ticks simulated
|
||||
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.829332 # Number of seconds simulated
|
||||
sim_ticks 1829332269000 # Number of ticks simulated
|
||||
final_tick 1829332269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1529223 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1529222 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46594888750 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306208 # Number of bytes of host memory used
|
||||
host_seconds 39.26 # Real time elapsed on the host
|
||||
sim_insts 60037737 # Number of instructions simulated
|
||||
sim_ops 60037737 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory
|
||||
host_inst_rate 1710493 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1710492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52117657653 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306192 # Number of bytes of host memory used
|
||||
host_seconds 35.10 # Real time elapsed on the host
|
||||
sim_insts 60038305 # Number of instructions simulated
|
||||
sim_ops 60038305 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -184,18 +184,18 @@ system.physmem.writeRowHits 0 # Nu
|
|||
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap nan # Average gap between requests
|
||||
system.membus.throughput 42552299 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 77842222 # Total data (bytes)
|
||||
system.membus.throughput 42552540 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 77842734 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.replacements 41686 # number of replacements
|
||||
system.iocache.tagsinuse 1.225558 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy
|
||||
system.iocache.tags.replacements 41686 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
|
|
@ -247,22 +247,22 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9710417 # DTB read hits
|
||||
system.cpu.dtb.read_hits 9710427 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6352487 # DTB write hits
|
||||
system.cpu.dtb.write_hits 6352498 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 16062904 # DTB hits
|
||||
system.cpu.dtb.data_hits 16062925 # DTB hits
|
||||
system.cpu.dtb.data_misses 11471 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 4974615 # ITB hits
|
||||
system.cpu.itb.fetch_hits 4974648 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5006 # ITB misses
|
||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 4979621 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -275,51 +275,51 @@ system.cpu.itb.data_hits 0 # DT
|
|||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3658661078 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3658664430 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60037737 # Number of instructions committed
|
||||
system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 60038305 # Number of instructions committed
|
||||
system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484174 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55912968 # number of integer instructions
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913521 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115688 # number of memory refs
|
||||
system.cpu.num_load_insts 9747503 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368185 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
|
||||
system.cpu.num_mem_refs 16115709 # number of memory refs
|
||||
system.cpu.num_load_insts 9747513 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368196 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598609001.180807 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811927418500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829332061500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||
|
|
@ -358,7 +358,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu
|
|||
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
||||
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
||||
|
|
@ -367,20 +367,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu
|
|||
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192177 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1735 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1906
|
||||
system.cpu.kern.mode_good::user 1735
|
||||
system.cpu.kern.callpal::total 192180 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1909
|
||||
system.cpu.kern.mode_good::user 1738
|
||||
system.cpu.kern.mode_good::idle 171
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801032784000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
|
|
@ -413,35 +413,35 @@ system.tsunami.ethernet.totalRxOrn 0 # to
|
|||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.iobus.throughput 1480182 # Throughput (bytes/s)
|
||||
system.iobus.throughput 1480181 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 2707742 # Total data (bytes)
|
||||
system.cpu.icache.replacements 919577 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59129371 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920204 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.replacements 919609 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59129907 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59129907 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59129907 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59129907 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59129907 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59129907 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920236 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920236 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920236 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920236 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920236 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920236 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
||||
|
|
@ -457,75 +457,75 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 992297 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2433228 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.301012 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 56309.097197 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 4867.351143 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 4247.927159 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811231 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1718013 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.replacements 992301 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374219 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2433263 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.301036 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.327126 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.919252 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906812 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1718044 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833497 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833497 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998465 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905247 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998465 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905247 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906812 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998462 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905274 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906812 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998462 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905274 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738871 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920218 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2659090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833497 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833497 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963406 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963406 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920218 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043219 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963437 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920218 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043219 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963437 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511328 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511328 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384814 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384814 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511329 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357073 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511329 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357073 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -534,58 +534,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74287 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74291 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2042707 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
|
||||
system.cpu.dcache.tags.replacements 2042706 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807777 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807777 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848211 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848211 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655988 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655988 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655988 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655988 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026073 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026073 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026073 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026073 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
||||
|
|
@ -598,11 +598,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 833497 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833497 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 132867618 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 243048686 # Total data (bytes)
|
||||
system.cpu.toL2Bus.throughput 132868790 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 243051054 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -233,29 +233,29 @@ system.realview.nvmem.bw_total::total 75 # To
|
|||
system.membus.throughput 64986577 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 59274047 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.l2c.replacements 70658 # number of replacements
|
||||
system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1623339 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 135810 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 11.953015 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 70658 # number of replacements
|
||||
system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
|
||||
|
|
@ -486,15 +486,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe
|
|||
system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed
|
||||
system.cpu0.icache.replacements 428546 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.replacements 428546 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits
|
||||
|
|
@ -528,15 +528,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 323609 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.replacements 323609 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits
|
||||
|
|
@ -662,15 +662,15 @@ system.cpu1.not_idle_fraction 0.022362 # Pe
|
|||
system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed
|
||||
system.cpu1.icache.replacements 433942 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.replacements 433942 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits
|
||||
|
|
@ -704,15 +704,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 294289 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.replacements 294289 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits
|
||||
|
|
@ -772,12 +772,12 @@ system.cpu1.dcache.cache_copies 0 # nu
|
|||
system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 266849 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
|||
|
|
@ -284,15 +284,15 @@ system.cpu.not_idle_fraction 0.016889 # Pe
|
|||
system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 850590 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 850590 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
|
||||
|
|
@ -326,23 +326,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 62243 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 62243 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
|
||||
|
|
@ -434,15 +434,15 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 623337 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 623337 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
|
||||
|
|
@ -501,12 +501,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu
|
|||
system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -223,27 +223,27 @@ system.realview.nvmem.bw_total::total 9 # To
|
|||
system.membus.throughput 55969561 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566366 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.l2c.replacements 62242 # number of replacements
|
||||
system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1678485 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 127627 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 13.151488 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.763036 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 62242 # number of replacements
|
||||
system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits
|
||||
|
|
@ -456,17 +456,17 @@ system.cpu0.not_idle_fraction 0.959732 # Pe
|
|||
system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu0.icache.replacements 850590 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 511.678593 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 60583498 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 851102 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 71.182418 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.replacements 850590 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
|
||||
|
|
@ -512,17 +512,17 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 623334 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 511.997031 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 23628284 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 623846 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 37.875187 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.replacements 623334 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits
|
||||
|
|
@ -666,12 +666,12 @@ system.cpu1.not_idle_fraction -0.942843 # Pe
|
|||
system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
|||
|
|
@ -1,51 +1,51 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112100 # Number of seconds simulated
|
||||
sim_ticks 5112099860500 # Number of ticks simulated
|
||||
final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 5.112102 # Number of seconds simulated
|
||||
sim_ticks 5112102211000 # Number of ticks simulated
|
||||
final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 794426 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1626557 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 20315509625 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 586244 # Number of bytes of host memory used
|
||||
host_seconds 251.64 # Real time elapsed on the host
|
||||
sim_insts 199905607 # Number of instructions simulated
|
||||
sim_ops 409299132 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory
|
||||
host_inst_rate 878832 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1799374 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22473674513 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 586256 # Number of bytes of host memory used
|
||||
host_seconds 227.47 # Real time elapsed on the host
|
||||
sim_insts 199908396 # Number of instructions simulated
|
||||
sim_ops 409304707 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -192,34 +192,34 @@ system.physmem.writeRowHits 0 # Nu
|
|||
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap nan # Average gap between requests
|
||||
system.membus.throughput 9632717 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 49243411 # Total data (bytes)
|
||||
system.membus.throughput 9632725 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 49243475 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.replacements 47568 # number of replacements
|
||||
system.iocache.tagsinuse 0.042441 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47584 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
|
||||
system.iocache.tags.replacements 47569 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
|
||||
system.iocache.overall_misses::total 47623 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
|
||||
system.iocache.overall_misses::total 47624 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
||||
|
|
@ -241,7 +241,7 @@ system.iocache.writebacks::total 46667 # nu
|
|||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
||||
|
|
@ -252,58 +252,58 @@ system.pc.south_bridge.ide.disks1.dma_write_full_pages 1
|
|||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iobus.throughput 2555194 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 13062406 # Total data (bytes)
|
||||
system.cpu.numCycles 10224199744 # number of cpu cycles simulated
|
||||
system.iobus.data_through_bus 13062414 # Total data (bytes)
|
||||
system.cpu.numCycles 10224204444 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199905607 # Number of instructions committed
|
||||
system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374462047 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 199908396 # Number of instructions committed
|
||||
system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2307315 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374462047 # number of integer instructions
|
||||
system.cpu.num_func_calls 2307395 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374467605 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 915890300 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480542889 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 35654170 # number of memory refs
|
||||
system.cpu.num_load_insts 27234345 # Number of load instructions
|
||||
system.cpu.num_store_insts 8419825 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955627 # Percentage of idle cycles
|
||||
system.cpu.num_mem_refs 35655576 # number of memory refs
|
||||
system.cpu.num_load_insts 27235236 # Number of load instructions
|
||||
system.cpu.num_store_insts 8420340 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955626 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 790584 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243492014 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791103 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.replacements 790522 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243495984 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791041 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
|
||||
|
|
@ -319,15 +319,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.replacements 3477 # number of replacements
|
||||
system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
|
|
@ -367,39 +367,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu
|
|||
system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.replacements 7629 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12955 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8819 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8819 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8819 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8819 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8819 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8819 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21774 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -411,47 +411,47 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu
|
|||
system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1621960 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12073185 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12073185 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8093252 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8093252 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20166437 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308369 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308369 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316387 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316387 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624756 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097774 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.tags.replacements 1622027 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20167772 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624823 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -460,50 +460,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535700 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535756 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 54622198 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 279208723 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 25408 # Total snoop data (bytes)
|
||||
system.cpu.l2cache.replacements 105930 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64819.953901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3456506 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.325454 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 51906.788145 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10422.435543 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.989074 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits
|
||||
system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes)
|
||||
system.cpu.l2cache.tags.replacements 105931 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275491 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062559 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179721 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179721 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1455212 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2242280 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1455212 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2242280 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
|
||||
|
|
@ -511,58 +511,58 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 32246 #
|
|||
system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134393 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134393 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 179971 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 179970 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307737 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108137 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314114 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314114 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621851 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2422251 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621851 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2422251 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427848 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427848 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102746 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074299 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -571,8 +571,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98090 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98091 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000025 # Number of seconds simulated
|
||||
sim_ticks 24560000 # Number of ticks simulated
|
||||
final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 25046000 # Number of ticks simulated
|
||||
final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1785 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1785 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6860090 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225432 # Number of bytes of host memory used
|
||||
host_seconds 3.58 # Real time elapsed on the host
|
||||
host_inst_rate 25238 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 25236 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98905790 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225424 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu
|
|||
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 24545500 # Total gap between requests
|
||||
system.physmem.totGap 25031500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # By
|
|||
system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1607750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 1857500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2345000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7576250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3428.04 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16154.05 # Average bank access latency per request
|
||||
system.physmem.totBankLat 7617500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3960.55 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16242.00 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24582.09 # Average memory access latency
|
||||
system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 25202.56 # Average memory access latency
|
||||
system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 9.53 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 9.34 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.47 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 402 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 52335.82 # Average gap between requests
|
||||
system.membus.throughput 1219543974 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 53372.07 # Average gap between requests
|
||||
system.membus.throughput 1195879582 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952
|
|||
system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 29952 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.8 # Layer utilization (%)
|
||||
system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.5 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 1632 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
|
||||
|
|
@ -247,7 +247,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 49121 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 50093 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
|
||||
|
|
@ -269,12 +269,12 @@ system.cpu.execution_unit.executions 4448 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7376 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 15.015981 # Percentage of cycles cpu is active
|
||||
system.cpu.activity 14.724612 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1183 # Number of Load instructions committed
|
||||
system.cpu.comStores 865 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
||||
|
|
@ -286,36 +286,36 @@ system.cpu.committedInsts 6390 # Nu
|
|||
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy
|
||||
system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
|
||||
|
|
@ -328,12 +328,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n
|
|||
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 355 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
|
||||
|
|
@ -346,17 +346,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978
|
|||
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -372,26 +372,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302
|
|||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67756.622517 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67756.622517 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1222149837 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -405,22 +405,22 @@ system.cpu.toL2Bus.tot_pkt_size 30016 # Cu
|
|||
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 451500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 197.103662 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 140.828803 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.274859 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006015 # Average percentage of cache occupancy
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -438,17 +438,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20144000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6932500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27076500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4877500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4877500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20144000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11810000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31954000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20144000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11810000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31954000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -471,17 +471,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66923.588040 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72973.684211 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68375 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66815.068493 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66815.068493 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68132.196162 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68132.196162 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -501,17 +501,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16417750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5764000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22181750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16417750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9750750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26168500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16417750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9750750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26168500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -523,27 +523,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54544.019934 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60673.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56014.520202 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 102.747723 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 102.747723 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025085 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025085 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
|
||||
|
|
@ -560,14 +560,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n
|
|||
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 447 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7336500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7336500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21108000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21108000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28444500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28444500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28444500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28444500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -584,19 +584,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75634.020619 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75634.020619 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60308.571429 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60308.571429 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -616,14 +616,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7034000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7034000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4955000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4955000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11989000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11989000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11989000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11989000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -632,14 +632,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 65088 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
|
||||
|
|
@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -300,15 +300,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 33048 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 80.050296 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
|
||||
|
|
@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.003270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
|
||||
|
|
@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000016 # Number of seconds simulated
|
||||
sim_ticks 16387000 # Number of ticks simulated
|
||||
final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 16494000 # Number of ticks simulated
|
||||
final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31359 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39125 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 111893890 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244352 # Number of bytes of host memory used
|
||||
host_inst_rate 31208 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38937 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 112083077 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244336 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17344 # Nu
|
|||
system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 393 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 393 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 16329500 # Total gap between requests
|
||||
system.physmem.totGap 16436500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # By
|
|||
system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2029000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2047500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1965000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 5472500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5162.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13924.94 # Average bank access latency per request
|
||||
system.physmem.totBankLat 5445000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5209.92 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13854.96 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24087.79 # Average memory access latency
|
||||
system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 24064.89 # Average memory access latency
|
||||
system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 11.99 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.58 # Average read queue length over time
|
||||
system.physmem.busUtil 11.91 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.57 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 348 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 41550.89 # Average gap between requests
|
||||
system.membus.throughput 1534875206 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 41823.16 # Average gap between requests
|
||||
system.membus.throughput 1524918152 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -200,18 +200,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152
|
|||
system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25152 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 22.4 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 2471 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted
|
||||
system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 22.3 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 2479 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 695 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 697 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
|
||||
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
|
||||
|
|
@ -301,129 +301,129 @@ system.cpu.itb.inst_accesses 0 # IT
|
|||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 32775 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 32989 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2415 # Number of cycles decode is running
|
||||
system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2420 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
|
||||
system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2217 # Number of cycles rename is running
|
||||
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2221 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued
|
||||
|
|
@ -452,84 +452,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
||||
system.cpu.iq.rate 0.272189 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.FU_type_0::total 8917 # Type of FU issued
|
||||
system.cpu.iq.rate 0.270302 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 222 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3294 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1436 # Number of branches executed
|
||||
system.cpu.iew.exec_refs 3296 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.259863 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.258268 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3885 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7780 # num instructions consuming a value
|
||||
system.cpu.iew.wb_count 8067 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3881 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7779 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -542,23 +542,23 @@ system.cpu.commit.int_insts 4976 # Nu
|
|||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23312 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23396 # The number of ROB writes
|
||||
system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 23271 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23399 # The number of ROB writes
|
||||
system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39187 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
||||
system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39193 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7983 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 2976 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 2975 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -573,60 +573,60 @@ system.cpu.toL2Bus.data_through_bus 27968 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.icache.replacements 4 # number of replacements
|
||||
system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1578 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1578 # number of overall hits
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1583 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 364 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -642,36 +642,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
|
|||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 183.439490 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
|
||||
|
|
@ -692,17 +692,17 @@ system.cpu.l2cache.demand_misses::total 398 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 398 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18145000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6188500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24333500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2992500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2992500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18145000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9181000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 27326000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18145000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9181000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 27326000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -725,17 +725,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908676 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66955.719557 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71959.302326 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -761,17 +761,17 @@ system.cpu.l2cache.demand_mshr_misses::total 393
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14791750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4905500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19697250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2490250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2490250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14791750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22187500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14791750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22187500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -783,39 +783,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60737.804878 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60737.804878 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2366 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2369 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
|
||||
|
|
@ -826,53 +826,53 @@ system.cpu.dcache.demand_misses::cpu.data 497 # n
|
|||
system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 497 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -894,30 +894,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000016 # Number of seconds simulated
|
||||
sim_ticks 16387000 # Number of ticks simulated
|
||||
final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 16494000 # Number of ticks simulated
|
||||
final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 36614 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45680 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 130634561 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244344 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_inst_rate 66928 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 83502 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 240363471 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244336 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17344 # Nu
|
|||
system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 393 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 393 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 16329500 # Total gap between requests
|
||||
system.physmem.totGap 16436500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # By
|
|||
system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2029000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2047500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1965000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 5472500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5162.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13924.94 # Average bank access latency per request
|
||||
system.physmem.totBankLat 5445000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5209.92 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13854.96 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24087.79 # Average memory access latency
|
||||
system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 24064.89 # Average memory access latency
|
||||
system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 11.99 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.58 # Average read queue length over time
|
||||
system.physmem.busUtil 11.91 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.57 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 348 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 41550.89 # Average gap between requests
|
||||
system.membus.throughput 1534875206 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 41823.16 # Average gap between requests
|
||||
system.membus.throughput 1524918152 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -200,18 +200,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152
|
|||
system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25152 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 22.4 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 2471 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted
|
||||
system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 22.3 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 2479 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 695 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 697 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
|
|
@ -256,129 +256,129 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 32775 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 32989 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2415 # Number of cycles decode is running
|
||||
system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2420 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
|
||||
system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2217 # Number of cycles rename is running
|
||||
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2221 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued
|
||||
|
|
@ -407,84 +407,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
||||
system.cpu.iq.rate 0.272189 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.FU_type_0::total 8917 # Type of FU issued
|
||||
system.cpu.iq.rate 0.270302 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 222 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3294 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1436 # Number of branches executed
|
||||
system.cpu.iew.exec_refs 3296 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.259863 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.258268 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3885 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7780 # num instructions consuming a value
|
||||
system.cpu.iew.wb_count 8067 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3881 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7779 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -497,23 +497,23 @@ system.cpu.commit.int_insts 4976 # Nu
|
|||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23312 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23396 # The number of ROB writes
|
||||
system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 23271 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23399 # The number of ROB writes
|
||||
system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39187 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
||||
system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39193 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7983 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 2976 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 2975 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -528,60 +528,60 @@ system.cpu.toL2Bus.data_through_bus 27968 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.icache.replacements 4 # number of replacements
|
||||
system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1578 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1578 # number of overall hits
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1583 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 364 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -597,36 +597,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
|
|||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 183.439490 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
|
||||
|
|
@ -647,17 +647,17 @@ system.cpu.l2cache.demand_misses::total 398 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 398 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18145000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6188500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24333500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2992500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2992500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18145000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9181000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 27326000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18145000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9181000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 27326000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -680,17 +680,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908676 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66955.719557 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71959.302326 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -716,17 +716,17 @@ system.cpu.l2cache.demand_mshr_misses::total 393
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14791750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4905500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19697250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2490250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2490250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14791750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22187500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14791750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22187500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -738,39 +738,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60737.804878 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60737.804878 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2366 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2369 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
|
||||
|
|
@ -781,53 +781,53 @@ system.cpu.dcache.demand_misses::cpu.data 497 # n
|
|||
system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 497 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -849,30 +849,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 51938 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits
|
||||
|
|
@ -185,17 +185,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
|
||||
|
|
@ -313,15 +313,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000025 # Number of seconds simulated
|
||||
sim_ticks 24539000 # Number of ticks simulated
|
||||
final_tick 24539000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 24587000 # Number of ticks simulated
|
||||
final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 40560 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 40552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 171130571 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226208 # Number of bytes of host memory used
|
||||
host_inst_rate 41260 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41253 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 174426700 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226212 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu
|
|||
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 826765557 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 359916867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1186682424 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 826765557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 826765557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 826765557 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 359916867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1186682424 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 455 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 24472000 # Total gap between requests
|
||||
system.physmem.totGap 24519000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::960 1 1.06% 97.87% # By
|
|||
system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2632000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13115750 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2305250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2275000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8208750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5784.62 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18041.21 # Average bank access latency per request
|
||||
system.physmem.totBankLat 8195000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5066.48 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18010.99 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 28825.82 # Average memory access latency
|
||||
system.physmem.avgRdBW 1186.68 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 28077.47 # Average memory access latency
|
||||
system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1186.68 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 9.27 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.53 # Average read queue length over time
|
||||
system.physmem.busUtil 9.25 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.52 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 361 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 53784.62 # Average gap between requests
|
||||
system.membus.throughput 1186682424 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 53887.91 # Average gap between requests
|
||||
system.membus.throughput 1184365722 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 404 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 404 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
|
|
@ -201,9 +201,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120
|
|||
system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 29120 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4265750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.4 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 1157 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted
|
||||
|
|
@ -233,7 +233,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 49079 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 49175 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True).
|
||||
|
|
@ -255,12 +255,12 @@ system.cpu.execution_unit.executions 3133 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 9516 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 488 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 43696 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 5383 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 10.968031 # Percentage of cycles cpu is active
|
||||
system.cpu.activity 10.946619 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1163 # Number of Load instructions committed
|
||||
system.cpu.comStores 925 # Number of Store instructions committed
|
||||
system.cpu.comBranches 915 # Number of Branches instructions committed
|
||||
|
|
@ -272,36 +272,36 @@ system.cpu.committedInsts 5814 # Nu
|
|||
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 8.441520 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 8.441520 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.118462 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.118462 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 45429 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 7.436989 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 46265 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 5.733613 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 46314 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 5.633774 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 47841 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.522464 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 46189 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 5.888466 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.tagsinuse 150.599216 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 428 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 150.599216 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.073535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.073535 # Average percentage of cache occupancy
|
||||
system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
|
||||
|
|
@ -314,12 +314,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n
|
|||
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25149500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25149500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25149500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25149500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
|
||||
|
|
@ -332,12 +332,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871
|
|||
system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71855.714286 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 71855.714286 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 71855.714286 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 71855.714286 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -358,26 +358,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319
|
|||
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22969000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22969000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22969000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22969000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22969000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22969000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72003.134796 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72003.134796 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1191898610 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
|
|
@ -392,21 +392,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 208.333773 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 152.278645 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.055128 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006358 # Average percentage of cache occupancy
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -424,17 +424,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22623500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6716000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29339500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3640500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3640500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22623500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10356500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32980000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22623500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10356500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32980000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -457,17 +457,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71367.507886 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77195.402299 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72622.524752 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71382.352941 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71382.352941 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72483.516484 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72483.516484 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -487,17 +487,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18696000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5647250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24343250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18696000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8653250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27349250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18696000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8653250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27349250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -509,51 +509,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58977.917981 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64910.919540 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60255.569307 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 90.129103 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1637 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11.862319 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 90.129103 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.022004 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.022004 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1065 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1065 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1637 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1637 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1637 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1637 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 1638 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1638 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1638 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1638 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 451 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 451 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 451 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 451 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7478500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7478500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21383500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21383500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28862000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28862000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28862000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28862000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 450 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 450 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7523000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7523000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21590750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21590750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -562,38 +562,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 #
|
|||
system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084265 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.084265 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083405 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.083405 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.215996 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.215996 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.215996 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.215996 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76311.224490 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 76311.224490 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60576.487252 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60576.487252 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63995.565410 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63995.565410 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 253 # number of cycles access was blocked
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.461538 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 313 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 313 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 312 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 312 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
|
||||
|
|
@ -602,14 +602,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6809500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6809500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3694500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3694500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10504000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10504000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10504000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10504000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78270.114943 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78270.114943 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72441.176471 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72441.176471 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -83,15 +83,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 63266 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.tagsinuse 132.545353 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5513 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
|
||||
|
|
@ -161,17 +161,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -286,15 +286,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 18326500 # Number of ticks simulated
|
||||
final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 18469500 # Number of ticks simulated
|
||||
final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 41507 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41499 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 131284333 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224304 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 54927 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 54916 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 175080000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224296 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu
|
|||
system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 446 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 18199000 # Total gap between requests
|
||||
system.physmem.totGap 18341000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # By
|
|||
system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2004500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 1996500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2230000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 6737500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4494.39 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15106.50 # Average bank access latency per request
|
||||
system.physmem.totBankLat 6765000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4476.46 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15168.16 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24600.90 # Average memory access latency
|
||||
system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 24644.62 # Average memory access latency
|
||||
system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 12.17 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 12.07 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.60 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 380 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 40804.93 # Average gap between requests
|
||||
system.membus.throughput 1557525987 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 41123.32 # Average gap between requests
|
||||
system.membus.throughput 1545466851 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
|
|
@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544
|
|||
system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 22.7 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 2238 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
|
||||
|
|
@ -233,92 +233,92 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 9 # Number of system calls
|
||||
system.cpu.numCycles 36654 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 36940 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2263 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2096 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing
|
||||
system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2098 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1984 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups
|
||||
system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1987 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11308 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 226 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 9701 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 18192 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 18137 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 4703 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 575 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available
|
||||
|
|
@ -388,10 +388,10 @@ system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8903 # Type of FU issued
|
||||
system.cpu.iq.rate 0.242893 # Inst issue rate
|
||||
system.cpu.iq.rate 0.241012 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
|
||||
|
|
@ -408,12 +408,12 @@ system.cpu.iew.lsq.thread0.squashedStores 785 # N
|
|||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 10362 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
|
||||
|
|
@ -432,35 +432,35 @@ system.cpu.iew.exec_nop 0 # nu
|
|||
system.cpu.iew.exec_refs 3201 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1351 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1523 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.231953 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.230157 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8157 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 4222 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6684 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 4221 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6683 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 5792 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -473,22 +473,22 @@ system.cpu.commit.int_insts 5698 # Nu
|
|||
system.cpu.commit.function_calls 103 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 21419 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21457 # The number of ROB writes
|
||||
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 24797 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 21366 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21446 # The number of ROB writes
|
||||
system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5792 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.328384 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.328384 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.158018 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.158018 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 13474 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7049 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.toL2Bus.throughput 1581971462 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
|
|
@ -503,60 +503,60 @@ system.cpu.toL2Bus.data_through_bus 28992 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 526500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 167.412828 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1371 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.905983 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 167.412828 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.081745 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.081745 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1371 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1371 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1371 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1371 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1371 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1371 # number of overall hits
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1372 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1372 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1372 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 442 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28629500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28629500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28629500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28629500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28629500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28629500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243795 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.243795 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.243795 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.243795 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.243795 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.243795 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64772.624434 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 64772.624434 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 64772.624434 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 64772.624434 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 425 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1814 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1814 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1814 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243660 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.243660 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 70.833333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 72.166667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -572,36 +572,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351
|
|||
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23362000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23362000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23362000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23362000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23362000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23362000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66558.404558 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66558.404558 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 197.575721 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 166.296629 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.279092 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005075 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006030 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
|
||||
|
|
@ -622,17 +622,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22950500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4123000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27073500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3627500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22950500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7750500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30701000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22950500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7750500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30701000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23046250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4132250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27178500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3637250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3637250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 23046250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7769500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30815750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 23046250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7769500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30815750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -655,17 +655,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66523.188406 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76351.851852 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67853.383459 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77180.851064 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77180.851064 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68836.322870 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68836.322870 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66800.724638 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -685,17 +685,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18670000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22133750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3054750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3054750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18670000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6518500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 25188500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18670000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6518500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 25188500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18694250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6525500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -707,51 +707,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54115.942029 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64143.518519 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55473.057644 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64994.680851 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64994.680851 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 63.158434 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2188 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 21.450980 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 63.158434 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.015420 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.015420 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2188 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2192 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 435 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7358500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7358500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19767997 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19767997 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 27126497 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 27126497 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 27126497 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 27126497 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 431 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -762,36 +762,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2623
|
|||
system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.807692 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.807692 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59722.045317 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59722.045317 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62359.763218 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62359.763218 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
|
||||
|
|
@ -800,14 +800,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102
|
|||
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4188500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4188500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676999 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676999 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7865499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7865499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7865499 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7865499 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -816,14 +816,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76154.545455 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78234.021277 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78234.021277 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000021 # Number of seconds simulated
|
||||
sim_ticks 20764500 # Number of ticks simulated
|
||||
final_tick 20764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 20802500 # Number of ticks simulated
|
||||
final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 44697 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 44687 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 174155494 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232524 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 39959 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39952 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 155990706 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232536 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu
|
|||
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 890751041 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 413012594 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1303763635 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 890751041 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 890751041 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 890751041 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 413012594 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1303763635 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 423 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 20696000 # Total gap between requests
|
||||
system.physmem.totGap 20733000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # By
|
|||
system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3131250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11791250 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2859500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2115000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 6545000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 7402.48 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15472.81 # Average bank access latency per request
|
||||
system.physmem.totBankLat 6490000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6760.05 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15342.79 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 27875.30 # Average memory access latency
|
||||
system.physmem.avgRdBW 1303.76 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 27102.84 # Average memory access latency
|
||||
system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1303.76 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 10.19 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.57 # Average read queue length over time
|
||||
system.physmem.busUtil 10.17 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.55 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 358 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 48926.71 # Average gap between requests
|
||||
system.membus.throughput 1303763635 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 49014.18 # Average gap between requests
|
||||
system.membus.throughput 1301382045 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 342 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 342 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
|
|
@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072
|
|||
system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 27072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3936500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 19.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 18.9 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 1636 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
|
||||
|
|
@ -215,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT
|
|||
system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 41530 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 41606 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.execution_unit.executions 3957 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 9717 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 35284 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6246 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 15.039730 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 15.009854 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 715 # Number of Load instructions committed
|
||||
system.cpu.comStores 673 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1115 # Number of Branches instructions committed
|
||||
|
|
@ -254,36 +254,36 @@ system.cpu.committedInsts 5327 # Nu
|
|||
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 7.796133 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 7.796133 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.128269 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.128269 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 36890 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 11.172646 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 38335 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 7.693234 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 38497 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 7.303154 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 40555 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.347700 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 38373 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 7.601734 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 142.226837 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.065292 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 142.226837 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.069447 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.069447 # Average percentage of cache occupancy
|
||||
system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits
|
||||
|
|
@ -296,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n
|
|||
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 366 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25702500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25702500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25702500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25702500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25702500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25702500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
|
||||
|
|
@ -314,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938
|
|||
system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70225.409836 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70225.409836 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70225.409836 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70225.409836 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -340,26 +340,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
|
|||
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21114000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 21114000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21114000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 21114000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21114000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 21114000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72556.701031 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72556.701031 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1313010186 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
|
|
@ -374,21 +374,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 168.609847 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 141.647687 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.962160 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004323 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005146 # Average percentage of cache occupancy
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
|
|
@ -409,17 +409,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20795500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3765500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24561000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5904000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5904000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20795500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9669500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30465000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20795500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9669500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30465000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -442,17 +442,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71956.747405 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71047.169811 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71815.789474 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72888.888889 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72888.888889 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72021.276596 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72021.276596 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -472,17 +472,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17227750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3116250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20344000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4915500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4915500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17227750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8031750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 25259500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17227750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8031750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 25259500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -494,27 +494,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59611.591696 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58797.169811 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59485.380117 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60685.185185 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.185185 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 84.923213 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 84.923213 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020733 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020733 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
|
||||
|
|
@ -531,14 +531,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n
|
|||
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 474 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4316000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4316000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26761000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 26761000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31077000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31077000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31077000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31077000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -555,19 +555,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499
|
|||
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.098361 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.098361 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64796.610169 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64796.610169 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65563.291139 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65563.291139 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.406250 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.548387 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -587,14 +587,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
|||
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5987500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5987500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9819500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9819500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9819500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9819500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -603,14 +603,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70962.962963 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70962.962963 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73919.753086 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73919.753086 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 55600 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 117.043638 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
|
||||
|
|
@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
||||
|
|
@ -271,15 +271,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -69,15 +69,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 56716 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
|
||||
|
|
@ -147,17 +147,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -272,15 +272,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 27167500 # Number of ticks simulated
|
||||
final_tick 27167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 27282000 # Number of ticks simulated
|
||||
final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49297 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 49293 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 88314525 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232472 # Number of bytes of host memory used
|
||||
host_seconds 0.31 # Real time elapsed on the host
|
||||
host_inst_rate 50184 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50180 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 90285398 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232468 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu
|
|||
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 702015276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 325094322 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1027109598 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 702015276 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 702015276 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 702015276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 325094322 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1027109598 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 436 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 27134000 # Total gap between requests
|
||||
system.physmem.totGap 27248500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # By
|
|||
system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1645750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10137000 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 1525500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2180000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 6311250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3774.66 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14475.34 # Average bank access latency per request
|
||||
system.physmem.totBankLat 6325000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3498.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14506.88 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 23250.00 # Average memory access latency
|
||||
system.physmem.avgRdBW 1027.11 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 23005.73 # Average memory access latency
|
||||
system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1027.11 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 8.02 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 7.99 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.37 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 387 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 62233.94 # Average gap between requests
|
||||
system.membus.throughput 1024753842 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 62496.56 # Average gap between requests
|
||||
system.membus.throughput 1020453046 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
|
|
@ -203,7 +203,7 @@ system.membus.data_through_bus 27840 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4057250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 14.9 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 5146 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
|
||||
|
|
@ -215,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT
|
|||
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 54336 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 54565 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.execution_unit.executions 11045 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 21896 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 36768 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 32.332155 # Percentage of cycles cpu is active
|
||||
system.cpu.activity 32.196463 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 2225 # Number of Load instructions committed
|
||||
system.cpu.comStores 1448 # Number of Store instructions committed
|
||||
system.cpu.comBranches 3358 # Number of Branches instructions committed
|
||||
|
|
@ -254,36 +254,36 @@ system.cpu.committedInsts 15162 # Nu
|
|||
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 3.583696 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 3.583696 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.279042 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.279042 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 40910 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 24.709217 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 44983 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 17.213266 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 45533 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 16.201045 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 51458 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 5.296673 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 45027 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 17.132288 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 168.384950 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 3004 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 168.384950 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.082219 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.082219 # Average percentage of cache occupancy
|
||||
system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
|
||||
|
|
@ -296,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n
|
|||
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 381 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25319500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25319500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25319500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25319500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25319500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25319500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
|
||||
|
|
@ -314,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555
|
|||
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66455.380577 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 66455.380577 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 66455.380577 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 66455.380577 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -340,26 +340,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301
|
|||
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66573.089701 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66573.089701 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1029465354 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
|
|
@ -374,21 +374,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 448500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 199.348050 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 167.722707 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.625344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006084 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -406,17 +406,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19715000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3728500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 23443500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5878000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5878000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19715000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9606500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19715000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9606500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29321500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -439,17 +439,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.454849 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70349.056604 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66600.852273 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69152.941176 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69152.941176 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67097.254005 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67097.254005 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -469,17 +469,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16042000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19118500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16042000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7917250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23959250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16042000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7917250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23959250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -491,27 +491,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53652.173913 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58047.169811 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54313.920455 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 98.129274 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 98.129274 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.023957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.023957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
|
||||
|
|
@ -530,14 +530,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n
|
|||
system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 480 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4284500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4284500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25306500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25306500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29591000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29591000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29591000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29591000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -556,19 +556,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897
|
|||
system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73870.689655 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73870.689655 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.009479 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.009479 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61647.916667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61647.916667 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1016 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.882353 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.969697 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -588,14 +588,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3783000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3783000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5966000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5966000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9749000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9749000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9749000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9749000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -604,14 +604,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71377.358491 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71377.358491 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70188.235294 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70188.235294 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 26399500 # Number of ticks simulated
|
||||
final_tick 26399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 26524500 # Number of ticks simulated
|
||||
final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 93938 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 93929 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 171756334 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 52714 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52709 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 96835127 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234512 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu
|
|||
system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 812136593 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 356370386 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1168506979 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 812136593 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 812136593 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 812136593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 356370386 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1168506979 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 482 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 26239500 # Total gap between requests
|
||||
system.physmem.totGap 26363500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
|
|
@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # By
|
|||
system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1765750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10927000 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 1755500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2410000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 6751250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3663.38 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14006.74 # Average bank access latency per request
|
||||
system.physmem.totBankLat 6765000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3642.12 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14035.27 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 22670.12 # Average memory access latency
|
||||
system.physmem.avgRdBW 1168.51 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 22677.39 # Average memory access latency
|
||||
system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1168.51 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 9.13 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 9.09 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.41 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 430 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 54438.80 # Average gap between requests
|
||||
system.membus.throughput 1168506979 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 54696.06 # Average gap between requests
|
||||
system.membus.throughput 1163000245 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
|
|
@ -200,104 +200,104 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848
|
|||
system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 30848 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 583000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4486500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.0 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 6719 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 4457 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1075 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 5025 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 2433 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 6716 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 2432 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 48.417910 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 52800 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 53050 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 12414 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 31130 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6719 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 2877 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 3041 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 8772 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 994 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 5381 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 33187 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.938018 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.130523 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24054 72.48% 72.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4509 13.59% 86.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 475 1.43% 87.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 33187 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.127254 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.589583 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 13016 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 9761 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 8340 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 29004 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 13656 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 501 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 8734 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 7953 # Number of cycles rename is running
|
||||
system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 8344 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 7952 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 26651 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 23943 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 49443 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 49443 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 49456 # Number of integer rename lookups
|
||||
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 10124 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 3527 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 2284 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 22510 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 21113 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 7896 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5507 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 33187 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.636183 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.261114 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 23946 72.15% 72.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3557 10.72% 82.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2326 7.01% 89.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1693 5.10% 94.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 889 2.68% 97.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 472 1.42% 99.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 239 0.72% 99.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 33187 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available
|
||||
|
|
@ -333,113 +333,113 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 15643 74.09% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 15651 74.10% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 2108 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 21113 # Type of FU issued
|
||||
system.cpu.iq.rate 0.399867 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 21122 # Type of FU issued
|
||||
system.cpu.iq.rate 0.398153 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.006963 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 75656 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 31087 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 19513 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 21260 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1302 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 836 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 398 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 3527 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 2284 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 359 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 24307 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1209 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 20068 # Number of executed instructions
|
||||
system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 1134 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 5224 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 4238 # Number of branches executed
|
||||
system.cpu.iew.exec_branches 4239 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 2022 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.380076 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 19741 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 19513 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 9111 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 11226 # num instructions consuming a value
|
||||
system.cpu.iew.exec_rate 0.378398 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 19522 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 9120 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 11235 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.369564 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.811598 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1075 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 31317 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.484146 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.180879 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 23994 76.62% 76.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 4076 13.02% 89.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 763 2.44% 96.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 350 1.12% 97.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 272 0.87% 98.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 322 1.03% 99.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 115 0.37% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 31317 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 15162 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -450,24 +450,24 @@ system.cpu.commit.branches 3358 # Nu
|
|||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 187 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 54580 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 50280 # The number of ROB writes
|
||||
system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19613 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 54596 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 50298 # The number of ROB writes
|
||||
system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 14436 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.657523 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.657523 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.273409 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.273409 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 32029 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 17831 # number of integer regfile writes
|
||||
system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 32043 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 17841 # number of integer regfile writes
|
||||
system.cpu.misc_regfile_reads 6919 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1173355556 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
|
|
@ -482,55 +482,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 505500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 187.819339 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4874 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 14.462908 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 187.819339 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.091709 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.091709 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4874 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4874 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4874 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4874 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4874 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4874 # number of overall hits
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 4873 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 507 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30807500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 30807500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 30807500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 30807500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 30807500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 30807500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5381 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5381 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5381 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5381 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5381 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5381 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094220 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.094220 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.094220 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.094220 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.094220 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.094220 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60764.299803 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 60764.299803 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 60764.299803 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 60764.299803 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -551,36 +551,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 337
|
|||
system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22247500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22247500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22247500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22247500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22247500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22247500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062628 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.062628 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.062628 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66016.320475 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66016.320475 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 221.715806 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 187.205303 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 34.510503 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005713 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001053 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006766 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -598,17 +598,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 482 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21890500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4591500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26482000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5706000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5706000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21890500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10297500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32188000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21890500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10297500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32188000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -631,17 +631,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65344.776119 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71742.187500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66370.927318 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68746.987952 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68746.987952 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66780.082988 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66780.082988 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -661,17 +661,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17748750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3809500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21558250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4697250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4697250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17748750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8506750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26255500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17748750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8506750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26255500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -683,27 +683,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52981.343284 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59523.437500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54030.701754 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56593.373494 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56593.373494 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 98.861742 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 4001 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27.217687 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 98.861742 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.024136 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.024136 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
|
||||
|
|
@ -722,14 +722,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n
|
|||
system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 535 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7949500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7949500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24575974 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 24575974 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 32525474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32525474 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 32525474 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32525474 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -748,19 +748,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102
|
|||
system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63091.269841 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63091.269841 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60087.955990 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60087.955990 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60795.278505 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60795.278505 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -780,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4656000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4656000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5790000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5790000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10446000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10446000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10446000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10446000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -796,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69759.036145 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69759.036145 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 82736 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
|
||||
|
|
@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
|
|||
system.cpu.num_busy_cycles 1454144 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 265.013024 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.129401 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
|
||||
|
|
@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.014695 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
|
||||
|
|
@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -118,15 +118,15 @@ system.cpu0.num_idle_cycles 0 # Nu
|
|||
system.cpu0.num_busy_cycles 500032 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu0.icache.replacements 152 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
|
||||
|
|
@ -160,15 +160,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 61 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
|
||||
|
|
@ -267,15 +267,15 @@ system.cpu1.num_idle_cycles 0 # Nu
|
|||
system.cpu1.num_busy_cycles 500032 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu1.icache.replacements 152 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
|
||||
|
|
@ -309,15 +309,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 61 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits
|
||||
|
|
@ -416,15 +416,15 @@ system.cpu2.num_idle_cycles 0 # Nu
|
|||
system.cpu2.num_busy_cycles 500032 # Number of busy cycles
|
||||
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu2.icache.replacements 152 # number of replacements
|
||||
system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
|
||||
system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
|
||||
system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
|
||||
|
|
@ -458,15 +458,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.dcache.replacements 61 # number of replacements
|
||||
system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
|
||||
system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
||||
system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits
|
||||
|
|
@ -565,15 +565,15 @@ system.cpu3.num_idle_cycles 0 # Nu
|
|||
system.cpu3.num_busy_cycles 500032 # Number of busy cycles
|
||||
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu3.icache.replacements 152 # number of replacements
|
||||
system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu3.icache.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
|
||||
system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
|
||||
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
|
||||
system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
|
||||
system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
|
||||
|
|
@ -607,15 +607,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.dcache.replacements 61 # number of replacements
|
||||
system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu3.dcache.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
|
||||
system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor
|
||||
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits
|
||||
system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
||||
system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits
|
||||
|
|
@ -659,31 +659,31 @@ system.cpu3.dcache.cache_copies 0 # nu
|
|||
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
|
||||
system.cpu3.dcache.writebacks::total 29 # number of writebacks
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.replacements 0 # number of replacements
|
||||
system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use
|
||||
system.l2c.total_refs 332 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.029950 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
|
||||
|
|
|
|||
|
|
@ -171,15 +171,15 @@ system.cpu0.num_idle_cycles 0 # Nu
|
|||
system.cpu0.num_busy_cycles 1458048 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu0.icache.replacements 152 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 216.376897 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.422611 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
|
||||
|
|
@ -249,15 +249,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330
|
|||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 61 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 273.500146 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.534180 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
|
||||
|
|
@ -404,15 +404,15 @@ system.cpu1.num_idle_cycles 0 # Nu
|
|||
system.cpu1.num_busy_cycles 1458048 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu1.icache.replacements 152 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 216.373058 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.422604 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits
|
||||
|
|
@ -482,15 +482,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775
|
|||
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 61 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 273.495183 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.534170 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
|
||||
|
|
@ -637,15 +637,15 @@ system.cpu2.num_idle_cycles 0 # Nu
|
|||
system.cpu2.num_busy_cycles 1458048 # Number of busy cycles
|
||||
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu2.icache.replacements 152 # number of replacements
|
||||
system.cpu2.icache.tagsinuse 216.369218 # Cycle average of tags in use
|
||||
system.cpu2.icache.total_refs 499542 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.avg_refs 1078.924406 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.occ_percent::total 0.422596 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use
|
||||
system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits
|
||||
system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits
|
||||
system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits
|
||||
|
|
@ -715,15 +715,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220
|
|||
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
|
||||
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.dcache.replacements 61 # number of replacements
|
||||
system.cpu2.dcache.tagsinuse 273.490220 # Cycle average of tags in use
|
||||
system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.occ_percent::total 0.534161 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use
|
||||
system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits
|
||||
system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
|
||||
system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
|
||||
|
|
@ -870,15 +870,15 @@ system.cpu3.num_idle_cycles 0 # Nu
|
|||
system.cpu3.num_busy_cycles 1458048 # Number of busy cycles
|
||||
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu3.icache.replacements 152 # number of replacements
|
||||
system.cpu3.icache.tagsinuse 216.365379 # Cycle average of tags in use
|
||||
system.cpu3.icache.total_refs 499535 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.avg_refs 1078.909287 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor
|
||||
system.cpu3.icache.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.occ_percent::total 0.422589 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.tags.replacements 152 # number of replacements
|
||||
system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use
|
||||
system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor
|
||||
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits
|
||||
system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits
|
||||
system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits
|
||||
|
|
@ -948,15 +948,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665
|
|||
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
|
||||
system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
|
||||
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.dcache.replacements 61 # number of replacements
|
||||
system.cpu3.dcache.tagsinuse 273.485257 # Cycle average of tags in use
|
||||
system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor
|
||||
system.cpu3.dcache.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.occ_percent::total 0.534151 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.tags.replacements 61 # number of replacements
|
||||
system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use
|
||||
system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor
|
||||
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits
|
||||
system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
|
||||
system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
|
||||
|
|
@ -1048,31 +1048,31 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464
|
|||
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.replacements 0 # number of replacements
|
||||
system.l2c.tagsinuse 1943.172107 # Cycle average of tags in use
|
||||
system.l2c.total_refs 332 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.029650 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -86,15 +86,15 @@ system.cpu0.num_idle_cycles 0 # Nu
|
|||
system.cpu0.num_busy_cycles 175415 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu0.icache.replacements 215 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.replacements 215 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
|
||||
|
|
@ -128,15 +128,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.replacements 2 # number of replacements
|
||||
system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.replacements 2 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
|
||||
|
|
@ -210,15 +210,15 @@ system.cpu1.num_idle_cycles 7873.724337 # Nu
|
|||
system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
|
||||
system.cpu1.icache.replacements 278 # number of replacements
|
||||
system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.replacements 278 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
|
||||
|
|
@ -252,15 +252,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.replacements 0 # number of replacements
|
||||
system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
|
||||
|
|
@ -332,15 +332,15 @@ system.cpu2.num_idle_cycles 7936.951217 # Nu
|
|||
system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
|
||||
system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
|
||||
system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
|
||||
system.cpu2.icache.replacements 278 # number of replacements
|
||||
system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use
|
||||
system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.tags.replacements 278 # number of replacements
|
||||
system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
|
||||
system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
|
||||
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
|
||||
system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
|
||||
system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
|
||||
|
|
@ -374,15 +374,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.dcache.replacements 0 # number of replacements
|
||||
system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use
|
||||
system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
|
||||
system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
|
||||
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
|
||||
system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
|
||||
system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
|
||||
|
|
@ -454,15 +454,15 @@ system.cpu3.num_idle_cycles 8001.119846 # Nu
|
|||
system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
|
||||
system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
|
||||
system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
|
||||
system.cpu3.icache.replacements 279 # number of replacements
|
||||
system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use
|
||||
system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
|
||||
system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.tags.replacements 279 # number of replacements
|
||||
system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
|
||||
system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
|
||||
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
|
||||
system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
|
||||
system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
|
||||
|
|
@ -496,15 +496,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.dcache.replacements 0 # number of replacements
|
||||
system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use
|
||||
system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
|
||||
system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
|
||||
system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
|
||||
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
|
||||
system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
|
||||
system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
|
||||
|
|
@ -554,31 +554,31 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.replacements 0 # number of replacements
|
||||
system.l2c.tagsinuse 366.582542 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1220 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 421 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 2.897862 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 12296459257 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231220 # Number of bytes of host memory used
|
||||
host_seconds 8.13 # Real time elapsed on the host
|
||||
host_tick_rate 29067628326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231288 # Number of bytes of host memory used
|
||||
host_seconds 3.44 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
|
||||
system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
|
||||
|
|
@ -519,7 +519,5 @@ system.monitor.writeTransHist::17 0 0.00% 100.00% # Hi
|
|||
system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
|
||||
system.monitor.readAddrDist::total 16 # Read address distribution
|
||||
system.monitor.writeAddrDist::total 16 # Write address distribution
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 7576487056 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230980 # Number of bytes of host memory used
|
||||
host_seconds 13.20 # Real time elapsed on the host
|
||||
host_tick_rate 14083896029 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231304 # Number of bytes of host memory used
|
||||
host_seconds 7.10 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory
|
||||
|
|
@ -376,7 +376,5 @@ system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% #
|
|||
system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
|
||||
system.monitor.readAddrDist::total 16 # Read address distribution
|
||||
system.monitor.writeAddrDist::total 16 # Write address distribution
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue