5a15909bac
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
835 lines
95 KiB
Plaintext
835 lines
95 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000012 # Number of seconds simulated
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sim_ticks 11933500 # Number of ticks simulated
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final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 492 # Simulator instruction rate (inst/s)
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host_op_rate 492 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2461163 # Simulator tick rate (ticks/s)
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host_mem_usage 226156 # Number of bytes of host memory used
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host_seconds 4.85 # Real time elapsed on the host
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sim_insts 2387 # Number of instructions simulated
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sim_ops 2387 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
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system.physmem.bytes_read::total 17472 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 273 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 17472 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 11844000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 273 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation
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system.physmem.totQLat 1190000 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests
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system.physmem.totBusLat 1365000 # Total cycles spent in databus access
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system.physmem.totBankLat 4180000 # Total cycles spent in bank access
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system.physmem.avgQLat 4358.97 # Average queueing delay per request
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system.physmem.avgBankLat 15311.36 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 24670.33 # Average memory access latency
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system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 11.44 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.56 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 240 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 43384.62 # Average gap between requests
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system.membus.throughput 1464113630 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 249 # Transaction distribution
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system.membus.trans_dist::ReadResp 249 # Transaction distribution
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system.membus.trans_dist::ReadExReq 24 # Transaction distribution
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system.membus.trans_dist::ReadExResp 24 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 546 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 17472 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
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system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
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system.cpu.branchPred.lookups 1175 # Number of BP lookups
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system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 253 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 31.467662 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 707 # DTB read hits
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system.cpu.dtb.read_misses 31 # DTB read misses
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system.cpu.dtb.read_acv 1 # DTB read access violations
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system.cpu.dtb.read_accesses 738 # DTB read accesses
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system.cpu.dtb.write_hits 371 # DTB write hits
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system.cpu.dtb.write_misses 20 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 391 # DTB write accesses
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system.cpu.dtb.data_hits 1078 # DTB hits
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system.cpu.dtb.data_misses 51 # DTB misses
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system.cpu.dtb.data_acv 1 # DTB access violations
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system.cpu.dtb.data_accesses 1129 # DTB accesses
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system.cpu.itb.fetch_hits 1067 # ITB hits
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system.cpu.itb.fetch_misses 30 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 1097 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numCycles 23868 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 1156 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 1065 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 6674 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 4046 # Type of FU issued
|
|
system.cpu.iq.rate 0.169516 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 338 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 1130 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 644 # Number of branches executed
|
|
system.cpu.iew.exec_stores 391 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.161513 # Inst execution rate
|
|
system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 3661 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1709 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2209 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
|
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 709 # Number of memory references committed
|
|
system.cpu.commit.loads 415 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 396 # Number of branches committed
|
|
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 71 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 12303 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 11127 # The number of ROB writes
|
|
system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
|
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
|
system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 4674 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2826 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 816 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 816 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 816 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 251 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 251 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 251 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 251 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 251 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 251 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16843749 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 16843749 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 16843749 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 16843749 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 16843749 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 16843749 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235239 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.235239 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.235239 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.235239 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.235239 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.235239 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67106.569721 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 67106.569721 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 67106.569721 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 67106.569721 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12795749 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12795749 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12795749 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12795749 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12795749 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12795749 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176195 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.176195 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.176195 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68062.494681 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68062.494681 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12607000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4547250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 17154250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1720750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1720750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 12607000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6268000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 18875000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 12607000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6268000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 18875000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67058.510638 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74545.081967 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68892.570281 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71697.916667 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71697.916667 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69139.194139 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69139.194139 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10234500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3797750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14032250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1425250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1425250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10234500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 15457500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10234500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 15457500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54438.829787 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62258.196721 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 758 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 758 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 758 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 758 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 194 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 194 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 952 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 952 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 952 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 952 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.171733 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.171733 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.250000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 109 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 109 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 109 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|