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gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
Andreas Hansson 5a15909bac stats: Update stats for monitor, cache and bus changes 
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
2013-06-27 05:49:51 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.023492 # Number of seconds simulated
sim_ticks 23492267500 # Number of ticks simulated
final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 122951 # Simulator instruction rate (inst/s)
host_op_rate 122951 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34312389 # Simulator tick rate (ticks/s)
host_mem_usage 231868 # Number of bytes of host memory used
host_seconds 684.66 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory
system.physmem.bytes_read::total 334464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 8339084 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5898111 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14237195 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8339084 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8339084 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5226 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 5226 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 334464 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 301 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 220 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 227 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 220 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 289 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 491 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 446 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 23492140500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 5226 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1366 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 416 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 780.923077 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 283.989164 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1375.157964 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 120 28.85% 28.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 59 14.18% 43.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 37 8.89% 51.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 19 4.57% 56.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 16 3.85% 60.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 20 4.81% 65.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 8 1.92% 67.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 8 1.92% 68.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 5 1.20% 70.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 5 1.20% 71.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 6 1.44% 72.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 8 1.92% 74.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 6 1.44% 76.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 4 0.96% 77.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 4 0.96% 78.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 2 0.48% 78.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 5 1.20% 79.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 4 0.96% 83.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 3 0.72% 83.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 3 0.72% 85.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 4 0.96% 86.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 4 0.96% 89.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 2 0.48% 90.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 1 0.24% 91.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 2 0.48% 91.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 1 0.24% 91.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 2 0.48% 92.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 1 0.24% 93.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 1 0.24% 93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 5 1.20% 96.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 1 0.24% 97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 1 0.24% 98.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 1 0.24% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 416 # Bytes accessed per row activation
system.physmem.totQLat 21308250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 115583250 # Sum of mem lat for all requests
system.physmem.totBusLat 26130000 # Total cycles spent in databus access
system.physmem.totBankLat 68145000 # Total cycles spent in bank access
system.physmem.avgQLat 4077.35 # Average queueing delay per request
system.physmem.avgBankLat 13039.61 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22116.96 # Average memory access latency
system.physmem.avgRdBW 14.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.24 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.11 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 4810 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 92.04 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 4495243.11 # Average gap between requests
system.membus.throughput 14237195 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3520 # Transaction distribution
system.membus.trans_dist::ReadResp 3520 # Transaction distribution
system.membus.trans_dist::ReadExReq 1706 # Transaction distribution
system.membus.trans_dist::ReadExResp 1706 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 10452 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 10452 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334464 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 334464 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 334464 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 49069500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.branchPred.lookups 14868892 # Number of BP lookups
system.cpu.branchPred.condPredicted 10787177 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 926932 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8430316 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6969924 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 82.676901 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1469870 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3126 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 23134581 # DTB read hits
system.cpu.dtb.read_misses 192685 # DTB read misses
system.cpu.dtb.read_acv 2 # DTB read access violations
system.cpu.dtb.read_accesses 23327266 # DTB read accesses
system.cpu.dtb.write_hits 7072669 # DTB write hits
system.cpu.dtb.write_misses 1128 # DTB write misses
system.cpu.dtb.write_acv 2 # DTB write access violations
system.cpu.dtb.write_accesses 7073797 # DTB write accesses
system.cpu.dtb.data_hits 30207250 # DTB hits
system.cpu.dtb.data_misses 193813 # DTB misses
system.cpu.dtb.data_acv 4 # DTB access violations
system.cpu.dtb.data_accesses 30401063 # DTB accesses
system.cpu.itb.fetch_hits 14756036 # ITB hits
system.cpu.itb.fetch_misses 101 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 14756137 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 46984536 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 15488073 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 127117981 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14868892 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 8439794 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22159630 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4494895 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 5563054 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2312 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14756036 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 325999 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 46746670 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.719295 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.375691 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24587040 52.60% 52.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2365337 5.06% 57.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1191741 2.55% 60.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1747442 3.74% 63.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2760154 5.90% 69.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1154764 2.47% 72.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1218466 2.61% 74.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 772204 1.65% 76.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10949522 23.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 46746670 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.705528 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17316199 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4260248 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 20549941 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1098483 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3521799 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 2517933 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12169 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 124122749 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 32253 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3521799 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18461305 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 962240 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 7648 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20480612 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3313066 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 121283530 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 398899 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 147895466 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 9699627 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 733 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 729 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 8785388 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 25392018 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 8252125 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2596537 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 925406 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 105547434 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2098 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 96644788 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 177437 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 20878127 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 15672265 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1709 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 46746670 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.067415 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.876261 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 12170136 26.03% 26.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 9358863 20.02% 46.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8416132 18.00% 64.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6289434 13.45% 77.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4916374 10.52% 88.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2864607 6.13% 94.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1727461 3.70% 97.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 797242 1.71% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 206421 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 46746670 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 188535 12.02% 12.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 207 0.01% 12.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 7191 0.46% 12.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 5653 0.36% 12.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 842893 53.74% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 446132 28.45% 95.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 77750 4.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 58781922 60.82% 60.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 479844 0.50% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2799901 2.90% 64.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 115380 0.12% 64.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2387749 2.47% 66.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 311051 0.32% 67.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 760106 0.79% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 23852037 24.68% 92.60% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7156472 7.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 96644788 # Type of FU issued
system.cpu.iq.rate 2.056949 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1568361 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016228 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 226659796 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 117693658 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 87130802 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15122248 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8768674 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7065649 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 90221948 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7991194 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1517986 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 5395820 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 18680 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 34810 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1751022 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 10535 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1932 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3521799 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 133427 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 18321 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 115791419 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 375079 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 25392018 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 8252125 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2098 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2892 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 34810 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 537595 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 497018 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1034613 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 95405393 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23327731 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1239395 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 10241887 # number of nop insts executed
system.cpu.iew.exec_refs 30401730 # number of memory reference insts executed
system.cpu.iew.exec_branches 12031007 # Number of branches executed
system.cpu.iew.exec_stores 7073999 # Number of stores executed
system.cpu.iew.exec_rate 2.030570 # Inst execution rate
system.cpu.iew.wb_sent 94717591 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 94196451 # cumulative count of insts written-back
system.cpu.iew.wb_producers 64508240 # num instructions producing a value
system.cpu.iew.wb_consumers 89892394 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.004839 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.717616 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 23889448 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 915179 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 43224871 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.126161 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.744271 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 16760873 38.78% 38.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 9929358 22.97% 61.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4485318 10.38% 72.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2262602 5.23% 77.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1610546 3.73% 81.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1125217 2.60% 83.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 721883 1.67% 85.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 816904 1.89% 87.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5512170 12.75% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 43224871 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 26497301 # Number of memory references committed
system.cpu.commit.loads 19996198 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 10240685 # Number of branches committed
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5512170 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 153504164 # The number of ROB reads
system.cpu.rob.rob_writes 235130535 # The number of ROB writes
system.cpu.timesIdled 5262 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 237866 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.558146 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.558146 # CPI: Total CPI of All Threads
system.cpu.ipc 1.791647 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.791647 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 129142322 # number of integer regfile reads
system.cpu.int_regfile_writes 70569523 # number of integer regfile writes
system.cpu.fp_regfile_reads 6189856 # number of floating regfile reads
system.cpu.fp_regfile_writes 6047601 # number of floating regfile writes
system.cpu.misc_regfile_reads 714537 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 37717943 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 12006 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 22984 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4598 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 27582 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 735488 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150592 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 886080 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 17871250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 9559 # number of replacements
system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14741729 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14741729 # number of overall hits
system.cpu.icache.overall_hits::total 14741729 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 14307 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 14307 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 14307 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 14307 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 14307 # number of overall misses
system.cpu.icache.overall_misses::total 14307 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 399491250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 399491250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 399491250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 399491250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 399491250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 399491250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14756036 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14756036 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14756036 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14756036 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14756036 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14756036 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27922.782554 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 27922.782554 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 27922.782554 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 27922.782554 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2815 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2815 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2815 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2815 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2815 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2815 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11492 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 11492 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 11492 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 11492 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 11492 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 11492 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295512250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 295512250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295512250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 295512250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295512250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 295512250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000779 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25714.605813 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25714.605813 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2404.485668 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8502 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.370226 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.679636 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.666457 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 379.139575 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061269 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011570 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.073379 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 8431 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 8486 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 8431 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 8511 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8431 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits
system.cpu.l2cache.overall_hits::total 8511 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3061 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 459 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3520 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1706 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1706 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3061 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5226 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3061 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses
system.cpu.l2cache.overall_misses::total 5226 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 199703250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34029500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 233732750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114147250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 114147250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 199703250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 148176750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 347880000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 199703250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 148176750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 347880000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11492 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 514 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 12006 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 11492 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 13737 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 11492 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 13737 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266359 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892996 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.293187 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985557 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266359 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.380432 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266359 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.380432 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65241.179353 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74138.344227 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66401.349432 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66909.290739 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66909.290739 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65241.179353 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68441.916859 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66567.164179 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65241.179353 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68441.916859 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66567.164179 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3061 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3520 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3061 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5226 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3061 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5226 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160781250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28303000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 189084250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93191250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93191250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160781250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121494250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 282275500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160781250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121494250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 282275500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266359 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892996 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293187 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985557 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266359 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.380432 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266359 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.380432 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52525.726887 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61662.309368 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53717.116477 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54625.586166 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54625.586166 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52525.726887 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52525.726887 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 158 # number of replacements
system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21603146 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6492891 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6492891 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 28096037 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28096037 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28096037 # number of overall hits
system.cpu.dcache.overall_hits::total 28096037 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 988 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 988 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 8212 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 8212 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9200 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9200 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9200 # number of overall misses
system.cpu.dcache.overall_misses::total 9200 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 60150500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 60150500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 476870547 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 476870547 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 537021047 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 537021047 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 537021047 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 537021047 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 21604134 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 21604134 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 237 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 28105237 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28105237 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28105237 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28105237 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001263 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001263 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004219 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004219 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60881.072874 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60881.072874 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58069.964321 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 58069.964321 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 58371.852935 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 58371.852935 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 21919 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.235119 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 108 # number of writebacks
system.cpu.dcache.writebacks::total 108 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 475 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 475 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6481 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6481 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6956 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6956 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6956 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6956 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35017250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 35017250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116268497 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 116268497 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151285747 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 151285747 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151285747 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 151285747 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004219 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004219 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68259.746589 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68259.746589 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67168.398036 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67168.398036 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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