5a15909bac
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
1406 lines
158 KiB
Plaintext
1406 lines
158 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.000729 # Number of seconds simulated
|
|
sim_ticks 729024000 # Number of ticks simulated
|
|
final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 1420709 # Simulator instruction rate (inst/s)
|
|
host_op_rate 1420692 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 517863701 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 236964 # Number of bytes of host memory used
|
|
host_seconds 1.41 # Real time elapsed on the host
|
|
sim_insts 1999959 # Number of instructions simulated
|
|
sim_ops 1999959 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
|
|
system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
|
|
system.physmem.bw_read::cpu0.inst 35378808 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 39856027 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 35378808 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 39856027 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu2.inst 35378808 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu2.data 39856027 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu3.inst 35378808 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu3.data 39856027 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 300939338 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu2.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu3.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 141515231 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 39856027 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 39856027 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu2.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu2.data 39856027 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu3.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu3.data 39856027 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 300939338 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 300939338 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 2872 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 2872 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 556 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 556 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side 6856 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count 6856 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side 219392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size 219392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 219392 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.membus.respLayer0.occupancy 31051500 # Layer occupancy (ticks)
|
|
system.membus.respLayer0.utilization 4.3 # Layer utilization (%)
|
|
system.toL2Bus.throughput 335352471 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 926 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 955 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count 7524 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size 244480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 244480 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 2374000 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 2083500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%)
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 124435 # DTB read hits
|
|
system.cpu0.dtb.read_misses 8 # DTB read misses
|
|
system.cpu0.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 124443 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 56340 # DTB write hits
|
|
system.cpu0.dtb.write_misses 10 # DTB write misses
|
|
system.cpu0.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 56350 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 180775 # DTB hits
|
|
system.cpu0.dtb.data_misses 18 # DTB misses
|
|
system.cpu0.dtb.data_acv 0 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 180793 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 500020 # ITB hits
|
|
system.cpu0.itb.fetch_misses 13 # ITB misses
|
|
system.cpu0.itb.fetch_acv 0 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 500033 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu0.numCycles 1458048 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 500001 # Number of instructions committed
|
|
system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 474689 # number of integer instructions
|
|
system.cpu0.num_fp_insts 32 # number of float instructions
|
|
system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 180793 # number of memory refs
|
|
system.cpu0.num_load_insts 124443 # Number of load instructions
|
|
system.cpu0.num_store_insts 56350 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 1458048 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu0.icache.tags.replacements 152 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 499557 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23096000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 23096000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 23096000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 23096000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 23096000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 23096000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49883.369330 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 49883.369330 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 49883.369330 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 49883.369330 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22170000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 22170000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22170000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 22170000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22170000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 22170000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47883.369330 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 61 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17474500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7669500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 25144000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53933.641975 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 139 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24218000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 124435 # DTB read hits
|
|
system.cpu1.dtb.read_misses 8 # DTB read misses
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 124443 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 56339 # DTB write hits
|
|
system.cpu1.dtb.write_misses 10 # DTB write misses
|
|
system.cpu1.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 56349 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 180774 # DTB hits
|
|
system.cpu1.dtb.data_misses 18 # DTB misses
|
|
system.cpu1.dtb.data_acv 0 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 180792 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 500012 # ITB hits
|
|
system.cpu1.itb.fetch_misses 13 # ITB misses
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 500025 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu1.numCycles 1458048 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 499993 # Number of instructions committed
|
|
system.cpu1.committedOps 499993 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 474681 # number of integer instructions
|
|
system.cpu1.num_fp_insts 32 # number of float instructions
|
|
system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 180792 # number of memory refs
|
|
system.cpu1.num_load_insts 124443 # Number of load instructions
|
|
system.cpu1.num_store_insts 56349 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 1458048 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu1.icache.tags.replacements 152 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 499549 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 499549 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 499549 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23105000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 23105000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 23105000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 23105000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 23105000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 23105000 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 500012 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 500012 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 500012 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 500012 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 500012 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 500012 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49902.807775 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 49902.807775 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 49902.807775 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 49902.807775 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22179000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22179000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22179000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47902.807775 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.tags.replacements 61 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 180311 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17474500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7669500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 25144000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53933.641975 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55176.258993 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 139 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24218000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu2.dtb.read_hits 124433 # DTB read hits
|
|
system.cpu2.dtb.read_misses 8 # DTB read misses
|
|
system.cpu2.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu2.dtb.read_accesses 124441 # DTB read accesses
|
|
system.cpu2.dtb.write_hits 56339 # DTB write hits
|
|
system.cpu2.dtb.write_misses 10 # DTB write misses
|
|
system.cpu2.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
|
|
system.cpu2.dtb.data_hits 180772 # DTB hits
|
|
system.cpu2.dtb.data_misses 18 # DTB misses
|
|
system.cpu2.dtb.data_acv 0 # DTB access violations
|
|
system.cpu2.dtb.data_accesses 180790 # DTB accesses
|
|
system.cpu2.itb.fetch_hits 500005 # ITB hits
|
|
system.cpu2.itb.fetch_misses 13 # ITB misses
|
|
system.cpu2.itb.fetch_acv 0 # ITB acv
|
|
system.cpu2.itb.fetch_accesses 500018 # ITB accesses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.read_acv 0 # DTB read access violations
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.write_acv 0 # DTB write access violations
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.data_hits 0 # DTB hits
|
|
system.cpu2.itb.data_misses 0 # DTB misses
|
|
system.cpu2.itb.data_acv 0 # DTB access violations
|
|
system.cpu2.itb.data_accesses 0 # DTB accesses
|
|
system.cpu2.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu2.numCycles 1458048 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 499986 # Number of instructions committed
|
|
system.cpu2.committedOps 499986 # Number of ops (including micro ops) committed
|
|
system.cpu2.num_int_alu_accesses 474674 # Number of integer alu accesses
|
|
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
|
|
system.cpu2.num_int_insts 474674 # number of integer instructions
|
|
system.cpu2.num_fp_insts 32 # number of float instructions
|
|
system.cpu2.num_int_register_reads 654263 # number of times the integer registers were read
|
|
system.cpu2.num_int_register_writes 371529 # number of times the integer registers were written
|
|
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu2.num_mem_refs 180790 # number of memory refs
|
|
system.cpu2.num_load_insts 124441 # Number of load instructions
|
|
system.cpu2.num_store_insts 56349 # Number of store instructions
|
|
system.cpu2.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu2.num_busy_cycles 1458048 # Number of busy cycles
|
|
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu2.icache.tags.replacements 152 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 499542 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 499542 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 499542 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23114000 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 23114000 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 23114000 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 23114000 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 23114000 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 23114000 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 500005 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 500005 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 500005 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 500005 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 500005 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 500005 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49922.246220 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 49922.246220 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 49922.246220 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 49922.246220 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22188000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 22188000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22188000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 22188000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22188000 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 22188000 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47922.246220 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.tags.replacements 61 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 180309 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 180309 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 180309 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 180309 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17474500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7669500 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 25144000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 180772 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 180772 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53933.641975 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55176.258993 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu2.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24218000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu3.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu3.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu3.dtb.read_hits 124431 # DTB read hits
|
|
system.cpu3.dtb.read_misses 8 # DTB read misses
|
|
system.cpu3.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu3.dtb.read_accesses 124439 # DTB read accesses
|
|
system.cpu3.dtb.write_hits 56339 # DTB write hits
|
|
system.cpu3.dtb.write_misses 10 # DTB write misses
|
|
system.cpu3.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu3.dtb.write_accesses 56349 # DTB write accesses
|
|
system.cpu3.dtb.data_hits 180770 # DTB hits
|
|
system.cpu3.dtb.data_misses 18 # DTB misses
|
|
system.cpu3.dtb.data_acv 0 # DTB access violations
|
|
system.cpu3.dtb.data_accesses 180788 # DTB accesses
|
|
system.cpu3.itb.fetch_hits 499998 # ITB hits
|
|
system.cpu3.itb.fetch_misses 13 # ITB misses
|
|
system.cpu3.itb.fetch_acv 0 # ITB acv
|
|
system.cpu3.itb.fetch_accesses 500011 # ITB accesses
|
|
system.cpu3.itb.read_hits 0 # DTB read hits
|
|
system.cpu3.itb.read_misses 0 # DTB read misses
|
|
system.cpu3.itb.read_acv 0 # DTB read access violations
|
|
system.cpu3.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu3.itb.write_hits 0 # DTB write hits
|
|
system.cpu3.itb.write_misses 0 # DTB write misses
|
|
system.cpu3.itb.write_acv 0 # DTB write access violations
|
|
system.cpu3.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu3.itb.data_hits 0 # DTB hits
|
|
system.cpu3.itb.data_misses 0 # DTB misses
|
|
system.cpu3.itb.data_acv 0 # DTB access violations
|
|
system.cpu3.itb.data_accesses 0 # DTB accesses
|
|
system.cpu3.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu3.numCycles 1458048 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.committedInsts 499979 # Number of instructions committed
|
|
system.cpu3.committedOps 499979 # Number of ops (including micro ops) committed
|
|
system.cpu3.num_int_alu_accesses 474668 # Number of integer alu accesses
|
|
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
|
|
system.cpu3.num_int_insts 474668 # number of integer instructions
|
|
system.cpu3.num_fp_insts 32 # number of float instructions
|
|
system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read
|
|
system.cpu3.num_int_register_writes 371524 # number of times the integer registers were written
|
|
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu3.num_mem_refs 180788 # number of memory refs
|
|
system.cpu3.num_load_insts 124439 # Number of load instructions
|
|
system.cpu3.num_store_insts 56349 # Number of store instructions
|
|
system.cpu3.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu3.num_busy_cycles 1458048 # Number of busy cycles
|
|
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu3.icache.tags.replacements 152 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 499535 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 499535 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 499535 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23123000 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 23123000 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 23123000 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 23123000 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 23123000 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 23123000 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 499998 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 499998 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 499998 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 499998 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 499998 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 499998 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49941.684665 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 49941.684665 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 49941.684665 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 49941.684665 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22197000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 22197000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22197000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 22197000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22197000 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 22197000 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 47941.684665 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.tags.replacements 61 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 180307 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 180307 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 180307 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 180307 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17474500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7669500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 25144000 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 124431 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 180770 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 180770 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 180770 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 180770 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53933.641975 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55176.258993 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu3.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 139 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24218000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 116 # number of Writeback hits
|
|
system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
|
system.l2c.overall_hits::total 276 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
|
|
system.l2c.overall_misses::total 3428 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 21101500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 21110000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 16409500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 21118500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 16409500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.inst 21129500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.data 16412000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 150100000 # number of ReadReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 7252500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 7252500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 7252500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 7252500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 29010000 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 21101500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 21110000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 23662000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 21118500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 23662000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 21129500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 23664500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 179110000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 21101500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 23662000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 21110000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 23662000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 21118500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 23662000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 21129500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 23664500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 179110000 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52361.042184 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52093.650794 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52382.133995 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52093.650794 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52403.225806 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52093.650794 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52430.521092 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.data 52101.587302 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 52263.231198 # average ReadReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52176.258993 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52176.258993 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52176.258993 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52176.258993 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 52176.258993 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 52361.042184 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 52382.133995 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 52118.942731 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 52403.225806 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 52118.942731 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 52430.521092 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 52124.449339 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 52249.124854 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 52361.042184 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 52382.133995 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 52118.942731 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 52403.225806 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 52118.942731 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 52430.521092 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 52124.449339 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 52249.124854 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 2872 # number of ReadReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 556 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 3428 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16120000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12600000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16274000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12629500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16282500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12629500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16293500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12632000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 115461000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5560000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5584500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5584500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5584500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 22313500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 16120000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 18160000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 16274000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 18214000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 16282500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 18214000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 16293500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 18216500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 137774500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 16120000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 18160000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 16274000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 18214000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 16282500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 18214000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 16293500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 18216500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 137774500 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050 # average ReadReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|