5a15909bac
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
980 lines
111 KiB
Text
980 lines
111 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.024977 # Number of seconds simulated
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sim_ticks 24977022500 # Number of ticks simulated
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final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 130696 # Simulator instruction rate (inst/s)
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host_op_rate 130696 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 41014411 # Simulator tick rate (ticks/s)
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host_mem_usage 236320 # Number of bytes of host memory used
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host_seconds 608.98 # Real time elapsed on the host
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sim_insts 79591756 # Number of instructions simulated
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sim_ops 79591756 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 166305 # Total number of read requests seen
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system.physmem.writeReqs 114016 # Total number of write requests seen
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system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 10643520 # Total number of bytes read from memory
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system.physmem.bytesWritten 7297024 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 24976988500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 166305 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 114016 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation
|
|
system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 831510000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 1564048750 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 39434.04 # Average queueing delay per request
|
|
system.physmem.avgBankLat 9404.87 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 53838.91 # Average memory access latency
|
|
system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 5.61 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.36 # Average read queue length over time
|
|
system.physmem.avgWrQLen 9.86 # Average write queue length over time
|
|
system.physmem.readRowHits 154145 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 76216 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 89101.38 # Average gap between requests
|
|
system.membus.throughput 718281933 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 35508 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 35508 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 114016 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 130797 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 130797 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side 446626 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940544 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 17940544 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 5.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
|
|
system.cpu.branchPred.lookups 16531947 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 22403443 # DTB read hits
|
|
system.cpu.dtb.read_misses 219972 # DTB read misses
|
|
system.cpu.dtb.read_acv 45 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 22623415 # DTB read accesses
|
|
system.cpu.dtb.write_hits 15699616 # DTB write hits
|
|
system.cpu.dtb.write_misses 41064 # DTB write misses
|
|
system.cpu.dtb.write_acv 1 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 15740680 # DTB write accesses
|
|
system.cpu.dtb.data_hits 38103059 # DTB hits
|
|
system.cpu.dtb.data_misses 261036 # DTB misses
|
|
system.cpu.dtb.data_acv 46 # DTB access violations
|
|
system.cpu.dtb.data_accesses 38364095 # DTB accesses
|
|
system.cpu.itb.fetch_hits 13905618 # ITB hits
|
|
system.cpu.itb.fetch_misses 35229 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 13940847 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
|
system.cpu.numCycles 49954048 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 122850608 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 451670 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued
|
|
system.cpu.iq.rate 1.769927 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 9476343 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 15087087 # Number of branches executed
|
|
system.cpu.iew.exec_stores 15740989 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.753174 # Inst execution rate
|
|
system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 33345535 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
|
|
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 34890015 # Number of memory references committed
|
|
system.cpu.commit.loads 20276638 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 13754477 # Number of branches committed
|
|
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 133828176 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 195767077 # The number of ROB writes
|
|
system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
|
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 115893073 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 57500612 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 249654 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 240130 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 38049 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580061 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5969600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23967680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 91227 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 13799737 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 13799737 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 13799737 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 105880 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 105880 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 105880 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 105880 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 105880 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 105880 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2067336982 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 2067336982 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 2067336982 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 2067336982 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 2067336982 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 2067336982 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 13905617 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 13905617 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 13905617 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 13905617 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 13905617 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 13905617 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007614 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.007614 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.007614 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.007614 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.007614 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.007614 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19525.283170 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 19525.283170 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 19525.283170 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 19525.283170 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 35.812500 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12604 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 12604 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 12604 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 12604 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 12604 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 12604 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93276 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 93276 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 93276 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 93276 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 93276 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 93276 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1585767766 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1585767766 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1585767766 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1585767766 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1585767766 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1585767766 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006708 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.006708 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.006708 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17000.812278 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17000.812278 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 132400 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.970668 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 26388.752281 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.805321 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064277 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.067817 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.937414 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 85619 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 34304 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 119923 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 168929 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 168929 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 12613 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 12613 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 85619 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 46917 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 132536 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 85619 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 46917 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 132536 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 7657 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 27852 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 35509 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 130797 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 130797 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 7657 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 158649 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 166306 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 7657 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 158649 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 166306 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 635688000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2109478250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2745166250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14069629000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 14069629000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 635688000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 16179107250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 16814795250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 635688000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 16179107250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 16814795250 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 93276 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 62156 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 155432 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 168929 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 168929 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143410 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 143410 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 93276 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 205566 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 298842 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 93276 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 205566 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 298842 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082090 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448098 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.228454 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912049 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.912049 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082090 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771767 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.556501 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082090 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771767 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.556501 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83020.504114 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75738.842812 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77309.027289 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107568.438114 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107568.438114 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.504114 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101980.518314 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 101107.568278 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.504114 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101980.518314 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 101107.568278 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 114016 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 114016 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7657 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27852 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 35509 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130797 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 130797 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7657 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 158649 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 166306 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7657 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 158649 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 166306 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 538279000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1751974750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2290253750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12463858000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12463858000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538279000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14215832750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 14754111750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538279000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14215832750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 14754111750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448098 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228454 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912049 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912049 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.556501 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.556501 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70298.942144 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62903.014146 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64497.838576 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95291.619838 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95291.619838 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 201470 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 13574108 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 34190013 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 34190013 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 34190013 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 34190013 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 267467 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 267467 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1039269 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1039269 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1306736 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1306736 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1306736 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1306736 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15939734750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 15939734750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 90566913172 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 90566913172 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 106506647922 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 106506647922 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 106506647922 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 106506647922 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 20883372 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 20883372 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 168929 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|