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Stats: Update stats for cache timings in cycles

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This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
This commit is contained in:
Andreas Hansson 2012-10-15 08:12:21 -04:00
parent 88554790c3
commit d52adc4eb6
44 changed files with 14176 additions and 14341 deletions
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3002
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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232
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 1.855236 # Nu
sim_ticks 1855236450500 # Number of ticks simulated
final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 87142 # Simulator instruction rate (inst/s)
host_op_rate 87142 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3050446700 # Simulator tick rate (ticks/s)
host_mem_usage 299400 # Number of bytes of host memory used
host_seconds 608.19 # Real time elapsed on the host
host_inst_rate 182093 # Simulator instruction rate (inst/s)
host_op_rate 182093 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6374280472 # Simulator tick rate (ticks/s)
host_mem_usage 298212 # Number of bytes of host memory used
host_seconds 291.05 # Real time elapsed on the host
sim_insts 52998368 # Number of instructions simulated
sim_ops 52998368 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory
@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910
system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@ -258,12 +258,12 @@ system.cpu.iq.iqSquashedOperandsExamined 3652702 # Nu
system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle
@ -521,11 +521,11 @@ system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067
system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
@ -541,24 +541,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1021072
system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1402622 # number of replacements
system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use
@ -595,16 +595,16 @@ system.cpu.dcache.overall_misses::cpu.data 3739889 #
system.cpu.dcache.overall_misses::total 3739889 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses)
@ -631,22 +631,22 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.245731
system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks
@ -675,16 +675,16 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1385390
system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles
@ -705,16 +705,16 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028
system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -765,19 +765,19 @@ system.cpu.l2cache.demand_misses::total 404416 # nu
system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses
system.cpu.l2cache.overall_misses::total 404416 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808283500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 21260842000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21260842000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses)
@ -808,19 +808,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.166826 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -850,25 +850,25 @@ system.cpu.l2cache.demand_mshr_misses::total 404415
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses
@ -882,19 +882,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
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@ -1,133 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.116889 # Number of seconds simulated
sim_ticks 2233777512 # Number of ticks simulated
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
host_inst_rate 3140005 # Simulator instruction rate (inst/s)
host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3147745 # Simulator tick rate (ticks/s)
host_mem_usage 511524 # Number of bytes of host memory used
host_seconds 709.64 # Real time elapsed on the host
sim_insts 2228284650 # Number of instructions simulated
sim_ops 2229160714 # Number of ops (including micro ops) simulated
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s)
system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s)
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
system.physmem.num_other::total 14 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s)
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2228284650 # Number of instructions committed
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
system.cpu.num_int_insts 1839325658 # number of integer instructions
system.cpu.num_fp_insts 14608322 # number of float instructions
system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
system.cpu.num_mem_refs 547951940 # number of memory refs
system.cpu.num_load_insts 349807670 # Number of load instructions
system.cpu.num_store_insts 198144270 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------

26
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.271545 # Nu
sim_ticks 271544682500 # Number of ticks simulated
final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 105483 # Simulator instruction rate (inst/s)
host_op_rate 105483 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47591638 # Simulator tick rate (ticks/s)
host_mem_usage 219440 # Number of bytes of host memory used
host_seconds 5705.72 # Real time elapsed on the host
host_inst_rate 142205 # Simulator instruction rate (inst/s)
host_op_rate 142205 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64159611 # Simulator tick rate (ticks/s)
host_mem_usage 212920 # Number of bytes of host memory used
host_seconds 4232.33 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55134.540117
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 175 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 58.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits
@ -276,12 +276,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545
system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 42145 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4093205 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.320164 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19.357151 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
@ -410,11 +410,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed

70
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.133202 # Nu
sim_ticks 133202081500 # Number of ticks simulated
final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 189557 # Simulator instruction rate (inst/s)
host_op_rate 189557 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44645563 # Simulator tick rate (ticks/s)
host_mem_usage 220464 # Number of bytes of host memory used
host_seconds 2983.55 # Real time elapsed on the host
host_inst_rate 258977 # Simulator instruction rate (inst/s)
host_op_rate 258977 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 60995759 # Simulator tick rate (ticks/s)
host_mem_usage 213944 # Number of bytes of host memory used
host_seconds 2183.79 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
@ -480,12 +480,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 7340.245420
system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 483496 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 963 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 413 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4740.156863 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.441176 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 37.545455 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 444931 # number of writebacks
@ -571,14 +571,14 @@ system.cpu.l2cache.overall_misses::total 26388 # nu
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34437000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 148748500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 183185500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844656996 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 844656996 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844655000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 844655000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 34437000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 993405496 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1027842496 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 993403500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1027840500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 34437000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 993405496 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1027842496 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 993403500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1027840500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 210276 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 211255 # number of ReadReq accesses(hits+misses)
@ -606,19 +606,19 @@ system.cpu.l2cache.overall_miss_rate::total 0.056655 #
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.172864 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.172864 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.078437 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.078437 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 38951.132939 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 38951.057299 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 38951.132939 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 100996 # number of cycles access was blocked
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 38951.057299 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 198 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1246.864198 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2.444444 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
@ -638,14 +638,14 @@ system.cpu.l2cache.overall_mshr_misses::total 26388
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31379500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167175000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778051996 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778051996 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778050000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778050000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31379500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913847496 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 945226996 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913845500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 945225000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31379500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913847496 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 945226996 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913845500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 945225000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses
@ -660,14 +660,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.056655
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.212508 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.118081 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.118081 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

70
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.163008 # Nu
sim_ticks 163008222000 # Number of ticks simulated
final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 104701 # Simulator instruction rate (inst/s)
host_op_rate 110635 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29939476 # Simulator tick rate (ticks/s)
host_mem_usage 234836 # Number of bytes of host memory used
host_seconds 5444.59 # Real time elapsed on the host
host_inst_rate 178133 # Simulator instruction rate (inst/s)
host_op_rate 188229 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 50937760 # Simulator tick rate (ticks/s)
host_mem_usage 228580 # Number of bytes of host memory used
host_seconds 3200.15 # Real time elapsed on the host
sim_insts 570052710 # Number of instructions simulated
sim_ops 602360916 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
@ -502,12 +502,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 8537.033204
system.cpu.dcache.demand_avg_miss_latency::total 8537.033204 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 8537.033204 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 28514592 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 54626 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3014 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9460.714001 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 1000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.124088 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 421091 # number of writebacks
@ -595,14 +595,14 @@ system.cpu.l2cache.overall_misses::total 28446 # nu
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27249500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 189324500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 216574000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 974455801 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 974455801 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 974356500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 974356500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27249500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1163780301 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1191029801 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1163681000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1190930500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27249500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1163780301 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1191029801 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1163681000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1190930500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 818 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 197352 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 198170 # number of ReadReq accesses(hits+misses)
@ -630,19 +630,19 @@ system.cpu.l2cache.overall_miss_rate::total 0.063881 #
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36092.052980 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.870616 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34607.542346 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43918.144988 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43918.144988 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43913.669551 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43913.669551 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42027.384385 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 41869.851684 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 41866.360824 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42027.384385 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 41869.851684 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 13672801 # number of cycles access was blocked
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 41866.360824 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 27147 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 2920 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4682.466096 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9.296918 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
@ -671,14 +671,14 @@ system.cpu.l2cache.overall_mshr_misses::total 28433
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197057000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 900047801 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 900047801 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899948500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899948500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24797500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072307301 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1097104801 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072208000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1097005500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24797500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072307301 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1097104801 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072208000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1097005500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses
@ -693,14 +693,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.063852
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40564.620561 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40564.620561 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40560.145123 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40560.145123 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

14
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.386987 # Nu
sim_ticks 386986985000 # Number of ticks simulated
final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 135169 # Simulator instruction rate (inst/s)
host_op_rate 135595 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37331500 # Simulator tick rate (ticks/s)
host_mem_usage 223688 # Number of bytes of host memory used
host_seconds 10366.23 # Real time elapsed on the host
host_inst_rate 190632 # Simulator instruction rate (inst/s)
host_op_rate 191233 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 52649747 # Simulator tick rate (ticks/s)
host_mem_usage 217240 # Number of bytes of host memory used
host_seconds 7350.22 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory
@ -453,11 +453,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 6577.376711
system.cpu.dcache.demand_avg_miss_latency::total 6577.376711 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 6577.376711 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 6577.376711 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed

14
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.025432 # Nu
sim_ticks 25432499000 # Number of ticks simulated
final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 141358 # Simulator instruction rate (inst/s)
host_op_rate 142373 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 39681246 # Simulator tick rate (ticks/s)
host_mem_usage 367916 # Number of bytes of host memory used
host_seconds 640.92 # Real time elapsed on the host
host_inst_rate 191631 # Simulator instruction rate (inst/s)
host_op_rate 193007 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53793580 # Simulator tick rate (ticks/s)
host_mem_usage 361656 # Number of bytes of host memory used
host_seconds 472.78 # Real time elapsed on the host
sim_insts 90599358 # Number of instructions simulated
sim_ops 91249911 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory
@ -494,11 +494,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 7044.800890
system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 12648 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1374.477220 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.940175 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed

20
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.201852 # Nu
sim_ticks 201852280500 # Number of ticks simulated
final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 114620 # Simulator instruction rate (inst/s)
host_op_rate 129121 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45458575 # Simulator tick rate (ticks/s)
host_mem_usage 239092 # Number of bytes of host memory used
host_seconds 4440.36 # Real time elapsed on the host
host_inst_rate 135871 # Simulator instruction rate (inst/s)
host_op_rate 153059 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53886430 # Simulator tick rate (ticks/s)
host_mem_usage 232836 # Number of bytes of host memory used
host_seconds 3745.88 # Real time elapsed on the host
sim_insts 508955133 # Number of instructions simulated
sim_ops 573341693 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory
@ -162,9 +162,9 @@ system.cpu.iq.issued_per_cycle::samples 402291353 # Nu
system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 143645798 35.71% 35.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 74204622 18.45% 54.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 68520864 17.03% 71.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle
@ -503,11 +503,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 12757.829762
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6644 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 11.928187 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks

212
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.427481 # Number of seconds simulated
sim_ticks 427481057500 # Number of ticks simulated
final_tick 427481057500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 427481054500 # Number of ticks simulated
final_tick 427481054500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54913 # Simulator instruction rate (inst/s)
host_op_rate 101540 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28388930 # Simulator tick rate (ticks/s)
host_mem_usage 267916 # Number of bytes of host memory used
host_seconds 15058.02 # Real time elapsed on the host
host_inst_rate 86006 # Simulator instruction rate (inst/s)
host_op_rate 159036 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44463827 # Simulator tick rate (ticks/s)
host_mem_usage 261156 # Number of bytes of host memory used
host_seconds 9614.13 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988699 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory
@ -24,18 +24,18 @@ system.physmem.num_reads::total 434860 # Nu
system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory
system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 64585224 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 64585225 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 48653683 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 48653683 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 48653683 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 48653684 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 48653684 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 48653684 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 64585224 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 113758416 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 64585225 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 113758417 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 854962116 # number of cpu cycles simulated
system.cpu.numCycles 854962110 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups
@ -52,16 +52,16 @@ system.cpu.fetch.Branches 221542687 # Nu
system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 200356871 # Number of cycles fetch has spent blocked
system.cpu.fetch.BlockedCycles 200356865 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 847490251 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 847490245 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 469274174 55.37% 55.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 469274168 55.37% 55.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total)
@ -73,11 +73,11 @@ system.cpu.fetch.rateDist::8 188811034 22.28% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 847490251 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 847490245 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 159033013 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 159033007 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing
@ -85,7 +85,7 @@ system.cpu.decode.DecodedInsts 2233248714 # Nu
system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 34110312 # Number of cycles rename is blocking
system.cpu.rename.BlockCycles 34110306 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking
@ -114,11 +114,11 @@ system.cpu.iq.iqSquashedInstsIssued 951947 # Nu
system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 847490251 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 847490245 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 226384740 26.71% 26.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 226384734 26.71% 26.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle
@ -130,7 +130,7 @@ system.cpu.iq.issued_per_cycle::8 1920111 0.23% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 847490251 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 847490245 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available
@ -203,7 +203,7 @@ system.cpu.iq.FU_type_0::total 1834774344 # Ty
system.cpu.iq.rate 2.146030 # Inst issue rate
system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4534784465 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 4534784459 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads
@ -223,7 +223,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 10593 #
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 3929046 # Number of cycles IEW is blocking
system.cpu.iew.iewBlockCycles 3929040 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch
@ -256,11 +256,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 770294264 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 770294258 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 276893916 35.95% 35.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 276893910 35.95% 35.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle
@ -272,7 +272,7 @@ system.cpu.commit.committed_per_cycle::8 68515952 8.89% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 770294264 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 770294258 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -285,7 +285,7 @@ system.cpu.commit.int_insts 1528317557 # Nu
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 68515952 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2788262369 # The number of ROB reads
system.cpu.rob.rob_reads 2788262363 # The number of ROB reads
system.cpu.rob.rob_writes 4250388650 # The number of ROB writes
system.cpu.timesIdled 191112 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7471865 # Total number of cycles that the CPU has spent unscheduled due to idling
@ -302,12 +302,12 @@ system.cpu.fp_regfile_reads 9183 # nu
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 992828832 # number of misc regfile reads
system.cpu.icache.replacements 5688 # number of replacements
system.cpu.icache.tagsinuse 1035.102627 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1035.102624 # Cycle average of tags in use
system.cpu.icache.total_refs 179169407 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 7297 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 24553.845005 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1035.102627 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1035.102624 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.505421 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.505421 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 179186003 # number of ReadReq hits
@ -322,12 +322,12 @@ system.cpu.icache.demand_misses::cpu.inst 199745 # n
system.cpu.icache.demand_misses::total 199745 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 199745 # number of overall misses
system.cpu.icache.overall_misses::total 199745 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237682000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1237682000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1237682000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1237682000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1237682000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1237682000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237681000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1237681000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1237681000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1237681000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1237681000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1237681000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 179385748 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 179385748 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 179385748 # number of demand (read+write) accesses
@ -340,12 +340,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001113
system.cpu.icache.demand_miss_rate::total 0.001113 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001113 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001113 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.310296 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6196.310296 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6196.310296 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6196.310296 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.305289 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6196.305289 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6196.305289 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6196.305289 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -366,24 +366,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 198172
system.cpu.icache.demand_mshr_misses::total 198172 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 198172 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 198172 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804804500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 804804500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804804500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 804804500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804804500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 804804500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804803500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 804803500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804803500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 804803500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804803500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 804803500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001105 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001105 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001105 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.141332 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.141332 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.136286 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.136286 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2529003 # number of replacements
system.cpu.dcache.tagsinuse 4087.729607 # Cycle average of tags in use
@ -410,14 +410,14 @@ system.cpu.dcache.demand_misses::cpu.data 3725145 # n
system.cpu.dcache.demand_misses::total 3725145 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3725145 # number of overall misses
system.cpu.dcache.overall_misses::total 3725145 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892922500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 29892922500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960185000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16960185000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 46853107500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 46853107500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 46853107500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 46853107500 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892904500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 29892904500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960182000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16960182000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 46853086500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 46853086500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 46853086500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 46853086500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 264751521 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 264751521 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
@ -434,14 +434,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009000
system.cpu.dcache.demand_miss_rate::total 0.009000 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009000 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009000 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.054087 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.054087 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.940033 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.940033 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12577.525841 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12577.525841 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.047567 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.047567 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.936922 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.936922 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12577.520204 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12577.520204 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -468,14 +468,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2723946
system.cpu.dcache.demand_mshr_misses::total 2723946 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2723946 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2723946 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993049600 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993049600 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994697002 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994697002 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987746602 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 25987746602 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987746602 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 25987746602 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993099500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993099500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994695000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994695000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987794500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 25987794500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987794500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 25987794500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006658 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006658 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006445 # mshr miss rate for WriteReq accesses
@ -484,24 +484,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006581
system.cpu.dcache.demand_mshr_miss_rate::total 0.006581 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006581 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006581 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.759555 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.759555 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.963852 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.963852 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.787865 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.787865 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.961769 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.961769 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 408687 # number of replacements
system.cpu.l2cache.tagsinuse 29306.187052 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 29306.187032 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3611934 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 441022 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 8.189918 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 209697302000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21100.579663 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 21100.579684 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 146.976593 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 8058.630796 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 8058.630755 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.643939 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.245930 # Average percentage of cache occupancy
@ -612,18 +612,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 3470
system.cpu.l2cache.overall_mshr_misses::cpu.data 431420 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 434890 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111424500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957189466 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068613966 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5872774499 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5872774499 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957207430 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068631930 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5878812896 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5878812896 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6488320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6488320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111424500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445509466 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 13556933966 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445527430 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 13556951930 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111424500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445509466 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 13556933966 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445527430 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 13556951930 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126143 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127588 # mshr miss rate for ReadReq accesses
@ -638,18 +638,18 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478885
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.171193 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32110.806916 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.201825 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.512168 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31004.637934 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31004.637934 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.282671 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.591770 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31036.516957 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31036.516957 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.245600 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.245600 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

18
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.141181 # Nu
sim_ticks 141180939500 # Number of ticks simulated
final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 88431 # Simulator instruction rate (inst/s)
host_op_rate 88431 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31316360 # Simulator tick rate (ticks/s)
host_mem_usage 225476 # Number of bytes of host memory used
host_seconds 4508.22 # Real time elapsed on the host
host_inst_rate 139974 # Simulator instruction rate (inst/s)
host_op_rate 139974 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49569488 # Simulator tick rate (ticks/s)
host_mem_usage 218836 # Number of bytes of host memory used
host_seconds 2848.14 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 49040.669856
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 90 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits
@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 52755.480984
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 85964000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 45078.133193 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 90.156266 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks

18
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.080354 # Nu
sim_ticks 80354154000 # Number of ticks simulated
final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 172564 # Simulator instruction rate (inst/s)
host_op_rate 172564 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36920064 # Simulator tick rate (ticks/s)
host_mem_usage 226504 # Number of bytes of host memory used
host_seconds 2176.44 # Real time elapsed on the host
host_inst_rate 221188 # Simulator instruction rate (inst/s)
host_op_rate 221188 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47323038 # Simulator tick rate (ticks/s)
host_mem_usage 219864 # Number of bytes of host memory used
host_seconds 1697.99 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory
@ -473,11 +473,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864
system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
@ -607,11 +607,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 38052.307692
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.466131 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40136.807818 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 38052.307692 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 3500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3500 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed

14
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.070882 # Nu
sim_ticks 70882487500 # Number of ticks simulated
final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 119635 # Simulator instruction rate (inst/s)
host_op_rate 152946 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31056895 # Simulator tick rate (ticks/s)
host_mem_usage 243232 # Number of bytes of host memory used
host_seconds 2282.34 # Real time elapsed on the host
host_inst_rate 146290 # Simulator instruction rate (inst/s)
host_op_rate 187023 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37976354 # Simulator tick rate (ticks/s)
host_mem_usage 236976 # Number of bytes of host memory used
host_seconds 1866.49 # Real time elapsed on the host
sim_insts 273048441 # Number of instructions simulated
sim_ops 349076165 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory
@ -497,11 +497,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 32843.594242
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 313000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 626 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19562.500000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 39.125000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks

22
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.644314 # Nu
sim_ticks 644314104000 # Number of ticks simulated
final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 127860 # Simulator instruction rate (inst/s)
host_op_rate 127860 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45189117 # Simulator tick rate (ticks/s)
host_mem_usage 230524 # Number of bytes of host memory used
host_seconds 14258.17 # Real time elapsed on the host
host_inst_rate 164548 # Simulator instruction rate (inst/s)
host_op_rate 164548 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 58155841 # Simulator tick rate (ticks/s)
host_mem_usage 223896 # Number of bytes of host memory used
host_seconds 11079.10 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory
@ -488,12 +488,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 33793.696324
system.cpu.dcache.demand_avg_miss_latency::total 33793.696324 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33793.696324 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 167000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 43 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7952.380952 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.904762 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 43 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 109393 # number of writebacks
@ -624,11 +624,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 35105.146381
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35724.010731 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35103.896073 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 35105.146381 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 105500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 211 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5275 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.550000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed

14
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.659244 # Nu
sim_ticks 659244465000 # Number of ticks simulated
final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 88407 # Simulator instruction rate (inst/s)
host_op_rate 120399 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42099861 # Simulator tick rate (ticks/s)
host_mem_usage 243836 # Number of bytes of host memory used
host_seconds 15659.07 # Real time elapsed on the host
host_inst_rate 153116 # Simulator instruction rate (inst/s)
host_op_rate 208523 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 72914339 # Simulator tick rate (ticks/s)
host_mem_usage 237584 # Number of bytes of host memory used
host_seconds 9041.36 # Real time elapsed on the host
sim_insts 1384375635 # Number of instructions simulated
sim_ops 1885330387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory
@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33900.527612
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks

18
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.046793 # Nu
sim_ticks 46793182500 # Number of ticks simulated
final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 59681 # Simulator instruction rate (inst/s)
host_op_rate 59681 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31612654 # Simulator tick rate (ticks/s)
host_mem_usage 227600 # Number of bytes of host memory used
host_seconds 1480.20 # Real time elapsed on the host
host_inst_rate 131801 # Simulator instruction rate (inst/s)
host_op_rate 131801 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 69813482 # Simulator tick rate (ticks/s)
host_mem_usage 220956 # Number of bytes of host memory used
host_seconds 670.26 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory
@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 15833.265655
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 1025000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 2050 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 10904.255319 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 21.808511 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits
@ -277,11 +277,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 50319.544394
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6260683500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 12521367 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50440.975999 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 100.881952 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks

22
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.021083 # Nu
sim_ticks 21083079000 # Number of ticks simulated
final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 162660 # Simulator instruction rate (inst/s)
host_op_rate 162660 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 43087037 # Simulator tick rate (ticks/s)
host_mem_usage 228624 # Number of bytes of host memory used
host_seconds 489.31 # Real time elapsed on the host
host_inst_rate 198104 # Simulator instruction rate (inst/s)
host_op_rate 198104 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 52475767 # Simulator tick rate (ticks/s)
host_mem_usage 221996 # Number of bytes of host memory used
host_seconds 401.77 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory
@ -480,12 +480,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 36802.050170
system.cpu.dcache.demand_avg_miss_latency::total 36802.050170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36802.050170 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 90500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 25500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 181 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 51 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6033.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.066667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 51 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 166256 # number of writebacks
@ -614,11 +614,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 39898.128604
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 39898.128604 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 75 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3409.090909 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6.818182 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed

14
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.023747 # Nu
sim_ticks 23747395500 # Number of ticks simulated
final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 107822 # Simulator instruction rate (inst/s)
host_op_rate 153002 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36101670 # Simulator tick rate (ticks/s)
host_mem_usage 242616 # Number of bytes of host memory used
host_seconds 657.79 # Real time elapsed on the host
host_inst_rate 142184 # Simulator instruction rate (inst/s)
host_op_rate 201762 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47606944 # Simulator tick rate (ticks/s)
host_mem_usage 237384 # Number of bytes of host memory used
host_seconds 498.82 # Real time elapsed on the host
sim_insts 70924309 # Number of instructions simulated
sim_ops 100643556 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory
@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33713.205595
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 197000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 394 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19700 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 39.400000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks

26
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.983203 # Nu
sim_ticks 983202553500 # Number of ticks simulated
final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 94547 # Simulator instruction rate (inst/s)
host_op_rate 94547 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51082649 # Simulator tick rate (ticks/s)
host_mem_usage 219392 # Number of bytes of host memory used
host_seconds 19247.29 # Real time elapsed on the host
host_inst_rate 119503 # Simulator instruction rate (inst/s)
host_op_rate 119503 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64565869 # Simulator tick rate (ticks/s)
host_mem_usage 212872 # Number of bytes of host memory used
host_seconds 15227.90 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 54537.140204
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 210 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 52.500000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits
@ -276,12 +276,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885
system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 52857 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 15792734 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.145450 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 75.764150 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks
@ -407,11 +407,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 540500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12869.047619 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 25.738095 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed

1054
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

1076
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

18
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.042001 # Nu
sim_ticks 42001440000 # Number of ticks simulated
final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 75192 # Simulator instruction rate (inst/s)
host_op_rate 75192 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34364250 # Simulator tick rate (ticks/s)
host_mem_usage 223172 # Number of bytes of host memory used
host_seconds 1222.24 # Real time elapsed on the host
host_inst_rate 134131 # Simulator instruction rate (inst/s)
host_op_rate 134131 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 61300636 # Simulator tick rate (ticks/s)
host_mem_usage 216520 # Number of bytes of host memory used
host_seconds 685.17 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 24215.288412
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits
@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 54653.714005
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks

18
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.023660 # Nu
sim_ticks 23659827000 # Number of ticks simulated
final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 114539 # Simulator instruction rate (inst/s)
host_op_rate 114539 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32192844 # Simulator tick rate (ticks/s)
host_mem_usage 224192 # Number of bytes of host memory used
host_seconds 734.94 # Real time elapsed on the host
host_inst_rate 188397 # Simulator instruction rate (inst/s)
host_op_rate 188397 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 52951506 # Simulator tick rate (ticks/s)
host_mem_usage 217548 # Number of bytes of host memory used
host_seconds 446.82 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory
@ -481,11 +481,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504
system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
@ -623,11 +623,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 36749.952390
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35341.806995 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38760.286639 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 36749.952390 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed

14
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.075929 # Nu
sim_ticks 75929256000 # Number of ticks simulated
final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 99785 # Simulator instruction rate (inst/s)
host_op_rate 109254 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 43964821 # Simulator tick rate (ticks/s)
host_mem_usage 238132 # Number of bytes of host memory used
host_seconds 1727.05 # Real time elapsed on the host
host_inst_rate 126863 # Simulator instruction rate (inst/s)
host_op_rate 138901 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 55895176 # Simulator tick rate (ticks/s)
host_mem_usage 231880 # Number of bytes of host memory used
host_seconds 1358.42 # Real time elapsed on the host
sim_insts 172333091 # Number of instructions simulated
sim_ops 188686573 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory
@ -497,11 +497,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 31016.696141
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 4500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks

940
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

452
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
View file

@ -1,132 +1,52 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.829332 # Number of seconds simulated
sim_ticks 1829332258000 # Number of ticks simulated
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 1.829331 # Number of seconds simulated
sim_ticks 1829330593000 # Number of ticks simulated
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2962809 # Simulator instruction rate (inst/s)
host_op_rate 2962806 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 90274916526 # Simulator tick rate (ticks/s)
host_mem_usage 302384 # Number of bytes of host memory used
host_seconds 20.26 # Real time elapsed on the host
sim_insts 60038305 # Number of instructions simulated
sim_ops 60038305 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory
host_inst_rate 2569577 # Simulator instruction rate (inst/s)
host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 78294086451 # Simulator tick rate (ticks/s)
host_mem_usage 295292 # Number of bytes of host memory used
host_seconds 23.37 # Real time elapsed on the host
sim_insts 60037737 # Number of instructions simulated
sim_ops 60037737 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory
system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory
system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
system.cpu.l2cache.replacements 992301 # number of replacements
system.cpu.l2cache.tagsinuse 65424.374305 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2433239 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1057464 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.301014 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits
system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses
system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks
system.cpu.l2cache.writebacks::total 74291 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s)
system.iocache.replacements 41686 # number of replacements
system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
system.iocache.tagsinuse 1.225558 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy
system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
@ -178,22 +98,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 9710427 # DTB read hits
system.cpu.dtb.read_hits 9710417 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.write_hits 6352498 # DTB write hits
system.cpu.dtb.write_hits 6352487 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.data_hits 16062925 # DTB hits
system.cpu.dtb.data_hits 16062904 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
system.cpu.itb.fetch_hits 4974648 # ITB hits
system.cpu.itb.fetch_hits 4974615 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
system.cpu.itb.fetch_accesses 4979621 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -206,51 +126,51 @@ system.cpu.itb.data_hits 0 # DT
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 3658664408 # number of cpu cycles simulated
system.cpu.numCycles 3658661078 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60038305 # Number of instructions committed
system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
system.cpu.committedInsts 60037737 # Number of instructions committed
system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
system.cpu.num_int_insts 55913521 # number of integer instructions
system.cpu.num_func_calls 1484174 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls
system.cpu.num_int_insts 55912968 # number of integer instructions
system.cpu.num_fp_insts 324460 # number of float instructions
system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read
system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
system.cpu.num_mem_refs 16115709 # number of memory refs
system.cpu.num_load_insts 9747513 # Number of load instructions
system.cpu.num_store_insts 6368196 # Number of store instructions
system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
system.cpu.num_mem_refs 16115688 # number of memory refs
system.cpu.num_load_insts 9747503 # Number of load instructions
system.cpu.num_store_insts 6368185 # Number of store instructions
system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles
system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles
system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
@ -289,7 +209,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
@ -298,20 +218,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192180 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1909
system.cpu.kern.mode_good::user 1738
system.cpu.kern.callpal::total 192177 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches
system.cpu.kern.mode_switch::user 1735 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1906
system.cpu.kern.mode_good::user 1735
system.cpu.kern.mode_good::idle 171
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
@ -344,33 +264,33 @@ system.tsunami.ethernet.totalRxOrn 0 # to
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.icache.replacements 919594 # number of replacements
system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use
system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks.
system.cpu.icache.replacements 919577 # number of replacements
system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use
system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits
system.cpu.icache.overall_hits::total 59129922 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses
system.cpu.icache.overall_misses::total 920221 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits
system.cpu.icache.overall_hits::total 59129371 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses
system.cpu.icache.overall_misses::total 920204 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
@ -386,55 +306,55 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2042702 # number of replacements
system.cpu.dcache.replacements 2042708 # number of replacements
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks.
system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits
system.cpu.dcache.overall_hits::total 13655992 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits
system.cpu.dcache.overall_hits::total 13655967 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses
system.cpu.dcache.overall_misses::total 2026069 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses
system.cpu.dcache.overall_misses::total 2026075 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
@ -450,5 +370,85 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
system.cpu.dcache.writebacks::total 833491 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 992297 # number of replacements
system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits
system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses
system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks
system.cpu.l2cache.writebacks::total 74287 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

2016
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

70
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.914421 # Nu
sim_ticks 1914420945000 # Number of ticks simulated
final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1284205 # Simulator instruction rate (inst/s)
host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 43773036105 # Simulator tick rate (ticks/s)
host_mem_usage 295308 # Number of bytes of host memory used
host_seconds 43.74 # Real time elapsed on the host
host_inst_rate 1299276 # Simulator instruction rate (inst/s)
host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44286723014 # Simulator tick rate (ticks/s)
host_mem_usage 288696 # Number of bytes of host memory used
host_seconds 43.23 # Real time elapsed on the host
sim_insts 56164879 # Number of instructions simulated
sim_ops 56164879 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989
system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@ -649,14 +649,14 @@ system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles
@ -681,14 +681,14 @@ system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

1880
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
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370
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
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@ -1,28 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.624688 # Number of seconds simulated
sim_ticks 2624688029000 # Number of ticks simulated
final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2624688000000 # Number of ticks simulated
final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 388710 # Simulator instruction rate (inst/s)
host_op_rate 494628 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16947208284 # Simulator tick rate (ticks/s)
host_mem_usage 385844 # Number of bytes of host memory used
host_seconds 154.87 # Real time elapsed on the host
host_inst_rate 509092 # Simulator instruction rate (inst/s)
host_op_rate 647812 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 22195691402 # Simulator tick rate (ticks/s)
host_mem_usage 379628 # Number of bytes of host memory used
host_seconds 118.25 # Real time elapsed on the host
sim_insts 60201138 # Number of instructions simulated
sim_ops 76605123 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
@ -60,7 +48,19 @@ system.physmem.bw_total::cpu.dtb.walker 122 # To
system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
@ -109,7 +109,7 @@ system.cpu.itb.inst_accesses 61499578 # IT
system.cpu.itb.hits 61495107 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61499578 # DTB accesses
system.cpu.numCycles 5249376058 # number of cpu cycles simulated
system.cpu.numCycles 5249376000 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60201138 # Number of instructions committed
@ -121,14 +121,14 @@ system.cpu.num_conditional_control_insts 7948064 # nu
system.cpu.num_int_insts 68872510 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read
system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written
system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27395681 # number of memory refs
system.cpu.num_load_insts 15660705 # Number of load instructions
system.cpu.num_store_insts 11734976 # Number of store instructions
system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles
system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles
system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles
system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles
system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.871278 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
@ -154,12 +154,12 @@ system.cpu.icache.demand_misses::cpu.inst 856390 # n
system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses
system.cpu.icache.overall_misses::total 856390 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses
@ -172,12 +172,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013926
system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -192,12 +192,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856390
system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852692500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9852692500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852692500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9852692500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852692500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9852692500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles
@ -208,58 +208,58 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926
system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.913065 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.913065 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 627202 # number of replacements
system.cpu.dcache.replacements 627203 # number of replacements
system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use
system.cpu.dcache.total_refs 23656924 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627714 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.687425 # Average number of references to valid blocks.
system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13196261 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13196261 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23170044 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23170044 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23170044 # number of overall hits
system.cpu.dcache.overall_hits::total 23170044 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368703 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368703 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits
system.cpu.dcache.overall_hits::total 23170043 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 619213 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619213 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619213 # number of overall misses
system.cpu.dcache.overall_misses::total 619213 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201080500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses
system.cpu.dcache.overall_misses::total 619214 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses)
@ -282,16 +282,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.026029
system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -302,32 +302,32 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks
system.cpu.dcache.writebacks::total 595968 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619213 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463674500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463674500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8475687500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8475687500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939362000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12939362000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939362000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12939362000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses
@ -338,16 +338,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029
system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.423056 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.423056 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33833.729192 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -356,16 +356,16 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 61913 # number of replacements
system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor
system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 6985.667758 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6014.098399 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
@ -375,8 +375,8 @@ system.cpu.l2cache.occ_percent::total 0.776184 # Av
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 370245 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226697 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
@ -386,13 +386,13 @@ system.cpu.l2cache.ReadExReq_hits::total 114435 # nu
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 484680 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1341132 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 484680 # number of overall hits
system.cpu.l2cache.overall_hits::total 1341132 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits
system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses
@ -414,28 +414,28 @@ system.cpu.l2cache.overall_misses::cpu.data 143034 #
system.cpu.l2cache.overall_misses::total 153657 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553303500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513115500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1066836500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6933900000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6933900000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 553303500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7447015500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 8000736500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7447598500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 8001378500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 553303500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7447015500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8000736500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 553362500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7447598500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8001378500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 380103 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1247178 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 380104 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1247179 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses)
@ -445,13 +445,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 247611
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 627714 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494789 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 627715 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494790 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 627714 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494789 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 627715 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494790 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses
@ -473,23 +473,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865
system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52124.682054 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52050.669507 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.082564 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52130.240226 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52051.886792 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52092.549192 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52065.687511 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52065.687511 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52069.975071 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52069.975071 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52068.805847 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52072.983984 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52068.805847 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -521,31 +521,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143034
system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425853000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394738000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820911000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115017000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115017000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5335717000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5335717000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425912000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394750500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820982500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115023000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115023000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5336288000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5336288000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425853000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5730455000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6156628000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425912000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5731038500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6157270500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425912000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5731038500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6157270500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763232500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028072500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856015000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856015000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198619247500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198884087500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses
@ -567,23 +567,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency

512
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
View file

@ -1,184 +1,76 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.112043 # Number of seconds simulated
sim_ticks 5112043255000 # Number of ticks simulated
final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 5.112041 # Number of seconds simulated
sim_ticks 5112040968500 # Number of ticks simulated
final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1011485 # Simulator instruction rate (inst/s)
host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 25877843451 # Simulator tick rate (ticks/s)
host_mem_usage 397304 # Number of bytes of host memory used
host_seconds 197.55 # Real time elapsed on the host
sim_insts 199813914 # Number of instructions simulated
sim_ops 409133298 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory
host_inst_rate 923075 # Simulator instruction rate (inst/s)
host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23616389220 # Simulator tick rate (ticks/s)
host_mem_usage 353316 # Number of bytes of host memory used
host_seconds 216.46 # Real time elapsed on the host
sim_insts 199810236 # Number of instructions simulated
sim_ops 409125915 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory
system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory
system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory
system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory
system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory
system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory
system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory
system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s)
system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory
system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory
system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s)
system.cpu.l2cache.replacements 106561 # number of replacements
system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits
system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses
system.cpu.l2cache.overall_misses::total 179910 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks
system.cpu.l2cache.writebacks::total 98533 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 47570 # number of replacements
system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
system.iocache.replacements 47569 # number of replacements
system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
system.iocache.overall_misses::total 47625 # number of overall misses
system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
system.iocache.overall_misses::total 47624 # number of overall misses
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
@ -200,7 +92,7 @@ system.iocache.writebacks::total 46667 # nu
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
@ -210,57 +102,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.numCycles 10224086531 # number of cpu cycles simulated
system.cpu.numCycles 10224081960 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 199813914 # Number of instructions committed
system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses
system.cpu.committedInsts 199810236 # Number of instructions committed
system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls
system.cpu.num_int_insts 374297264 # number of integer instructions
system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
system.cpu.num_int_insts 374289906 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read
system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written
system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read
system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 35626517 # number of memory refs
system.cpu.num_load_insts 27217782 # Number of load instructions
system.cpu.num_store_insts 8408735 # Number of store instructions
system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles
system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles
system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
system.cpu.num_mem_refs 35624588 # number of memory refs
system.cpu.num_load_insts 27216588 # Number of load instructions
system.cpu.num_store_insts 8408000 # Number of store instructions
system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles
system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles
system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.replacements 790793 # number of replacements
system.cpu.icache.replacements 790732 # number of replacements
system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks.
system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits
system.cpu.icache.overall_hits::total 243365779 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses
system.cpu.icache.overall_misses::total 791312 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits
system.cpu.icache.overall_hits::total 243360722 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses
system.cpu.icache.overall_misses::total 791251 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
@ -277,14 +169,14 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 3335 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use
system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
@ -324,39 +216,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu
system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 7598 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses
system.cpu.dtb_walker_cache.replacements 7597 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -368,39 +260,39 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu
system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1621273 # number of replacements
system.cpu.dcache.replacements 1621135 # number of replacements
system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use
system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks.
system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits
system.cpu.dcache.overall_hits::total 20139960 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits
system.cpu.dcache.overall_hits::total 20138167 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses
system.cpu.dcache.overall_misses::total 1623919 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
@ -417,8 +309,116 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks
system.cpu.dcache.writebacks::total 1534981 # number of writebacks
system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks
system.cpu.dcache.writebacks::total 1534848 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 106558 # number of replacements
system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits
system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses
system.cpu.l2cache.overall_misses::total 179909 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks
system.cpu.l2cache.writebacks::total 98530 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

162
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 5.187896 # Nu
sim_ticks 5187896410000 # Number of ticks simulated
final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 834857 # Simulator instruction rate (inst/s)
host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33766110220 # Simulator tick rate (ticks/s)
host_mem_usage 354356 # Number of bytes of host memory used
host_seconds 153.64 # Real time elapsed on the host
host_inst_rate 812782 # Simulator instruction rate (inst/s)
host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32873266023 # Simulator tick rate (ticks/s)
host_mem_usage 347504 # Number of bytes of host memory used
host_seconds 157.82 # Real time elapsed on the host
sim_insts 128269216 # Number of instructions simulated
sim_ops 247270559 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory
@ -59,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558
system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
system.iocache.overall_misses::total 47558 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
@ -83,19 +83,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@ -109,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558
system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86510932 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 86510932 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266723160 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8266723160 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8353234092 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
@ -125,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103235.002387 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 103235.002387 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176941.848459 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176941.848459 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@ -437,14 +437,14 @@ system.cpu.dcache.demand_misses::cpu.data 1621067 # n
system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses
system.cpu.dcache.overall_misses::total 1621067 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175237000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18175237000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 27078679500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 27078679500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 27078679500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 27078679500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses)
@ -461,14 +461,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074870
system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16704.232151 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -487,20 +487,20 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1621067
system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23836545500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses
@ -509,14 +509,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870
system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -672,21 +672,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922
system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144100000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661629500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677130500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6194660000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677130500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6194660000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles
@ -710,21 +710,21 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

14
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
sim_ticks 21628500 # Number of ticks simulated
final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 48865 # Simulator instruction rate (inst/s)
host_op_rate 48859 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 165354272 # Simulator tick rate (ticks/s)
host_mem_usage 218640 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_inst_rate 34038 # Simulator instruction rate (inst/s)
host_op_rate 34033 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 115179622 # Simulator tick rate (ticks/s)
host_mem_usage 212112 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56590.517241
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits

18
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
sim_ticks 20184000 # Number of ticks simulated
final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50290 # Simulator instruction rate (inst/s)
host_op_rate 50282 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 174536927 # Simulator tick rate (ticks/s)
host_mem_usage 219492 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_inst_rate 91753 # Simulator instruction rate (inst/s)
host_op_rate 91718 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 318298211 # Simulator tick rate (ticks/s)
host_mem_usage 212944 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
@ -160,11 +160,11 @@ system.cpu.icache.demand_avg_miss_latency::total 56098.837209
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits
@ -256,11 +256,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 57663.385827
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits

18
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
sim_ticks 18570500 # Number of ticks simulated
final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 42410 # Simulator instruction rate (inst/s)
host_op_rate 42404 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 147804999 # Simulator tick rate (ticks/s)
host_mem_usage 221464 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_inst_rate 78205 # Simulator instruction rate (inst/s)
host_op_rate 78177 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 272440141 # Simulator tick rate (ticks/s)
host_mem_usage 214124 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55220
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 218 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 36333.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 72.666667 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits
@ -238,11 +238,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 55992.711370
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits

14
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu
sim_ticks 14818500 # Number of ticks simulated
final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 71701 # Simulator instruction rate (inst/s)
host_op_rate 71694 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 83350191 # Simulator tick rate (ticks/s)
host_mem_usage 220256 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
host_inst_rate 95139 # Simulator instruction rate (inst/s)
host_op_rate 95123 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 110579898 # Simulator tick rate (ticks/s)
host_mem_usage 213740 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
@ -736,11 +736,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 49000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4083.333333 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8.166667 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed

18
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
sim_ticks 25317500 # Number of ticks simulated
final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 47783 # Simulator instruction rate (inst/s)
host_op_rate 47781 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 79779918 # Simulator tick rate (ticks/s)
host_mem_usage 220364 # Number of bytes of host memory used
host_seconds 0.32 # Real time elapsed on the host
host_inst_rate 84248 # Simulator instruction rate (inst/s)
host_op_rate 84237 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 140641450 # Simulator tick rate (ticks/s)
host_mem_usage 214032 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 54837.398374
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 131 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
@ -242,11 +242,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56182.451253
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits

3847
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
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1925
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
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2842
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
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