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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson d52adc4eb6 Stats: Update stats for cache timings in cycles 
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
2012-10-15 08:12:21 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.454149 # Number of seconds simulated
sim_ticks 454149445000 # Number of ticks simulated
final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 251011 # Simulator instruction rate (inst/s)
host_op_rate 280022 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 73805166 # Simulator tick rate (ticks/s)
host_mem_usage 228580 # Number of bytes of host memory used
host_seconds 6153.36 # Real time elapsed on the host
sim_insts 1544563043 # Number of instructions simulated
sim_ops 1723073855 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory
system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory
system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 908298891 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed
system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued
system.cpu.iq.rate 2.213059 # Inst issue rate
system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 81 # number of nop insts executed
system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed
system.cpu.iew.exec_branches 237537296 # Number of branches executed
system.cpu.iew.exec_stores 190660380 # Number of stores executed
system.cpu.iew.exec_rate 2.180837 # Inst execution rate
system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1293399468 # num instructions producing a value
system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563061 # Number of instructions committed
system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773822 # Number of memory references committed
system.cpu.commit.loads 485926773 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462430 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2910643265 # The number of ROB reads
system.cpu.rob.rob_writes 4428322151 # The number of ROB writes
system.cpu.timesIdled 678500 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 6477371 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563043 # Number of Instructions Simulated
system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated
system.cpu.cpi 0.588062 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.588062 # CPI: Total CPI of All Threads
system.cpu.ipc 1.700501 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.700501 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9924419417 # number of integer regfile reads
system.cpu.int_regfile_writes 1932830839 # number of integer regfile writes
system.cpu.fp_regfile_reads 180 # number of floating regfile reads
system.cpu.fp_regfile_writes 196 # number of floating regfile writes
system.cpu.misc_regfile_reads 2885680755 # number of misc regfile reads
system.cpu.misc_regfile_writes 132 # number of misc regfile writes
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.tagsinuse 628.471657 # Cycle average of tags in use
system.cpu.icache.total_refs 282187157 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 359474.085350 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 628.471657 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.306871 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.306871 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 282187157 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 282187157 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 282187157 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 282187157 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 282187157 # number of overall hits
system.cpu.icache.overall_hits::total 282187157 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses
system.cpu.icache.overall_misses::total 1154 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39417000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39417000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39417000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39417000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39417000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39417000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 282188311 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 282188311 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 282188311 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 282188311 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 282188311 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 282188311 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34156.845754 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34156.845754 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34156.845754 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34156.845754 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 369 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 369 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 369 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 369 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28514500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 28514500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28514500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 28514500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28514500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 28514500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36324.203822 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36324.203822 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9616145 # number of replacements
system.cpu.dcache.tagsinuse 4087.425286 # Cycle average of tags in use
system.cpu.dcache.total_refs 659915514 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9620241 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.596568 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.425286 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 492504705 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 492504705 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167410650 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167410650 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 659915355 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 659915355 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 659915355 # number of overall hits
system.cpu.dcache.overall_hits::total 659915355 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 10104493 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 10104493 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5175397 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5175397 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 15279890 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 15279890 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 15279890 # number of overall misses
system.cpu.dcache.overall_misses::total 15279890 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151975224500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 151975224500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 119867822584 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 119867822584 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 111500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 111500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 271843047084 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 271843047084 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 271843047084 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 271843047084 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 502609198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 502609198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 675195245 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 675195245 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 675195245 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 675195245 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020104 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.020104 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029987 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029987 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.022630 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.022630 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.022630 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.022630 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15040.361204 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15040.361204 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23161.087465 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23161.087465 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17790.903409 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17790.903409 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 547911 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 306 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 59951 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.139314 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3473179 # number of writebacks
system.cpu.dcache.writebacks::total 3473179 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2378385 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2378385 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281264 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3281264 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 5659649 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 5659649 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 5659649 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 5659649 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726108 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7726108 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894133 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1894133 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9620241 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9620241 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9620241 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9620241 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75134366500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75134366500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39443717607 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 39443717607 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114578084107 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 114578084107 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114578084107 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 114578084107 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015372 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015372 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014248 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014248 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9724.736763 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9724.736763 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20824.154168 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20824.154168 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2426778 # number of replacements
system.cpu.l2cache.tagsinuse 31133.069432 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8743063 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2456493 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.559165 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 77443387000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14066.378954 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 15.908545 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 17050.781934 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.429272 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000485 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.520349 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.950106 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6115252 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6115280 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3473179 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3473179 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1063326 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1063326 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7178578 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7178606 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7178578 # number of overall hits
system.cpu.l2cache.overall_hits::total 7178606 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1610856 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1611613 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 830807 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 830807 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2441663 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2442420 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2441663 # number of overall misses
system.cpu.l2cache.overall_misses::total 2442420 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27670500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59328864000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 59356534500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35694611500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 35694611500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27670500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 95023475500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 95051146000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27670500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 95023475500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 95051146000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 785 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7726108 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7726893 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3473179 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3473179 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894133 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1894133 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 785 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9620241 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9621026 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 785 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9620241 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9621026 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964331 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208495 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.208572 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438621 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.438621 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964331 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.253805 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.253863 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964331 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.253805 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.253863 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36552.840159 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36830.644080 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36830.513591 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42963.782804 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42963.782804 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 38916.789905 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 38916.789905 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 229442 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 20875 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.991234 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1123907 # number of writebacks
system.cpu.l2cache.writebacks::total 1123907 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 754 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1610849 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1611603 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830807 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 830807 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 754 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2441656 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2442410 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 754 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2441656 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2442410 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25220000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54195045500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54220265500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33065264000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33065264000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25220000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87260309500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 87285529500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25220000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87260309500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 87285529500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208494 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208571 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438621 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438621 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.253862 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.253862 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33448.275862 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33643.777598 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33643.686131 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39798.971362 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39798.971362 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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