d52adc4eb6
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
447 lines
51 KiB
Text
447 lines
51 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.000022 # Number of seconds simulated
|
|
sim_ticks 21628500 # Number of ticks simulated
|
|
final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 34038 # Simulator instruction rate (inst/s)
|
|
host_op_rate 34033 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 115179622 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 212112 # Number of bytes of host memory used
|
|
host_seconds 0.19 # Real time elapsed on the host
|
|
sim_insts 6390 # Number of instructions simulated
|
|
sim_ops 6390 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
|
|
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 1184 # DTB read hits
|
|
system.cpu.dtb.read_misses 7 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 1191 # DTB read accesses
|
|
system.cpu.dtb.write_hits 900 # DTB write hits
|
|
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 903 # DTB write accesses
|
|
system.cpu.dtb.data_hits 2084 # DTB hits
|
|
system.cpu.dtb.data_misses 10 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 2094 # DTB accesses
|
|
system.cpu.itb.fetch_hits 908 # ITB hits
|
|
system.cpu.itb.fetch_misses 17 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 925 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
system.cpu.numCycles 43258 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.branch_predictor.lookups 1606 # Number of BP lookups
|
|
system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted
|
|
system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect
|
|
system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups
|
|
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
|
|
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
|
|
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage
|
|
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
|
|
system.cpu.branch_predictor.predictedNotTaken 1142 # Number of Branches Predicted As Not Taken (False).
|
|
system.cpu.regfile_manager.intRegFileReads 5205 # Number of Reads from Int. Register File
|
|
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
|
|
system.cpu.regfile_manager.intRegFileAccesses 9772 # Total Accesses (Read+Write) to the Int. Register File
|
|
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
|
|
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
|
|
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
|
|
system.cpu.regfile_manager.regForwards 2961 # Number of Registers Read Through Forwarding Logic
|
|
system.cpu.agen_unit.agens 2181 # Number of Address Generations
|
|
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts
|
|
system.cpu.execution_unit.executions 4463 # Number of Instructions Executed.
|
|
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
|
system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 7403 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 17.113597 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 1183 # Number of Load instructions committed
|
|
system.cpu.comStores 865 # Number of Store instructions committed
|
|
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
|
system.cpu.comNops 17 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 3254 # Number of Integer instructions committed
|
|
system.cpu.comFloats 2 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 6390 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 557 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 557 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 351 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 614 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1700 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1700 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1700 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1700 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 251 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 251 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 348 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 348 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290173 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.290173 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 178 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 178 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 180 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|