d52adc4eb6
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
1038 lines
122 KiB
Plaintext
1038 lines
122 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.133289 # Number of seconds simulated
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sim_ticks 5133289198000 # Number of ticks simulated
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final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 170996 # Simulator instruction rate (inst/s)
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host_op_rate 338013 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2151657827 # Simulator tick rate (ticks/s)
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host_mem_usage 361992 # Number of bytes of host memory used
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host_seconds 2385.74 # Real time elapsed on the host
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sim_insts 407952579 # Number of instructions simulated
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sim_ops 806410876 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory
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system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory
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system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory
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system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory
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system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s)
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system.iocache.replacements 47577 # number of replacements
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system.iocache.tagsinuse 0.116486 # Cycle average of tags in use
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit.
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system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor
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system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy
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system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy
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system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
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system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
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system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
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system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
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system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
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system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
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system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
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system.iocache.overall_misses::total 47632 # number of overall misses
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system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles
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system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles
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system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles
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system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles
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system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles
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system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles
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system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles
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system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles
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system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
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system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
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system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
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system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
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system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
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system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
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system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
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system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
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system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency
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system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency
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system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency
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system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency
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system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency
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system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency
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system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency
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system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency
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system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.writebacks::writebacks 46667 # number of writebacks
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system.iocache.writebacks::total 46667 # number of writebacks
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system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
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system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
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system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
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system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
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system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
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system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
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system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles
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system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles
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system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles
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system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles
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system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
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system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
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system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
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system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
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system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency
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system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency
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system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency
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system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
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system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
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system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
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system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
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system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
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system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
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system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
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system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
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system.cpu.numCycles 448600431 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing
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system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb
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system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed
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system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 154456 0.06% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued
|
|
system.cpu.iq.rate 1.837676 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 725973 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 11358 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 710415 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1333170 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 17608498 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 26834247 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 83283502 # Number of branches executed
|
|
system.cpu.iew.exec_stores 9225749 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.833188 # Inst execution rate
|
|
system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 819707466 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 640500741 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1046431080 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1052864 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1189777 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 255221218 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 3.159655 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.852368 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 11920052 4.67% 37.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4017826 1.57% 38.85% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 74972744 29.38% 68.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 2476508 0.97% 69.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1494072 0.59% 69.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1000652 0.39% 70.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 70934036 27.79% 97.96% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5202298 2.04% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 255221218 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 407952579 # Number of instructions committed
|
|
system.cpu.commit.committedOps 806410876 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 22397454 # Number of memory references committed
|
|
system.cpu.commit.loads 13980397 # Number of loads committed
|
|
system.cpu.commit.membars 473477 # Number of memory barriers committed
|
|
system.cpu.commit.branches 82193415 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 735346024 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 5202298 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 1080968615 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1665910047 # The number of ROB writes
|
|
system.cpu.timesIdled 1218526 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 189561046 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 9817975385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 407952579 # Number of Instructions Simulated
|
|
system.cpu.committedOps 806410876 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated
|
|
system.cpu.cpi 1.099639 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.909390 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.909390 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1508324148 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 977861305 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 65 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 265169626 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 402500 # number of misc regfile writes
|
|
system.cpu.icache.replacements 1068646 # number of replacements
|
|
system.cpu.icache.tagsinuse 510.896112 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 8129454 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1069158 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 7.603604 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 510.896112 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.997844 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.997844 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 8129454 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 8129454 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 8129454 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 8129454 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 8129454 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 8129454 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1139394 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1139394 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1139394 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1139394 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1139394 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1139394 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15246811490 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 15246811490 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 15246811490 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 15246811490 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 15246811490 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 15246811490 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 9268848 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 9268848 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 9268848 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 9268848 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 9268848 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 9268848 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122927 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.122927 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.122927 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.122927 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.122927 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.122927 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13381.509373 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13381.509373 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13381.509373 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13381.509373 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 5114 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 19.519084 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68044 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 68044 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 68044 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 68044 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 68044 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 68044 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071350 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1071350 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1071350 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1071350 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1071350 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1071350 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12542463990 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12542463990 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12542463990 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12542463990 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12542463990 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12542463990 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115586 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.115586 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.115586 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11707.158249 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11707.158249 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.itb_walker_cache.replacements 9707 # number of replacements
|
|
system.cpu.itb_walker_cache.tagsinuse 6.043772 # Cycle average of tags in use
|
|
system.cpu.itb_walker_cache.total_refs 27693 # Total number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.sampled_refs 9719 # Sample count of references to valid blocks.
|
|
system.cpu.itb_walker_cache.avg_refs 2.849367 # Average number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.warmup_cycle 5100157918000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.043772 # Average occupied blocks per requestor
|
|
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377736 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.occ_percent::total 0.377736 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27843 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 27843 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27846 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.demand_hits::total 27846 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27846 # number of overall hits
|
|
system.cpu.itb_walker_cache.overall_hits::total 27846 # number of overall hits
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10592 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 10592 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10592 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.demand_misses::total 10592 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10592 # number of overall misses
|
|
system.cpu.itb_walker_cache.overall_misses::total 10592 # number of overall misses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116124000 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116124000 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116124000 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::total 116124000 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116124000 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::total 116124000 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 38435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38438 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.demand_accesses::total 38438 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38438 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::total 38438 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275582 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275582 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275561 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.275561 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275561 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.275561 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10963.368580 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10963.368580 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10963.368580 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10963.368580 # average overall miss latency
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 1540 # number of writebacks
|
|
system.cpu.itb_walker_cache.writebacks::total 1540 # number of writebacks
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10592 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10592 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10592 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::total 10592 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10592 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::total 10592 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94940000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94940000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94940000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94940000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94940000 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94940000 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275582 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275582 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275561 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275561 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8963.368580 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dtb_walker_cache.replacements 107637 # number of replacements
|
|
system.cpu.dtb_walker_cache.tagsinuse 11.991971 # Cycle average of tags in use
|
|
system.cpu.dtb_walker_cache.total_refs 139374 # Total number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.sampled_refs 107653 # Sample count of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.avg_refs 1.294660 # Average number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.991971 # Average occupied blocks per requestor
|
|
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749498 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.occ_percent::total 0.749498 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139374 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 139374 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139374 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.demand_hits::total 139374 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139374 # number of overall hits
|
|
system.cpu.dtb_walker_cache.overall_hits::total 139374 # number of overall hits
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108671 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 108671 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108671 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.demand_misses::total 108671 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108671 # number of overall misses
|
|
system.cpu.dtb_walker_cache.overall_misses::total 108671 # number of overall misses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1362724500 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1362724500 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1362724500 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::total 1362724500 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1362724500 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::total 1362724500 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248045 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 248045 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248045 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 248045 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248045 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.438110 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.438110 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.438110 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.438110 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.438110 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.438110 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12539.909451 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12539.909451 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 32720 # number of writebacks
|
|
system.cpu.dtb_walker_cache.writebacks::total 32720 # number of writebacks
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108671 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108671 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108671 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::total 108671 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108671 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::total 108671 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1145382500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1145382500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1145382500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.438110 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.438110 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.438110 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10539.909451 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1673658 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.992942 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 19220297 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1674170 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 11.480493 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 32836000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.992942 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 11126575 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 11126575 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8088656 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 8088656 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 19215231 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 19215231 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 19215231 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 19215231 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2269640 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2269640 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 319173 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 319173 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2588813 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2588813 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2588813 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2588813 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31726602500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 31726602500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9823121491 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9823121491 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 41549723991 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 41549723991 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 41549723991 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 41549723991 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13396215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 13396215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8407829 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 8407829 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 21804044 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 21804044 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 21804044 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 21804044 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169424 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.169424 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037961 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037961 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.118731 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.118731 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.118731 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.118731 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.693758 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.693758 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30776.793435 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 30776.793435 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 16049.720081 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 16049.720081 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 366322 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 42954 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.528240 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1573837 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1573837 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884183 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 884183 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26057 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 26057 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 910240 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 910240 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 910240 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 910240 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385457 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1385457 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293116 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 293116 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1678573 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1678573 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1678573 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1678573 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17084942000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17084942000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8988357491 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8988357491 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26073299491 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 26073299491 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26073299491 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26073299491 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296962500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296962500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470375500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470375500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767338000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767338000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103422 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103422 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034862 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034862 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.076984 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.076984 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12331.629202 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12331.629202 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30664.847675 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30664.847675 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 113860 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 64830.724160 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3973813 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 177772 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 22.353425 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 50128.354504 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 11.733619 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.162766 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 3228.532252 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 11461.941019 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.764898 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000179 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.049263 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.174895 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.989238 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101628 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7965 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1052257 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1347205 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2509055 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1608097 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1608097 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 328 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 328 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 156120 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 156120 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 101628 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 7965 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1052257 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1503325 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2665175 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 101628 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 7965 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1052257 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1503325 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2665175 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 39 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 16857 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 37156 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 54059 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3590 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 3590 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133151 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133151 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 39 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 16857 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 170307 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 187210 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 39 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 16857 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 170307 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 187210 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2058500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 371500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 895435000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1995543998 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2893408998 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 37772999 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 37772999 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6939920000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6939920000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2058500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 371500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 895435000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8935463998 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 9833328998 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2058500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 371500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 895435000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8935463998 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 9833328998 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101667 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7972 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1069114 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1384361 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2563114 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1608097 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1608097 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3918 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 3918 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 289271 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 289271 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101667 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 7972 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1069114 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1673632 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2852385 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101667 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 7972 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1069114 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1673632 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2852385 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000384 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000878 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015767 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026840 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.021091 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916284 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916284 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460298 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.460298 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000384 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000878 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015767 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.101759 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.065633 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000384 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000878 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015767 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.101759 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.065633 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52782.051282 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 53071.428571 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53119.475589 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53707.180482 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53523.169093 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 10521.726741 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 10521.726741 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52120.675023 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52120.675023 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52782.051282 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 53071.428571 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53119.475589 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52466.804054 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52525.661012 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52782.051282 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 53071.428571 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53119.475589 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52466.804054 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52525.661012 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 102571 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 102571 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 39 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16855 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 37154 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 54055 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3590 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3590 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133151 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133151 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 39 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16855 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 170305 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 187206 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 39 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16855 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 170305 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 187206 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1582000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 689639500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1541128498 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2232636998 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 144031499 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 144031499 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5333340000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5333340000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1582000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689639500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6874468498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 7565976998 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1582000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689639500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6874468498 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 7565976998 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185727000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185727000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304773500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304773500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91490500500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91490500500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026838 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021090 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916284 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916284 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460298 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460298 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.065631 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.065631 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40916.018985 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41479.477257 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41303.061659 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40120.194708 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40120.194708 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40054.824973 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40054.824973 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|