d52adc4eb6
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
460 lines
52 KiB
Text
460 lines
52 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.141181 # Number of seconds simulated
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sim_ticks 141180939500 # Number of ticks simulated
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final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 139974 # Simulator instruction rate (inst/s)
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host_op_rate 139974 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 49569488 # Simulator tick rate (ticks/s)
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host_mem_usage 218836 # Number of bytes of host memory used
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host_seconds 2848.14 # Real time elapsed on the host
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sim_insts 398664595 # Number of instructions simulated
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sim_ops 398664595 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
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system.physmem.bytes_read::total 468608 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 94755019 # DTB read hits
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system.cpu.dtb.read_misses 21 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 94755040 # DTB read accesses
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system.cpu.dtb.write_hits 73522102 # DTB write hits
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system.cpu.dtb.write_misses 35 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 73522137 # DTB write accesses
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system.cpu.dtb.data_hits 168277121 # DTB hits
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system.cpu.dtb.data_misses 56 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 168277177 # DTB accesses
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system.cpu.itb.fetch_hits 49111833 # ITB hits
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system.cpu.itb.fetch_misses 88782 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 49200615 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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system.cpu.numCycles 282361880 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 168700458 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed.
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system.cpu.activity 95.223370 # Percentage of cycles cpu is active
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system.cpu.comLoads 94754489 # Number of Load instructions committed
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system.cpu.comStores 73520729 # Number of Store instructions committed
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system.cpu.comBranches 44587532 # Number of Branches instructions committed
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system.cpu.comNops 23089775 # Number of Nop instructions committed
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system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
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system.cpu.comInts 112239074 # Number of Integer instructions committed
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system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
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system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
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system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 1974 # number of replacements
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system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use
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system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits
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system.cpu.icache.overall_hits::total 49107443 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses
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system.cpu.icache.overall_misses::total 4389 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49040.669856 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 49040.669856 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 49040.669856 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 90 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_hits::total 488 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::cpu.inst 488 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_hits::total 488 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 488 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::total 488 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190519000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 190519000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190519000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 190519000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190519000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 190519000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.502948 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48838.502948 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 764 # number of replacements
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system.cpu.dcache.tagsinuse 3284.744401 # Cycle average of tags in use
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system.cpu.dcache.total_refs 168261808 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 40525.483622 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 3284.744401 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.801940 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.801940 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 73508547 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 73508547 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 168261808 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 168261808 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 168261808 # number of overall hits
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system.cpu.dcache.overall_hits::total 168261808 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 12182 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 12182 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 13410 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 13410 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 13410 # number of overall misses
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system.cpu.dcache.overall_misses::total 13410 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 65498000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 65498000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 641953000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 641953000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 707451000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 707451000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 707451000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 707451000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000166 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000166 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53337.133550 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 53337.133550 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52696.847808 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 52696.847808 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 90.156266 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8980 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 8980 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 9258 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 9258 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 9258 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 9258 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48495500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48495500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 175965000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 175965000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224460500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 224460500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224460500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 224460500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51047.894737 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51047.894737 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54954.715803 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54954.715803 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 3900.293758 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 370.502388 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2902.254610 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 627.536760 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.088570 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.119028 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 731 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3353 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7322 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7322 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 181079500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 181079500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 218267500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 399347000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 54540.699262 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4177 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7322 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 140250000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176303500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133849000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140250000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 310152500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 310152500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|