d52adc4eb6
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2357 lines
269 KiB
Plaintext
2357 lines
269 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000110 # Number of seconds simulated
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sim_ticks 109894000 # Number of ticks simulated
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final_tick 109894000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 161995 # Simulator instruction rate (inst/s)
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host_op_rate 161994 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 16590549 # Simulator tick rate (ticks/s)
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host_mem_usage 228988 # Number of bytes of host memory used
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host_seconds 6.62 # Real time elapsed on the host
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sim_insts 1073027 # Number of instructions simulated
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sim_ops 1073027 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 42880 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 256 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 670 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 209656578 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 97839736 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 51249386 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 11647588 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 2329518 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 7570932 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 2329518 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 7570932 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 390194187 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 209656578 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 51249386 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 2329518 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 2329518 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 265564999 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 209656578 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 97839736 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 51249386 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 11647588 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 2329518 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 7570932 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 2329518 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 7570932 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 390194187 # Total bandwidth to/from this memory (bytes/s)
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system.cpu0.workload.num_syscalls 89 # Number of system calls
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system.cpu0.numCycles 219789 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.BPredUnit.lookups 85747 # Number of BP lookups
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system.cpu0.BPredUnit.condPredicted 83485 # Number of conditional branches predicted
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system.cpu0.BPredUnit.condIncorrect 1265 # Number of conditional branches incorrect
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system.cpu0.BPredUnit.BTBLookups 83551 # Number of BTB lookups
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system.cpu0.BPredUnit.BTBHits 81101 # Number of BTB hits
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system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu0.BPredUnit.usedRAS 507 # Number of times the RAS was used to get a target.
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system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
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system.cpu0.fetch.icacheStallCycles 17217 # Number of cycles fetch is stalled on an Icache miss
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system.cpu0.fetch.Insts 509162 # Number of instructions fetch has processed
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system.cpu0.fetch.Branches 85747 # Number of branches that fetch encountered
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system.cpu0.fetch.predictedBranches 81608 # Number of branches that fetch has predicted taken
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system.cpu0.fetch.Cycles 167267 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu0.fetch.SquashCycles 3854 # Number of cycles fetch has spent squashing
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system.cpu0.fetch.BlockedCycles 13783 # Number of cycles fetch has spent blocked
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system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu0.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps
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system.cpu0.fetch.CacheLines 6029 # Number of cache lines fetched
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system.cpu0.fetch.IcacheSquashes 502 # Number of outstanding Icache misses that were squashed
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system.cpu0.fetch.rateDist::samples 202015 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::mean 2.520417 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::stdev 2.209670 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::0 34748 17.20% 17.20% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::1 82895 41.03% 58.23% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::2 589 0.29% 58.53% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::3 956 0.47% 59.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::4 519 0.26% 59.26% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::5 78871 39.04% 98.30% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::6 675 0.33% 98.63% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::7 356 0.18% 98.81% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::8 2406 1.19% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::total 202015 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.branchRate 0.390133 # Number of branch fetches per cycle
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system.cpu0.fetch.rate 2.316595 # Number of inst fetches per cycle
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system.cpu0.decode.IdleCycles 17805 # Number of cycles decode is idle
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system.cpu0.decode.BlockedCycles 15234 # Number of cycles decode is blocked
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system.cpu0.decode.RunCycles 166234 # Number of cycles decode is running
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system.cpu0.decode.UnblockCycles 301 # Number of cycles decode is unblocking
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system.cpu0.decode.SquashCycles 2441 # Number of cycles decode is squashing
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system.cpu0.decode.DecodedInsts 506087 # Number of instructions handled by decode
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system.cpu0.rename.SquashCycles 2441 # Number of cycles rename is squashing
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system.cpu0.rename.IdleCycles 18480 # Number of cycles rename is idle
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system.cpu0.rename.BlockCycles 1523 # Number of cycles rename is blocking
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system.cpu0.rename.serializeStallCycles 13039 # count of cycles rename stalled for serializing inst
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system.cpu0.rename.RunCycles 165885 # Number of cycles rename is running
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system.cpu0.rename.UnblockCycles 647 # Number of cycles rename is unblocking
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system.cpu0.rename.RenamedInsts 502881 # Number of instructions processed by rename
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system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full
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system.cpu0.rename.RenamedOperands 343651 # Number of destination operands rename has renamed
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system.cpu0.rename.RenameLookups 1003098 # Number of register rename lookups that rename has made
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system.cpu0.rename.int_rename_lookups 1003098 # Number of integer rename lookups
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system.cpu0.rename.CommittedMaps 330631 # Number of HB maps that are committed
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system.cpu0.rename.UndoneMaps 13020 # Number of HB maps that are undone due to squashing
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system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed
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system.cpu0.rename.tempSerializingInsts 932 # count of temporary serializing insts renamed
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system.cpu0.rename.skidInsts 3938 # count of insts added to the skid buffer
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system.cpu0.memDep0.insertedLoads 161147 # Number of loads inserted to the mem dependence unit.
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system.cpu0.memDep0.insertedStores 81377 # Number of stores inserted to the mem dependence unit.
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system.cpu0.memDep0.conflictingLoads 78673 # Number of conflicting loads.
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system.cpu0.memDep0.conflictingStores 78441 # Number of conflicting stores.
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system.cpu0.iq.iqInstsAdded 420405 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu0.iq.iqNonSpecInstsAdded 949 # Number of non-speculative instructions added to the IQ
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system.cpu0.iq.iqInstsIssued 417702 # Number of instructions issued
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system.cpu0.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued
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system.cpu0.iq.iqSquashedInstsExamined 10651 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu0.iq.iqSquashedOperandsExamined 9804 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.iqSquashedNonSpecRemoved 390 # Number of squashed non-spec instructions that were removed
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system.cpu0.iq.issued_per_cycle::samples 202015 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::mean 2.067678 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::stdev 1.086169 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::0 33785 16.72% 16.72% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::1 5274 2.61% 19.33% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::2 80485 39.84% 59.18% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::3 79928 39.57% 98.74% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::4 1527 0.76% 99.50% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::5 645 0.32% 99.82% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::6 270 0.13% 99.95% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::8 14 0.01% 100.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::total 202015 # Number of insts issued each cycle
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system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IntAlu 46 19.74% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IntMult 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.74% # attempts to use FU when none available
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system.cpu0.iq.fu_full::MemRead 73 31.33% 51.07% # attempts to use FU when none available
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system.cpu0.iq.fu_full::MemWrite 114 48.93% 100.00% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu0.iq.FU_type_0::IntAlu 176241 42.19% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
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system.cpu0.iq.FU_type_0::MemRead 160662 38.46% 80.66% # Type of FU issued
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system.cpu0.iq.FU_type_0::MemWrite 80799 19.34% 100.00% # Type of FU issued
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system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu0.iq.FU_type_0::total 417702 # Type of FU issued
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system.cpu0.iq.rate 1.900468 # Inst issue rate
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system.cpu0.iq.fu_busy_cnt 233 # FU busy when requested
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system.cpu0.iq.fu_busy_rate 0.000558 # FU busy rate (busy events/executed inst)
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system.cpu0.iq.int_inst_queue_reads 1037774 # Number of integer instruction queue reads
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system.cpu0.iq.int_inst_queue_writes 432063 # Number of integer instruction queue writes
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system.cpu0.iq.int_inst_queue_wakeup_accesses 415867 # Number of integer instruction queue wakeup accesses
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system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
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system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
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system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
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system.cpu0.iq.int_alu_accesses 417935 # Number of integer alu accesses
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system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
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system.cpu0.iew.lsq.thread0.forwLoads 78173 # Number of loads that had data forwarded from stores
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|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2242 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 1114 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 500579 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 311 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 161147 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 81377 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 1472 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 416616 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 160343 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1086 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 79225 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 241004 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 82800 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 80661 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 1.895527 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 416200 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 415867 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 246464 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 248856 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 1.892119 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.990388 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 12251 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 1265 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 199591 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 2.446493 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 2.132962 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 34293 17.18% 17.18% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 82677 41.42% 58.60% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 2432 1.22% 59.82% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 705 0.35% 60.18% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 565 0.28% 60.46% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 77961 39.06% 99.52% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 418 0.21% 99.73% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 251 0.13% 99.86% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 289 0.14% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 199591 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 488298 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 488298 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 238864 # Number of memory references committed
|
|
system.cpu0.commit.loads 158905 # Number of loads committed
|
|
system.cpu0.commit.membars 84 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 81846 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 328962 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 223 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 289 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 698690 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 1003556 # The number of ROB writes
|
|
system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 17774 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.committedInsts 409636 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 409636 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 409636 # Number of Instructions Simulated
|
|
system.cpu0.cpi 0.536547 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 0.536547 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 1.863769 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 1.863769 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 745424 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 335847 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
|
|
system.cpu0.misc_regfile_reads 242810 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
|
|
system.cpu0.icache.replacements 299 # number of replacements
|
|
system.cpu0.icache.tagsinuse 247.576197 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 5285 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 591 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 8.942470 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 247.576197 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.483547 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.483547 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 5285 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 5285 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 5285 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 5285 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 5285 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 5285 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 744 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28183000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 28183000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 28183000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 28183000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 28183000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 28183000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6029 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 6029 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 6029 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 6029 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 6029 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 6029 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123404 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.123404 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123404 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.123404 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123404 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.123404 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 37880.376344 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 37880.376344 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 37880.376344 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 37880.376344 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 152 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 152 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 152 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 152 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 152 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 152 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 592 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 592 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 592 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 592 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 592 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 592 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22043000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 22043000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22043000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 22043000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22043000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 22043000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098192 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.098192 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.098192 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37234.797297 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 2 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 144.284283 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 160925 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 946.617647 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 144.284283 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.281805 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.281805 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 81643 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 81643 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 79364 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 79364 # number of WriteReq hits
|
|
system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
|
|
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 161007 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 161007 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 161007 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 161007 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 465 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 465 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 553 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 553 # number of WriteReq misses
|
|
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
|
|
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1018 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14129000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 14129000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26395982 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 26395982 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 370000 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::total 370000 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 40524982 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 40524982 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 40524982 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 40524982 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 82108 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 82108 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 79917 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 79917 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 162025 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 162025 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 162025 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 162025 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005663 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.005663 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006920 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.006920 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006283 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.006283 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006283 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.006283 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30384.946237 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30384.946237 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47732.336347 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 47732.336347 # average WriteReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 17619.047619 # average SwapReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::total 17619.047619 # average SwapReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 39808.430255 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 39808.430255 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.291667 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 1 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 381 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 381 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 657 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 657 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 657 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 657 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5343500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5343500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6330000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6330000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 328000 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 328000 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11673500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 11673500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11673500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 11673500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002302 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002302 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002228 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002228 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28272.486772 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28272.486772 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36802.325581 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36802.325581 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15619.047619 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15619.047619 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.numCycles 184127 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.BPredUnit.lookups 48566 # Number of BP lookups
|
|
system.cpu1.BPredUnit.condPredicted 45425 # Number of conditional branches predicted
|
|
system.cpu1.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
|
|
system.cpu1.BPredUnit.BTBLookups 41634 # Number of BTB lookups
|
|
system.cpu1.BPredUnit.BTBHits 40784 # Number of BTB hits
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target.
|
|
system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
system.cpu1.fetch.icacheStallCycles 32363 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 265611 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 48566 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 41641 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 96301 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 4375 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.BlockedCycles 40077 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.NoActiveThreadStallCycles 6455 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu1.fetch.PendingTrapStallCycles 1055 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.CacheLines 23564 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 345 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 179027 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.483637 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.076927 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 82726 46.21% 46.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 49826 27.83% 74.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 7772 4.34% 78.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 3158 1.76% 80.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 709 0.40% 80.54% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 29207 16.31% 96.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1125 0.63% 97.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 886 0.49% 97.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 3618 2.02% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 179027 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.263764 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 1.442542 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 39330 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 35122 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 88807 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 6541 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 2772 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DecodedInsts 261671 # Number of instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 2772 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 40116 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 20114 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 14157 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 82544 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 12869 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 259082 # Number of instructions processed by rename
|
|
system.cpu1.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.RenamedOperands 180494 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 488461 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 488461 # Number of integer rename lookups
|
|
system.cpu1.rename.CommittedMaps 165372 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 15122 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 1240 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 15783 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 71004 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 32715 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 34344 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 27479 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 212625 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 7991 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 216005 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 69 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 12464 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 11017 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 179027 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 1.206550 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.298788 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 80193 44.79% 44.79% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 27393 15.30% 60.09% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 32961 18.41% 78.51% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 33539 18.73% 97.24% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 3241 1.81% 99.05% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1264 0.71% 99.76% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 324 0.18% 99.94% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 179027 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 20 6.78% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 65 22.03% 28.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 107139 49.60% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.60% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 76812 35.56% 85.16% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 32054 14.84% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 216005 # Type of FU issued
|
|
system.cpu1.iq.rate 1.173131 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.001366 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 611401 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 233118 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 214044 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 216300 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 27354 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2609 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1525 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 2772 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 1710 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 255983 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 380 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 71004 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 32715 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 1213 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 214708 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 69981 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 1297 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 35367 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 101954 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 44806 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 31973 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 1.166086 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 214321 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 214044 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 118861 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 123754 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 1.162480 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.960462 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 14492 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 7251 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 1525 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 169801 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 1.422188 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.937267 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 80979 47.69% 47.69% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 42780 25.19% 72.88% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 6215 3.66% 76.54% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 8147 4.80% 81.34% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1520 0.90% 82.24% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 27830 16.39% 98.63% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 515 0.30% 98.93% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 1002 0.59% 99.52% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 169801 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 241489 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 241489 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 99585 # Number of memory references committed
|
|
system.cpu1.commit.loads 68395 # Number of loads committed
|
|
system.cpu1.commit.membars 6536 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 43685 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 165393 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 813 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 424382 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 514748 # The number of ROB writes
|
|
system.cpu1.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 5100 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 35660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 200479 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 200479 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 200479 # Number of Instructions Simulated
|
|
system.cpu1.cpi 0.918435 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 0.918435 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 1.088808 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 1.088808 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 365766 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 171568 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 103658 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
|
|
system.cpu1.icache.replacements 321 # number of replacements
|
|
system.cpu1.icache.tagsinuse 92.890627 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 23041 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 438 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 52.605023 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 92.890627 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.181427 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.181427 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 23041 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 23041 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 23041 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 23041 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 23041 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 23041 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 523 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 523 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 523 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 523 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 523 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 523 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10934000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 10934000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 10934000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 10934000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 10934000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 10934000 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 23564 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 23564 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 23564 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 23564 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 23564 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 23564 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022195 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.022195 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022195 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.022195 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022195 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.022195 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20906.309751 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 20906.309751 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 20906.309751 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 20906.309751 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 438 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 438 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 438 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 438 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8718000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8718000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8718000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 8718000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8718000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 8718000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018588 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.018588 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.018588 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19904.109589 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 27.499718 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 37345 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 1333.750000 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 27.499718 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.053710 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.053710 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 42212 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 42212 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 30981 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 30981 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 17 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 17 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 73193 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 73193 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 73193 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 73193 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 398 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 398 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 538 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 538 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 538 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 538 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9898500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3138500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 3138500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1008000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 1008000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 13037000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 13037000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 13037000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 13037000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 42610 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 42610 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 31121 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 31121 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 73731 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 73731 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 73731 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 73731 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009341 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.009341 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004499 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.004499 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.753623 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.753623 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007297 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.007297 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007297 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.007297 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 24870.603015 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 24870.603015 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22417.857143 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22417.857143 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 19384.615385 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 19384.615385 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 24232.342007 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 24232.342007 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 238 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 37 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 37 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 275 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 275 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2446500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1653500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1653500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 904000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 904000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4100000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 4100000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4100000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 4100000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003755 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003755 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003310 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003310 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.753623 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15290.625000 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15290.625000 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16053.398058 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16053.398058 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17384.615385 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17384.615385 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.numCycles 183836 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.BPredUnit.lookups 53962 # Number of BP lookups
|
|
system.cpu2.BPredUnit.condPredicted 50907 # Number of conditional branches predicted
|
|
system.cpu2.BPredUnit.condIncorrect 1502 # Number of conditional branches incorrect
|
|
system.cpu2.BPredUnit.BTBLookups 47302 # Number of BTB lookups
|
|
system.cpu2.BPredUnit.BTBHits 46374 # Number of BTB hits
|
|
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.BPredUnit.usedRAS 814 # Number of times the RAS was used to get a target.
|
|
system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
system.cpu2.fetch.icacheStallCycles 29545 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 300535 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 53962 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 47188 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 106111 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 4305 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.BlockedCycles 35885 # Number of cycles fetch has spent blocked
|
|
system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.NoActiveThreadStallCycles 6446 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu2.fetch.PendingTrapStallCycles 1035 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.CacheLines 21240 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 181756 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.653508 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.139245 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 75645 41.62% 41.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 54116 29.77% 71.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 6682 3.68% 75.07% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 3224 1.77% 76.84% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 665 0.37% 77.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 35775 19.68% 96.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1232 0.68% 97.57% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 880 0.48% 98.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3537 1.95% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 181756 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.293533 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 1.634799 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 35633 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 31817 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 99530 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 5601 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 2729 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DecodedInsts 296271 # Number of instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 2729 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 36405 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 17349 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 13658 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 94174 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 10995 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 293755 # Number of instructions processed by rename
|
|
system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LSQFullEvents 37 # Number of times rename has blocked due to LSQ full
|
|
system.cpu2.rename.RenamedOperands 205188 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 562117 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 562117 # Number of integer rename lookups
|
|
system.cpu2.rename.CommittedMaps 190142 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 15046 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 1228 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 13734 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 82915 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 39246 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 39773 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 34011 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 242760 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 6943 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 245051 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 12414 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 11373 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 664 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 181756 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 1.348242 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.310708 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 73115 40.23% 40.23% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 24368 13.41% 53.63% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 39333 21.64% 75.27% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 39995 22.00% 97.28% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 3268 1.80% 99.08% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1268 0.70% 99.77% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 298 0.16% 99.94% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 181756 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 20 6.83% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 63 21.50% 28.33% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 118754 48.46% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 87780 35.82% 84.28% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 38517 15.72% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 245051 # Type of FU issued
|
|
system.cpu2.iq.rate 1.332987 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 293 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 672224 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 262158 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 243059 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 245344 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 33799 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 2624 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 1758 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 290501 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 82915 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 39246 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 41 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 1158 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 1671 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 243729 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 81914 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 1322 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 40798 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 120340 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 50195 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 38426 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.325796 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 243343 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 243059 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 137174 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 142058 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 1.322151 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.965620 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 14265 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 6279 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 1502 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 172582 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 1.600480 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 2.009191 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 72897 42.24% 42.24% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 48196 27.93% 70.17% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 6187 3.58% 73.75% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 7136 4.13% 77.89% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 1545 0.90% 78.78% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 34295 19.87% 98.65% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 518 0.30% 98.95% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 991 0.57% 99.53% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 817 0.47% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 172582 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 276214 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 276214 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 117916 # Number of memory references committed
|
|
system.cpu2.commit.loads 80291 # Number of loads committed
|
|
system.cpu2.commit.membars 5562 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 49152 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 189186 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 461657 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 583698 # The number of ROB writes
|
|
system.cpu2.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 2080 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 35951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 230713 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 230713 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.committedInsts_total 230713 # Number of Instructions Simulated
|
|
system.cpu2.cpi 0.796817 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 0.796817 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 1.254994 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 1.254994 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 420543 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 196056 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 121964 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
|
|
system.cpu2.icache.replacements 323 # number of replacements
|
|
system.cpu2.icache.tagsinuse 86.140818 # Cycle average of tags in use
|
|
system.cpu2.icache.total_refs 20746 # Total number of references to valid blocks.
|
|
system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.avg_refs 47.582569 # Average number of references to valid blocks.
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.occ_blocks::cpu2.inst 86.140818 # Average occupied blocks per requestor
|
|
system.cpu2.icache.occ_percent::cpu2.inst 0.168244 # Average percentage of cache occupancy
|
|
system.cpu2.icache.occ_percent::total 0.168244 # Average percentage of cache occupancy
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 20746 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 20746 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 20746 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 20746 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 20746 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 20746 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 494 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 494 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 494 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 494 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 494 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 494 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6486500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 6486500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 6486500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 6486500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 6486500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 6486500 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 21240 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 21240 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 21240 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 21240 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 21240 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 21240 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023258 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.023258 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023258 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.023258 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023258 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.023258 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13130.566802 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 13130.566802 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 13130.566802 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 13130.566802 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::cpu2.inst 58 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::cpu2.inst 58 # number of overall MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::total 58 # number of overall MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 436 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 436 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 436 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5217500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 5217500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5217500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 5217500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5217500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 5217500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020527 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.020527 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.020527 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11966.743119 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 11966.743119 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 11966.743119 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tagsinuse 26.073093 # Cycle average of tags in use
|
|
system.cpu2.dcache.total_refs 43891 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.avg_refs 1513.482759 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.occ_blocks::cpu2.data 26.073093 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.occ_percent::cpu2.data 0.050924 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_percent::total 0.050924 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 47692 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 47692 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 37413 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 37413 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 85105 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 85105 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 85105 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 85105 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 405 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 405 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 141 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 141 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 546 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 546 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 546 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 546 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9305500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 9305500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2828000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 2828000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 998500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 998500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 12133500 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 12133500 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 12133500 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 12133500 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 48097 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 48097 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 37554 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 37554 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 85651 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 85651 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 85651 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 85651 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008420 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.008420 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003755 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.003755 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.830986 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006375 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.006375 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006375 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.006375 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22976.543210 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 22976.543210 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20056.737589 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20056.737589 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 16923.728814 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 16923.728814 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 22222.527473 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 22222.527473 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 239 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::cpu2.data 273 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::cpu2.data 273 # number of overall MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::total 273 # number of overall MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 273 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 273 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2062000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2062000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1458000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 880500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 880500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 3520000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 3520000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003451 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003451 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002849 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002849 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.830986 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.003187 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.003187 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12421.686747 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12421.686747 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13626.168224 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13626.168224 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14923.728814 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14923.728814 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.numCycles 183564 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.BPredUnit.lookups 54292 # Number of BP lookups
|
|
system.cpu3.BPredUnit.condPredicted 51137 # Number of conditional branches predicted
|
|
system.cpu3.BPredUnit.condIncorrect 1552 # Number of conditional branches incorrect
|
|
system.cpu3.BPredUnit.BTBLookups 47375 # Number of BTB lookups
|
|
system.cpu3.BPredUnit.BTBHits 46456 # Number of BTB hits
|
|
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.BPredUnit.usedRAS 865 # Number of times the RAS was used to get a target.
|
|
system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
system.cpu3.fetch.icacheStallCycles 29332 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.Insts 302436 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.Branches 54292 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.predictedBranches 47321 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.Cycles 106466 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.SquashCycles 4424 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.BlockedCycles 35508 # Number of cycles fetch has spent blocked
|
|
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu3.fetch.NoActiveThreadStallCycles 6464 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu3.fetch.PendingTrapStallCycles 1083 # Number of stall cycles due to pending traps
|
|
system.cpu3.fetch.CacheLines 21183 # Number of cache lines fetched
|
|
system.cpu3.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.rateDist::samples 181653 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.664911 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.146175 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 75187 41.39% 41.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 54224 29.85% 71.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 6571 3.62% 74.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 3185 1.75% 76.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 729 0.40% 77.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 36075 19.86% 96.87% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 1175 0.65% 97.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 882 0.49% 98.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 3625 2.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 181653 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.branchRate 0.295766 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.rate 1.647578 # Number of inst fetches per cycle
|
|
system.cpu3.decode.IdleCycles 35528 # Number of cycles decode is idle
|
|
system.cpu3.decode.BlockedCycles 31409 # Number of cycles decode is blocked
|
|
system.cpu3.decode.RunCycles 99893 # Number of cycles decode is running
|
|
system.cpu3.decode.UnblockCycles 5564 # Number of cycles decode is unblocking
|
|
system.cpu3.decode.SquashCycles 2795 # Number of cycles decode is squashing
|
|
system.cpu3.decode.DecodedInsts 298258 # Number of instructions handled by decode
|
|
system.cpu3.rename.SquashCycles 2795 # Number of cycles rename is squashing
|
|
system.cpu3.rename.IdleCycles 36311 # Number of cycles rename is idle
|
|
system.cpu3.rename.BlockCycles 17134 # Number of cycles rename is blocking
|
|
system.cpu3.rename.serializeStallCycles 13439 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RunCycles 94588 # Number of cycles rename is running
|
|
system.cpu3.rename.UnblockCycles 10922 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RenamedInsts 295479 # Number of instructions processed by rename
|
|
system.cpu3.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
|
|
system.cpu3.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full
|
|
system.cpu3.rename.RenamedOperands 206753 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RenameLookups 566043 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.int_rename_lookups 566043 # Number of integer rename lookups
|
|
system.cpu3.rename.CommittedMaps 191392 # Number of HB maps that are committed
|
|
system.cpu3.rename.UndoneMaps 15361 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.serializingInsts 1256 # count of serializing insts renamed
|
|
system.cpu3.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed
|
|
system.cpu3.rename.skidInsts 13950 # count of insts added to the skid buffer
|
|
system.cpu3.memDep0.insertedLoads 83468 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 39555 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.conflictingLoads 39943 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 34309 # Number of conflicting stores.
|
|
system.cpu3.iq.iqInstsAdded 244369 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqNonSpecInstsAdded 6827 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqInstsIssued 246724 # Number of instructions issued
|
|
system.cpu3.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedInstsExamined 12382 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedOperandsExamined 11033 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 652 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.issued_per_cycle::samples 181653 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::mean 1.358216 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::stdev 1.312562 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::0 72528 39.93% 39.93% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::1 24126 13.28% 53.21% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::2 39707 21.86% 75.07% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::3 40305 22.19% 97.25% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::4 3272 1.80% 99.06% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::5 1282 0.71% 99.76% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::6 320 0.18% 99.94% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::8 60 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::total 181653 # Number of insts issued each cycle
|
|
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntAlu 22 7.41% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemRead 65 21.89% 29.29% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemWrite 210 70.71% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntAlu 119576 48.47% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.47% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemRead 88284 35.78% 84.25% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemWrite 38864 15.75% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::total 246724 # Type of FU issued
|
|
system.cpu3.iq.rate 1.344076 # Inst issue rate
|
|
system.cpu3.iq.fu_busy_cnt 297 # FU busy when requested
|
|
system.cpu3.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.int_inst_queue_reads 675462 # Number of integer instruction queue reads
|
|
system.cpu3.iq.int_inst_queue_writes 263617 # Number of integer instruction queue writes
|
|
system.cpu3.iq.int_inst_queue_wakeup_accesses 244690 # Number of integer instruction queue wakeup accesses
|
|
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu3.iq.int_alu_accesses 247021 # Number of integer alu accesses
|
|
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu3.iew.lsq.thread0.forwLoads 34138 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.squashedLoads 2601 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread0.squashedStores 1592 # Number of stores squashed
|
|
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewSquashCycles 2795 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.iewDispatchedInsts 292203 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewDispSquashedInsts 375 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispLoadInsts 83468 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispStoreInsts 39555 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations
|
|
system.cpu3.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.iew.predictedNotTakenIncorrect 1226 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.branchMispredicts 1724 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewExecutedInsts 245374 # Number of executed instructions
|
|
system.cpu3.iew.iewExecLoadInsts 82515 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu3.iew.exec_nop 41007 # number of nop insts executed
|
|
system.cpu3.iew.exec_refs 121290 # number of memory reference insts executed
|
|
system.cpu3.iew.exec_branches 50490 # Number of branches executed
|
|
system.cpu3.iew.exec_stores 38775 # Number of stores executed
|
|
system.cpu3.iew.exec_rate 1.336722 # Inst execution rate
|
|
system.cpu3.iew.wb_sent 244974 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.wb_count 244690 # cumulative count of insts written-back
|
|
system.cpu3.iew.wb_producers 138171 # num instructions producing a value
|
|
system.cpu3.iew.wb_consumers 143054 # num instructions consuming a value
|
|
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu3.iew.wb_rate 1.332996 # insts written-back per cycle
|
|
system.cpu3.iew.wb_fanout 0.965866 # average fanout of values written-back
|
|
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu3.commit.commitSquashedInsts 14351 # The number of squashed insts skipped by commit
|
|
system.cpu3.commit.commitNonSpecStalls 6175 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.branchMispredicts 1552 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.committed_per_cycle::samples 172395 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::mean 1.611613 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::stdev 2.012919 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::0 72191 41.88% 41.88% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::1 48466 28.11% 69.99% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::2 6229 3.61% 73.60% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::3 7040 4.08% 77.69% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::4 1522 0.88% 78.57% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::5 34600 20.07% 98.64% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::6 541 0.31% 98.95% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::7 992 0.58% 99.53% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::total 172395 # Number of insts commited each cycle
|
|
system.cpu3.commit.committedInsts 277834 # Number of instructions committed
|
|
system.cpu3.commit.committedOps 277834 # Number of ops (including micro ops) committed
|
|
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.refs 118830 # Number of memory references committed
|
|
system.cpu3.commit.loads 80867 # Number of loads committed
|
|
system.cpu3.commit.membars 5460 # Number of memory barriers committed
|
|
system.cpu3.commit.branches 49386 # Number of branches committed
|
|
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu3.commit.int_insts 190336 # Number of committed integer instructions.
|
|
system.cpu3.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu3.commit.bw_lim_events 814 # number cycles where commit BW limit reached
|
|
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu3.rob.rob_reads 463179 # The number of ROB reads
|
|
system.cpu3.rob.rob_writes 587180 # The number of ROB writes
|
|
system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.idleCycles 1911 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.quiesceCycles 36223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu3.committedInsts 232199 # Number of Instructions Simulated
|
|
system.cpu3.committedOps 232199 # Number of Ops (including micro ops) Simulated
|
|
system.cpu3.committedInsts_total 232199 # Number of Instructions Simulated
|
|
system.cpu3.cpi 0.790546 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 0.790546 # CPI: Total CPI of All Threads
|
|
system.cpu3.ipc 1.264948 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 1.264948 # IPC: Total IPC of All Threads
|
|
system.cpu3.int_regfile_reads 423588 # number of integer regfile reads
|
|
system.cpu3.int_regfile_writes 197545 # number of integer regfile writes
|
|
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu3.misc_regfile_reads 122942 # number of misc regfile reads
|
|
system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
|
|
system.cpu3.icache.replacements 321 # number of replacements
|
|
system.cpu3.icache.tagsinuse 83.581511 # Cycle average of tags in use
|
|
system.cpu3.icache.total_refs 20679 # Total number of references to valid blocks.
|
|
system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.avg_refs 47.428899 # Average number of references to valid blocks.
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.occ_blocks::cpu3.inst 83.581511 # Average occupied blocks per requestor
|
|
system.cpu3.icache.occ_percent::cpu3.inst 0.163245 # Average percentage of cache occupancy
|
|
system.cpu3.icache.occ_percent::total 0.163245 # Average percentage of cache occupancy
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 20679 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 20679 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 20679 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 20679 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 20679 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 20679 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 504 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6381500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 6381500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 6381500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 6381500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 6381500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 6381500 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 21183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 21183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 21183 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 21183 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 21183 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 21183 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023793 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.023793 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023793 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.023793 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023793 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.023793 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12661.706349 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 12661.706349 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 12661.706349 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 12661.706349 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 68 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::cpu3.inst 68 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::cpu3.inst 68 # number of overall MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5023500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 5023500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5023500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 5023500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5023500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 5023500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020583 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.020583 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.020583 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11521.788991 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11521.788991 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11521.788991 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11521.788991 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11521.788991 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11521.788991 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tagsinuse 24.842435 # Cycle average of tags in use
|
|
system.cpu3.dcache.total_refs 44137 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.avg_refs 1576.321429 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.occ_blocks::cpu3.data 24.842435 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.occ_percent::cpu3.data 0.048520 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_percent::total 0.048520 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 47956 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 47956 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 37758 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 37758 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 85714 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 85714 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 85714 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 85714 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 403 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 403 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 136 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 136 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 539 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 539 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 539 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 539 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8840000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 8840000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2771500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 2771500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 950000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 950000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 11611500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 11611500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 11611500 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 11611500 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 48359 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 48359 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 37894 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 37894 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 86253 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 86253 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 86253 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 86253 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008334 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.008334 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003589 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.003589 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.811594 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006249 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.006249 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006249 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.006249 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 21935.483871 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 21935.483871 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20378.676471 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 20378.676471 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 16964.285714 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 16964.285714 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21542.671614 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 21542.671614 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21542.671614 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 21542.671614 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 248 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::cpu3.data 279 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::cpu3.data 279 # number of overall MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1965500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1965500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1462000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1462000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 838000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 838000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3427500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 3427500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3427500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 3427500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003205 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003205 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002771 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.811594 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003014 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.003014 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003014 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.003014 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12680.645161 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12680.645161 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13923.809524 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13923.809524 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 14964.285714 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 14964.285714 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.replacements 0 # number of replacements
|
|
system.l2c.tagsinuse 435.526886 # Cycle average of tags in use
|
|
system.l2c.total_refs 1471 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 536 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 2.744403 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::writebacks 0.836552 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.inst 292.896606 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.data 59.494044 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.inst 70.004577 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.data 5.700111 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.inst 3.075204 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.data 0.772877 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.inst 2.016825 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.data 0.730090 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.004469 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.001068 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.006646 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.inst 232 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 348 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 427 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.inst 432 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1471 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.l2c.demand_hits::cpu0.inst 232 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 348 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 427 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 432 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1471 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 232 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 348 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 427 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 432 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
|
system.l2c.overall_hits::total 1471 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 360 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 90 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 9 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.inst 4 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 546 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 20 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 74 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 360 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 90 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 4 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 677 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 360 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 90 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 9 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 4 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
|
system.l2c.overall_misses::total 677 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 19126500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 4185500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 4718500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 377000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 420000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 52500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.inst 209000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 29141500 # number of ReadReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5186500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 748500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 663500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 659500 # number of ReadExReq miss cycles
|
|
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system.l2c.demand_miss_latency::cpu2.inst 420000 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu3.inst 209000 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::total 36399500 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::cpu0.inst 19126500 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu0.data 9372000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.inst 4718500 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.data 1125500 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu2.inst 420000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu2.data 716000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu3.inst 209000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu3.data 712000 # number of overall miss cycles
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system.l2c.overall_miss_latency::total 36399500 # number of overall miss cycles
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system.l2c.ReadReq_accesses::cpu0.inst 592 # number of ReadReq accesses(hits+misses)
|
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|
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system.l2c.ReadReq_accesses::cpu1.inst 438 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu2.inst 436 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu3.inst 436 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
|
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system.l2c.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses)
|
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system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
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system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
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system.l2c.UpgradeReq_accesses::cpu0.data 23 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
|
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system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
|
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system.l2c.UpgradeReq_accesses::total 77 # number of UpgradeReq accesses(hits+misses)
|
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|
|
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|
|
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
|
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system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
|
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system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
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system.l2c.demand_accesses::cpu0.inst 592 # number of demand (read+write) accesses
|
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system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
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|
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system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu2.inst 436 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu3.inst 436 # number of demand (read+write) accesses
|
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|
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system.l2c.demand_accesses::total 2148 # number of demand (read+write) accesses
|
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system.l2c.overall_accesses::cpu0.inst 592 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 438 # number of overall (read+write) accesses
|
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system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
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system.l2c.overall_accesses::cpu2.inst 436 # number of overall (read+write) accesses
|
|
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|
|
system.l2c.overall_accesses::cpu3.inst 436 # number of overall (read+write) accesses
|
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system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
|
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system.l2c.overall_accesses::total 2148 # number of overall (read+write) accesses
|
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|
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system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu2.inst 0.020642 # miss rate for ReadReq accesses
|
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system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu3.inst 0.009174 # miss rate for ReadReq accesses
|
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system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
|
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system.l2c.ReadReq_miss_rate::total 0.270699 # miss rate for ReadReq accesses
|
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system.l2c.UpgradeReq_miss_rate::cpu0.data 0.869565 # miss rate for UpgradeReq accesses
|
|
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|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
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system.l2c.UpgradeReq_miss_rate::total 0.961039 # miss rate for UpgradeReq accesses
|
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|
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|
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|
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system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
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system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
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|
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system.l2c.demand_miss_rate::cpu1.inst 0.205479 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu3.inst 0.009174 # miss rate for demand accesses
|
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|
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system.l2c.demand_miss_rate::total 0.315177 # miss rate for demand accesses
|
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|
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system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu3.inst 0.009174 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
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system.l2c.overall_miss_rate::total 0.315177 # miss rate for overall accesses
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|
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system.l2c.ReadReq_avg_miss_latency::cpu0.data 56560.810811 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::cpu1.data 53857.142857 # average ReadReq miss latency
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|
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|
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system.l2c.ReadExReq_avg_miss_latency::total 55404.580153 # average ReadExReq miss latency
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system.l2c.demand_avg_miss_latency::total 53765.878877 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu0.inst 53129.166667 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu1.data 56275 # average overall miss latency
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system.l2c.overall_avg_miss_latency::total 53765.878877 # average overall miss latency
|
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
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|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
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system.l2c.fast_writes 0 # number of fast writes performed
|
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|
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|
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|
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system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
|
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system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
|
|
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|
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system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
|
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system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
|
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|
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system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits
|
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|
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|
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|
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|
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system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses
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|
system.l2c.overall_mshr_miss_latency::cpu3.data 553500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 27972000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.608108 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.200913 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009174 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.267229 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.869565 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.961039 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.608108 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.200913 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009174 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.311918 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.608108 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.200913 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009174 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.311918 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44472.972973 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41714.285714 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 41391.465677 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40224.550000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40166.333333 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40138.611111 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40527.333333 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40263.135135 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42968.085106 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45500 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43166.666667 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42791.666667 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 43221.374046 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|