d52adc4eb6
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
420 lines
48 KiB
Plaintext
420 lines
48 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000025 # Number of seconds simulated
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sim_ticks 25317500 # Number of ticks simulated
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final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 84248 # Simulator instruction rate (inst/s)
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host_op_rate 84237 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 140641450 # Simulator tick rate (ticks/s)
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host_mem_usage 214032 # Number of bytes of host memory used
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host_seconds 0.18 # Real time elapsed on the host
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sim_insts 15162 # Number of instructions simulated
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sim_ops 15162 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27904 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 50636 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 5020 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 3517 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 2141 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 60.875746 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 2317 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 25466 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 5027 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 3931 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 68.939845 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 11058 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 17355 # Number of cycles cpu stages are processed.
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system.cpu.activity 34.274034 # Percentage of cycles cpu is active
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system.cpu.comLoads 2225 # Number of Load instructions committed
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system.cpu.comStores 1448 # Number of Store instructions committed
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system.cpu.comBranches 3358 # Number of Branches instructions committed
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system.cpu.comNops 726 # Number of Nop instructions committed
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system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed
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system.cpu.comInts 7166 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 15162 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
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system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 37504 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 47752 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 41318 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 164.702089 # Cycle average of tags in use
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system.cpu.icache.total_refs 2586 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 164.702089 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.080421 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 2586 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 2586 # number of overall hits
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system.cpu.icache.overall_hits::total 2586 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
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system.cpu.icache.overall_misses::total 369 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 20235000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 20235000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 20235000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 20235000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 20235000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 2955 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 2955 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 2955 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124873 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.124873 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54837.398374 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 54837.398374 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 131 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16329000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 16329000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16329000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 16329000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16329000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 16329000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.169435 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54249.169435 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 96.602865 # Cycle average of tags in use
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system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 96.602865 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.023585 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.023585 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 1141 # number of WriteReq hits
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system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
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system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
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system.cpu.dcache.demand_hits::cpu.data 3308 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 3308 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 3308 # number of overall hits
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system.cpu.dcache.overall_hits::total 3308 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 301 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 301 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses
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system.cpu.dcache.overall_misses::total 359 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 3411000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 3411000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 16758500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 16758500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 20169500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 20169500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 20169500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 20169500 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208738 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.208738 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58810.344828 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 58810.344828 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55676.079734 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 55676.079734 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 216 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 221 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 221 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2994500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2994500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7727500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7727500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7727500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7727500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55682.352941 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16005500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18945500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4645500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4645500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 16005500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7585500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 23591000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 16005500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7585500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 23591000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53530.100334 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53822.443182 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54652.941176 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54652.941176 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 53983.981693 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 53983.981693 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12396000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2298500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14694500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3614500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12396000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 18309000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12396000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 18309000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41745.738636 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42523.529412 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42523.529412 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|