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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
Andreas Hansson d52adc4eb6 Stats: Update stats for cache timings in cycles 
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
2012-10-15 08:12:21 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.855236 # Number of seconds simulated
sim_ticks 1855236450500 # Number of ticks simulated
final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 182093 # Simulator instruction rate (inst/s)
host_op_rate 182093 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6374280472 # Simulator tick rate (ticks/s)
host_mem_usage 298212 # Number of bytes of host memory used
host_seconds 291.05 # Real time elapsed on the host
sim_insts 52998368 # Number of instructions simulated
sim_ops 52998368 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory
system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory
system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s)
system.iocache.replacements 41685 # number of replacements
system.iocache.tagsinuse 1.255779 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 9942716 # DTB read hits
system.cpu.dtb.read_misses 44791 # DTB read misses
system.cpu.dtb.read_acv 565 # DTB read access violations
system.cpu.dtb.read_accesses 947396 # DTB read accesses
system.cpu.dtb.write_hits 6623666 # DTB write hits
system.cpu.dtb.write_misses 10259 # DTB write misses
system.cpu.dtb.write_acv 393 # DTB write access violations
system.cpu.dtb.write_accesses 338396 # DTB write accesses
system.cpu.dtb.data_hits 16566382 # DTB hits
system.cpu.dtb.data_misses 55050 # DTB misses
system.cpu.dtb.data_acv 958 # DTB access violations
system.cpu.dtb.data_accesses 1285792 # DTB accesses
system.cpu.itb.fetch_hits 1328947 # ITB hits
system.cpu.itb.fetch_misses 38142 # ITB misses
system.cpu.itb.fetch_acv 1080 # ITB acv
system.cpu.itb.fetch_accesses 1367089 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 112948398 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed
system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued
system.cpu.iq.rate 0.505315 # Inst issue rate
system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 3555305 # number of nop insts executed
system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed
system.cpu.iew.exec_branches 8969939 # Number of branches executed
system.cpu.iew.exec_stores 6649129 # Number of stores executed
system.cpu.iew.exec_rate 0.500679 # Inst execution rate
system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back
system.cpu.iew.wb_producers 27804186 # num instructions producing a value
system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56188905 # Number of instructions committed
system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 15476867 # Number of memory references committed
system.cpu.commit.loads 9095415 # Number of loads committed
system.cpu.commit.membars 226300 # Number of memory barriers committed
system.cpu.commit.branches 8447820 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
system.cpu.commit.int_insts 52034961 # Number of committed integer instructions.
system.cpu.commit.function_calls 740468 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 141682968 # The number of ROB reads
system.cpu.rob.rob_writes 129465441 # The number of ROB writes
system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52998368 # Number of Instructions Simulated
system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated
system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads
system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 74144483 # number of integer regfile reads
system.cpu.int_regfile_writes 40484328 # number of integer regfile writes
system.cpu.fp_regfile_reads 165992 # number of floating regfile reads
system.cpu.fp_regfile_writes 167427 # number of floating regfile writes
system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads
system.cpu.misc_regfile_writes 946826 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.icache.replacements 1020348 # number of replacements
system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use
system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits
system.cpu.icache.overall_hits::total 7661721 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses
system.cpu.icache.overall_misses::total 1079749 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 58677 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021072 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1021072 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1402622 # number of replacements
system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use
system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7274743 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7274743 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4204816 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4204816 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 190397 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 190397 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 219522 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits
system.cpu.dcache.overall_hits::total 11479559 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
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system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses
system.cpu.dcache.overall_misses::total 3739889 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6147230 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213437 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 213437 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 219523 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 219523 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15219448 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15219448 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15219448 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15219448 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198130 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.198130 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315982 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.315982 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107948 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks
system.cpu.dcache.writebacks::total 841878 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5152 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2354499 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2354499 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2354499 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2354499 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085162 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1085162 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300228 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 300228 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17888 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17888 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1385390 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 338417 # number of replacements
system.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 185452 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 185452 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.data 1013956 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 1013956 # number of overall hits
system.cpu.l2cache.overall_hits::total 2019767 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 273885 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 289036 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 115380 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 115380 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.data 389265 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 841878 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 841878 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 59 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 59 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 300832 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 300832 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.data 1403221 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 1403221 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2424183 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248447 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.136123 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.559322 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.559322 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383536 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383536 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014840 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277408 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.166826 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks
system.cpu.l2cache.writebacks::total 76030 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 191902 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1909
system.cpu.kern.mode_good::user 1739
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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