This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
460 lines
52 KiB
Text
460 lines
52 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.042001 # Number of seconds simulated
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sim_ticks 42001440000 # Number of ticks simulated
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final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 134131 # Simulator instruction rate (inst/s)
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host_op_rate 134131 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 61300636 # Simulator tick rate (ticks/s)
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host_mem_usage 216520 # Number of bytes of host memory used
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host_seconds 685.17 # Real time elapsed on the host
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sim_insts 91903056 # Number of instructions simulated
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sim_ops 91903056 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
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system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 19996215 # DTB read hits
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system.cpu.dtb.read_misses 10 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 19996225 # DTB read accesses
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system.cpu.dtb.write_hits 6501907 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 6501930 # DTB write accesses
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system.cpu.dtb.data_hits 26498122 # DTB hits
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system.cpu.dtb.data_misses 33 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 26498155 # DTB accesses
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system.cpu.itb.fetch_hits 10035828 # ITB hits
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system.cpu.itb.fetch_misses 49 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 10035877 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 389 # Number of system calls
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system.cpu.numCycles 84002881 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 26769096 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed.
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system.cpu.activity 90.809399 # Percentage of cycles cpu is active
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system.cpu.comLoads 19996198 # Number of Load instructions committed
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system.cpu.comStores 6501103 # Number of Store instructions committed
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system.cpu.comBranches 10240685 # Number of Branches instructions committed
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system.cpu.comNops 7723346 # Number of Nop instructions committed
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system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
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system.cpu.comInts 43665352 # Number of Integer instructions committed
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system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
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system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
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system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 8127 # number of replacements
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system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use
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system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits
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system.cpu.icache.overall_hits::total 10024070 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses
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system.cpu.icache.overall_misses::total 11754 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 157 # number of replacements
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system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use
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system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits
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system.cpu.dcache.overall_hits::total 26491189 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses
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system.cpu.dcache.overall_misses::total 6112 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
|
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system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000854 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000854 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 7218 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7297 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 7218 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7297 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 10012 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 12235 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 10012 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 12235 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279065 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.306665 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|