d52adc4eb6
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
698 lines
79 KiB
Text
698 lines
79 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.070882 # Number of seconds simulated
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sim_ticks 70882487500 # Number of ticks simulated
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final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 146290 # Simulator instruction rate (inst/s)
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host_op_rate 187023 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 37976354 # Simulator tick rate (ticks/s)
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host_mem_usage 236976 # Number of bytes of host memory used
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host_seconds 1866.49 # Real time elapsed on the host
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sim_insts 273048441 # Number of instructions simulated
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sim_ops 349076165 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 272768 # Number of bytes read from this memory
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system.physmem.bytes_read::total 467648 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 4262 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2749339 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3848172 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6597511 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2749339 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2749339 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2749339 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3848172 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6597511 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 191 # Number of system calls
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system.cpu.numCycles 141764976 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 43022632 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 21746290 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 2100537 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 27784307 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 17845610 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 6965581 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 7462 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 40878725 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 328721134 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 43022632 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 24811191 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 73667201 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 8391169 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 20823021 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 3522 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 39401519 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 692730 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 141652682 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.982295 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.454701 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 68666188 48.48% 48.48% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 7372946 5.20% 53.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 5824782 4.11% 57.79% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 6228810 4.40% 62.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 4953654 3.50% 65.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 4319066 3.05% 68.74% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 3319868 2.34% 71.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 4326916 3.05% 74.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 36640452 25.87% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 141652682 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.303479 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.318775 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 47724056 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 16047440 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 69280897 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 2389978 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 6210311 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 7496443 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 70615 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 414536105 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 220570 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 6210311 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 53491207 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 1558118 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 338571 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 65828585 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 14225890 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 403967880 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 1665803 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 10197275 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 723 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 443295910 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 2386846444 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1300310044 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1086536400 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 58710964 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 14469 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 14467 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 35655672 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 105463248 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 93220202 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 4594940 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 5698907 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 391915159 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 25548 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 378021086 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1395950 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 41892562 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 109796784 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 141652682 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.668648 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 2.042717 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 28697410 20.26% 20.26% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 20492119 14.47% 34.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 20907256 14.76% 49.48% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 18207035 12.85% 62.34% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 24094157 17.01% 79.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 15966233 11.27% 90.62% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 9051361 6.39% 97.01% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3319497 2.34% 99.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 917614 0.65% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 141652682 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 8869 0.05% 0.05% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 45720 0.25% 0.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 7848 0.04% 0.37% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 429 0.00% 0.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 193652 1.08% 1.45% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 4980 0.03% 1.48% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 240582 1.34% 2.82% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 9467921 52.63% 55.44% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 8015707 44.56% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 128195849 33.91% 33.91% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 2174611 0.58% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 6839706 1.81% 36.30% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.30% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 8692181 2.30% 38.60% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 3465000 0.92% 39.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 1622054 0.43% 39.94% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 21343322 5.65% 45.59% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 7172329 1.90% 47.49% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135364 1.89% 49.37% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.42% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 102447083 27.10% 76.52% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 88758301 23.48% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 378021086 # Type of FU issued
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system.cpu.iq.rate 2.666534 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 17990410 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.047591 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 665853263 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 301144367 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 252283124 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 251227951 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 132702727 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 118872712 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 266490153 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 129521343 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 10844694 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 10812156 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 121101 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14360 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 10842267 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 29815 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 119 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 6210311 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 59816 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 7651 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 391949728 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 1062817 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 105463248 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 93220202 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 14378 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 211 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 349 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 14360 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 1675475 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 499111 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 2174586 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 373364048 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 101084784 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 4657038 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 9021 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 188503459 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 38700482 # Number of branches executed
|
|
system.cpu.iew.exec_stores 87418675 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.633683 # Inst execution rate
|
|
system.cpu.iew.wb_sent 371949572 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 371155836 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 184798274 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 367725403 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.618107 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.502544 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 42873018 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 2030662 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 135442372 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.577309 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.655328 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 38119190 28.14% 28.14% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 29150867 21.52% 49.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 13483643 9.96% 59.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 11130935 8.22% 67.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 13797972 10.19% 78.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 7276796 5.37% 83.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 3948237 2.92% 86.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3977327 2.94% 89.25% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 14557405 10.75% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 135442372 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 273049053 # Number of instructions committed
|
|
system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 177029027 # Number of memory references committed
|
|
system.cpu.commit.loads 94651092 # Number of loads committed
|
|
system.cpu.commit.membars 11033 # Number of memory barriers committed
|
|
system.cpu.commit.branches 36549055 # Number of branches committed
|
|
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 279593983 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 14557405 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 512832239 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 790114412 # The number of ROB writes
|
|
system.cpu.timesIdled 3064 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 112294 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 273048441 # Number of Instructions Simulated
|
|
system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.519194 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.519194 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.926064 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.926064 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1783379175 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 236079321 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 189868959 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 133650660 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 990849298 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes
|
|
system.cpu.icache.replacements 13928 # number of replacements
|
|
system.cpu.icache.tagsinuse 1856.985526 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 39384906 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 15824 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 2488.934909 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1856.985526 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.906731 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.906731 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 39384906 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 39384906 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 39384906 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 39384906 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 39384906 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 39384906 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 16613 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 16613 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 16613 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 16613 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 16613 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 16613 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 188398500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 188398500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 188398500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 188398500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 188398500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 188398500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 39401519 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 39401519 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 39401519 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 39401519 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 39401519 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 39401519 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000422 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000422 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000422 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000422 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000422 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000422 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11340.426172 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 11340.426172 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 11340.426172 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 11340.426172 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 789 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 789 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 789 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 789 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 789 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15824 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 15824 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 15824 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 15824 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15824 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 15824 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 136475000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 136475000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 136475000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 136475000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 136475000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 136475000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000402 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000402 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000402 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8624.557634 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8624.557634 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1417 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3115.188705 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 172067508 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 4618 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 37260.179298 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3115.188705 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.760544 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.760544 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 90009194 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 90009194 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 82031517 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 82031517 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13545 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 13545 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 13252 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 13252 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 172040711 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 172040711 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 172040711 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 172040711 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 3936 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 3936 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 21143 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 21143 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 25079 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 25079 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 25079 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 25079 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 123444000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 123444000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 700240500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 700240500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 74000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 74000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 823684500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 823684500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 823684500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 823684500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 90013130 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 90013130 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13547 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 13547 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 13252 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 13252 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 172065790 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 172065790 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 172065790 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 172065790 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31362.804878 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 31362.804878 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33119.259329 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 33119.259329 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 32843.594242 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 626 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 39.125000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1041 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2130 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2130 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18331 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 18331 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 20461 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 20461 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 20461 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 20461 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4618 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4618 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4618 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4618 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 58649500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 58649500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107455500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 107455500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166105000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 166105000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166105000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 166105000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32474.806202 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32474.806202 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38213.193457 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38213.193457 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 3978.553859 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 13166 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 5424 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 2.427360 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 368.225876 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2798.824975 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 811.503008 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.011237 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.085413 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.024765 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.121416 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 12759 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 297 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 13056 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 12759 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 314 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 13073 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 12759 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 314 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 13073 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3064 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1508 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4572 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 2796 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 2796 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3064 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 4304 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7368 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3064 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 4304 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7368 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107820500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 56418000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 164238500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104584000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 104584000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 107820500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 161002000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 268822500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 107820500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 161002000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 268822500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15823 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1805 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 17628 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1041 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1041 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2813 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 15823 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4618 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 20441 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 15823 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4618 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 20441 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.193642 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835457 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.259360 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993957 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.993957 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.193642 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.932005 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.360452 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.193642 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.932005 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.360452 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35189.458225 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37412.466844 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35922.681540 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37404.864092 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37404.864092 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35189.458225 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37407.527881 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 36485.138436 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35189.458225 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37407.527881 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 36485.138436 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 61 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3045 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1466 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4511 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2796 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 2796 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3045 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 4262 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7307 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3045 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 4262 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7307 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97703000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50497000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 148200000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95754500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95754500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97703000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146251500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 243954500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97703000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146251500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 243954500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812188 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255900 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.357468 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.357468 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32086.371100 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34445.429741 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32853.025937 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34246.959943 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34246.959943 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|