stats: update stats for cache occupancy and clock domain changes
This commit is contained in:
parent
cfc4a99982
commit
f3585c841e
552 changed files with 10549 additions and 54346 deletions
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@ -15,16 +15,16 @@ boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/scratch/nilay/GEM5/system/binaries/console
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console=/dist/binaries/console
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eventq_index=0
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init_param=0
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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kernel=/dist/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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pal=/dist/binaries/ts_osfpal
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readfile=tests/halt.sh
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symbolfile=
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system_rev=1024
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@ -175,6 +175,7 @@ mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu0.dcache.tags
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@ -191,6 +192,7 @@ block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu0.dtb]
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@ -520,6 +522,7 @@ mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu0.icache.tags
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@ -536,6 +539,7 @@ block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu0.interrupts]
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@ -545,6 +549,7 @@ eventq_index=0
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[system.cpu0.isa]
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type=AlphaISA
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eventq_index=0
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system=system
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[system.cpu0.itb]
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type=AlphaTLB
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@ -675,6 +680,7 @@ mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu1.dcache.tags
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@ -691,6 +697,7 @@ block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu1.dtb]
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@ -1020,6 +1027,7 @@ mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu1.icache.tags
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@ -1036,6 +1044,7 @@ block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu1.interrupts]
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@ -1045,6 +1054,7 @@ eventq_index=0
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[system.cpu1.isa]
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type=AlphaISA
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eventq_index=0
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system=system
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[system.cpu1.itb]
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type=AlphaTLB
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@ -1081,7 +1091,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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image_file=/dist/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -1104,7 +1114,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
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image_file=/dist/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -1138,6 +1148,7 @@ mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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response_latency=50
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sequential_access=false
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size=1024
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system=system
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tags=system.iocache.tags
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@ -1154,6 +1165,7 @@ block_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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hit_latency=50
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sequential_access=false
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size=1024
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[system.l2c]
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@ -1171,6 +1183,7 @@ mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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response_latency=20
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sequential_access=false
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size=4194304
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system=system
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tags=system.l2c.tags
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@ -1187,6 +1200,7 @@ block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=20
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sequential_access=false
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size=4194304
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[system.membus]
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@ -1267,7 +1281,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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eventq_index=0
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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image_file=/dist/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections
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warn: Sockets disabled, not accepting gdb connections
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warn: Prefetch instructions in Alpha do not do anything
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warn: Prefetch instructions in Alpha do not do anything
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hack: be nice to actually delete the event here
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@ -1,13 +1,13 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 15 2013 18:24:51
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gem5 started Oct 16 2013 01:34:33
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gem5 executing on zizzer
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gem5 compiled Jan 22 2014 16:27:55
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gem5 started Jan 22 2014 19:30:57
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gem5 executing on u200540-lin
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux
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info: kernel located at: /dist/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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info: Launching CPU 1 @ 125036000
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Exiting @ tick 1902738973500 because m5_exit instruction encountered
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info: Launching CPU 1 @ 126320000
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Exiting @ tick 1903338216000 because m5_exit instruction encountered
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@ -4,13 +4,15 @@ sim_seconds 1.903338 # Nu
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sim_ticks 1903338216000 # Number of ticks simulated
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final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 100362 # Simulator instruction rate (inst/s)
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host_op_rate 100362 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3404824916 # Simulator tick rate (ticks/s)
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host_mem_usage 359096 # Number of bytes of host memory used
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host_seconds 559.01 # Real time elapsed on the host
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host_inst_rate 150214 # Simulator instruction rate (inst/s)
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host_op_rate 150214 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5096064990 # Simulator tick rate (ticks/s)
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host_mem_usage 314972 # Number of bytes of host memory used
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host_seconds 373.49 # Real time elapsed on the host
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sim_insts 56103611 # Number of instructions simulated
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sim_ops 56103611 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory
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@ -421,6 +423,7 @@ system.membus.respLayer1.occupancy 3836772510 # La
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks)
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system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.l2c.tags.replacements 345713 # number of replacements
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system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use
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system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks.
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@ -438,6 +441,15 @@ system.l2c.tags.occ_percent::cpu0.data 0.085431 # Av
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system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy
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system.l2c.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::1 2154 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::2 5524 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::3 6881 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::4 50473 # Occupied blocks per task id
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system.l2c.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id
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system.l2c.tags.tag_accesses 27399611 # Number of tag accesses
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system.l2c.tags.data_accesses 27399611 # Number of data accesses
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system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits
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@ -732,6 +744,11 @@ system.iocache.tags.warmup_cycle 1712301131000 # C
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system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor
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system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy
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system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
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system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
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system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
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system.iocache.tags.tag_accesses 375543 # Number of tag accesses
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system.iocache.tags.data_accesses 375543 # Number of data accesses
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system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
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system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
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system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
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@ -1129,8 +1146,8 @@ system.cpu0.int_regfile_reads 59516377 # nu
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system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes
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system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads
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system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes
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system.cpu0.misc_regfile_reads 1526243 # number of misc regfile reads
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system.cpu0.misc_regfile_writes 747832 # number of misc regfile writes
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system.cpu0.misc_regfile_reads 1625466 # number of misc regfile reads
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system.cpu0.misc_regfile_writes 747841 # number of misc regfile writes
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system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
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system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
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system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
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@ -1275,6 +1292,13 @@ system.cpu0.icache.tags.warmup_cycle 26716185250 # Cy
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system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
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system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
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system.cpu0.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
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system.cpu0.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id
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system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
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system.cpu0.icache.tags.tag_accesses 7662265 # Number of tag accesses
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system.cpu0.icache.tags.data_accesses 7662265 # Number of data accesses
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system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits
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system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits
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system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits
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@ -1359,6 +1383,13 @@ system.cpu0.dcache.tags.warmup_cycle 25754000 # Cy
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system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu0.dcache.tags.tag_accesses 50559091 # Number of tag accesses
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system.cpu0.dcache.tags.data_accesses 50559091 # Number of data accesses
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system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits
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@ -1814,8 +1845,8 @@ system.cpu1.int_regfile_reads 18552962 # nu
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system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes
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system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads
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system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes
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system.cpu1.misc_regfile_reads 621722 # number of misc regfile reads
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system.cpu1.misc_regfile_writes 265027 # number of misc regfile writes
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system.cpu1.misc_regfile_reads 1024653 # number of misc regfile reads
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system.cpu1.misc_regfile_writes 265032 # number of misc regfile writes
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system.cpu1.icache.tags.replacements 316719 # number of replacements
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system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use
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system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks.
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@ -1825,6 +1856,12 @@ system.cpu1.icache.tags.warmup_cycle 49140510500 # Cy
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system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor
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system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy
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system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu1.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
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system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id
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system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu1.icache.tags.tag_accesses 2498600 # Number of tag accesses
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system.cpu1.icache.tags.data_accesses 2498600 # Number of data accesses
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system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits
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system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits
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system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits
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@ -1909,6 +1946,12 @@ system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cy
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system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor
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system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy
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system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy
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system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id
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system.cpu1.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id
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system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
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system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id
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system.cpu1.dcache.tags.tag_accesses 17217310 # Number of tag accesses
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system.cpu1.dcache.tags.data_accesses 17217310 # Number of data accesses
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system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits
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system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits
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system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits
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@ -15,16 +15,16 @@ boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/scratch/nilay/GEM5/system/binaries/console
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console=/dist/binaries/console
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eventq_index=0
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init_param=0
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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kernel=/dist/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
pal=/dist/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
@ -175,6 +175,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -191,6 +192,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -520,6 +522,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -536,6 +539,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -545,6 +549,7 @@ eventq_index=0
|
|||
[system.cpu.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
|
@ -566,6 +571,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -582,6 +588,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -625,7 +632,7 @@ table_size=65536
|
|||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
image_file=/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
@ -648,7 +655,7 @@ table_size=65536
|
|||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
@ -682,6 +689,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -698,6 +706,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
|
@ -778,7 +787,7 @@ system=system
|
|||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
image_file=/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
|
@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 15 2013 18:24:51
|
||||
gem5 started Oct 16 2013 01:34:33
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 19:25:00
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: kernel located at: /dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1860200687500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1860197780500 because m5_exit instruction encountered
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 1.860198 # Nu
|
|||
sim_ticks 1860197780500 # Number of ticks simulated
|
||||
final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 103834 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 103834 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3645751305 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355004 # Number of bytes of host memory used
|
||||
host_seconds 510.24 # Real time elapsed on the host
|
||||
host_inst_rate 153122 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 153122 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5376333902 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 310876 # Number of bytes of host memory used
|
||||
host_seconds 346.00 # Real time elapsed on the host
|
||||
sim_insts 52979882 # Number of instructions simulated
|
||||
sim_ops 52979882 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
|
||||
|
@ -417,6 +419,11 @@ system.iocache.tags.warmup_cycle 1710341603000 # C
|
|||
system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
||||
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
|
@ -521,6 +528,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu
|
|||
system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
@ -814,7 +822,7 @@ system.cpu.int_regfile_reads 73881277 # nu
|
|||
system.cpu.int_regfile_writes 40316653 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 166009 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 167434 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1986207 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 2028435 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
|
@ -952,6 +960,13 @@ system.cpu.icache.tags.warmup_cycle 26489829250 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 9566377 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 9566377 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits
|
||||
|
@ -1040,6 +1055,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.821654
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081017 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.094308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3492 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3315 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2416 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55452 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 26727370 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 26727370 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 995146 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 827013 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1822159 # number of ReadReq hits
|
||||
|
@ -1232,6 +1256,13 @@ system.cpu.dcache.tags.warmup_cycle 25477000 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 63738376 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 63738376 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7205308 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7205308 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4203634 # number of WriteReq hits
|
||||
|
|
|
@ -15,16 +15,16 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/scratch/nilay/GEM5/system/binaries/console
|
||||
console=/dist/binaries/console
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
|
||||
kernel=/dist/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
pal=/dist/binaries/ts_osfpal
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
@ -108,6 +108,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
|
@ -124,6 +125,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
@ -146,6 +148,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
|
@ -162,6 +165,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
|
@ -171,6 +175,7 @@ eventq_index=0
|
|||
[system.cpu0.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
|
@ -218,6 +223,7 @@ size=64
|
|||
[system.cpu1.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
|
@ -646,6 +652,7 @@ opLat=3
|
|||
[system.cpu2.isa]
|
||||
type=AlphaISA
|
||||
eventq_index=0
|
||||
system=system
|
||||
|
||||
[system.cpu2.itb]
|
||||
type=AlphaTLB
|
||||
|
@ -682,7 +689,7 @@ table_size=65536
|
|||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
image_file=/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
@ -705,7 +712,7 @@ table_size=65536
|
|||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
@ -739,6 +746,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -755,6 +763,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
|
@ -772,6 +781,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
|
@ -788,6 +798,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
|
@ -868,7 +879,7 @@ system=system
|
|||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
|
||||
image_file=/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -4,13 +4,15 @@ sim_seconds 1.842697 # Nu
|
|||
sim_ticks 1842697218000 # Number of ticks simulated
|
||||
final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 189301 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 189301 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4767309141 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 353980 # Number of bytes of host memory used
|
||||
host_seconds 386.53 # Real time elapsed on the host
|
||||
host_inst_rate 281851 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 281851 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7098045398 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 310872 # Number of bytes of host memory used
|
||||
host_seconds 259.61 # Real time elapsed on the host
|
||||
sim_insts 73170192 # Number of instructions simulated
|
||||
sim_ops 73170192 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
|
||||
|
@ -375,6 +377,7 @@ system.membus.respLayer1.occupancy 764298954 # La
|
|||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 337398 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks.
|
||||
|
@ -396,6 +399,15 @@ system.l2c.tags.occ_percent::cpu1.data 0.009495 # Av
|
|||
system.l2c.tags.occ_percent::cpu2.inst 0.032789 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.031610 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.998241 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 988 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 5636 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 2991 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 26143118 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 26143118 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.inst 520243 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 493553 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 124286 # number of ReadReq hits
|
||||
|
@ -676,6 +688,11 @@ system.iocache.tags.warmup_cycle 1694870354000 # C
|
|||
system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
||||
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
|
@ -1026,6 +1043,13 @@ system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490904
|
|||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194517 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312998 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 45349405 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 45349405 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 33358489 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 7831408 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 2239644 # number of ReadReq hits
|
||||
|
@ -1156,6 +1180,13 @@ system.cpu0.dcache.tags.occ_percent::cpu0.data 0.487132
|
|||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.257733 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255131 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 63261634 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 63261634 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 4082373 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 1085171 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu2.data 2396693 # number of ReadReq hits
|
||||
|
@ -1763,7 +1794,7 @@ system.cpu2.int_regfile_reads 42582766 # nu
|
|||
system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes
|
||||
system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads
|
||||
system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes
|
||||
system.cpu2.misc_regfile_reads 5347337 # number of misc regfile reads
|
||||
system.cpu2.misc_regfile_reads 5361637 # number of misc regfile reads
|
||||
system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes
|
||||
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
|
|
@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
@ -23,7 +23,7 @@ eventq_index=0
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
@ -75,7 +75,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
@ -288,6 +288,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -304,6 +305,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -643,6 +645,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -659,6 +662,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -713,6 +717,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -729,6 +734,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -782,6 +788,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -798,6 +805,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
|
@ -11,22 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented
|
|||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: 6117297500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 6125706500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 6160975500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 6176055500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6715294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: 6165886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
|
||||
warn: 6172734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 6181171500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 6216960500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 6232347500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6775306000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: 51807478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 51869237500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: 2474714862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2488540668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2489750451500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2510845218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2511359133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2517064152000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2517573704500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2518135055000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2518136146000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
hack: be nice to actually delete the event here
|
||||
warn: 2475417694000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2489281853500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2490491047500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2511643992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2512158375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2516381302500: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0
|
||||
warn: 2516399186500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10
|
||||
warn: 2517881609000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2518389750000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2518949430500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2518950618000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
warn: 2519498238000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:36:42
|
||||
gem5 started Oct 16 2013 02:31:27
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 23 2014 00:07:43
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2524309551500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2525131633500 because m5_exit instruction encountered
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 2.525132 # Nu
|
|||
sim_ticks 2525131633500 # Number of ticks simulated
|
||||
final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 41051 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52821 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1718892257 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 447424 # Number of bytes of host memory used
|
||||
host_seconds 1469.05 # Real time elapsed on the host
|
||||
host_inst_rate 63748 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 82026 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2669254242 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 403420 # Number of bytes of host memory used
|
||||
host_seconds 946.01 # Real time elapsed on the host
|
||||
sim_insts 60305678 # Number of instructions simulated
|
||||
sim_ops 77596684 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||
|
@ -928,6 +930,7 @@ system.iobus.respLayer0.occupancy 2374785000 # La
|
|||
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 14384927 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect
|
||||
|
@ -958,8 +961,8 @@ system.cpu.checker.dtb.inst_accesses 0 # IT
|
|||
system.cpu.checker.dtb.hits 26214250 # DTB hits
|
||||
system.cpu.checker.dtb.misses 9498 # DTB misses
|
||||
system.cpu.checker.dtb.accesses 26223748 # DTB accesses
|
||||
system.cpu.checker.itb.inst_hits 61479663 # ITB inst hits
|
||||
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.checker.itb.inst_hits 61479661 # ITB inst hits
|
||||
system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
|
||||
system.cpu.checker.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.checker.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.checker.itb.write_hits 0 # DTB write hits
|
||||
|
@ -968,7 +971,7 @@ system.cpu.checker.itb.flush_tlb 4 # Nu
|
|||
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
||||
system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.itb.flush_entries 4683 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
@ -976,8 +979,8 @@ system.cpu.checker.itb.perms_faults 0 # Nu
|
|||
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.checker.itb.inst_accesses 61484134 # ITB inst accesses
|
||||
system.cpu.checker.itb.hits 61479663 # DTB hits
|
||||
system.cpu.checker.itb.misses 4471 # DTB misses
|
||||
system.cpu.checker.itb.hits 61479661 # DTB hits
|
||||
system.cpu.checker.itb.misses 4473 # DTB misses
|
||||
system.cpu.checker.itb.accesses 61484134 # DTB accesses
|
||||
system.cpu.checker.numCycles 77882476 # number of cpu cycles simulated
|
||||
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
@ -1332,6 +1335,14 @@ system.cpu.icache.tags.warmup_cycle 6918450250 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits
|
||||
|
@ -1432,6 +1443,19 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6962 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54965 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18784884 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18784884 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits
|
||||
|
@ -1687,6 +1711,13 @@ system.cpu.dcache.tags.warmup_cycle 42430250 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits
|
||||
|
@ -1846,6 +1877,8 @@ system.iocache.tags.total_refs 0 # To
|
|||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 0 # Number of data accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
@ -23,7 +23,7 @@ eventq_index=0
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
@ -75,7 +75,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
@ -204,6 +204,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
|
@ -220,6 +221,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
@ -559,6 +561,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
|
@ -575,6 +578,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
|
@ -738,6 +742,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.dcache.tags
|
||||
|
@ -754,6 +759,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu1.dtb]
|
||||
|
@ -1093,6 +1099,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.icache.tags
|
||||
|
@ -1109,6 +1116,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
|
@ -1188,6 +1196,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -1204,6 +1213,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
|
@ -1221,6 +1231,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
|
@ -1237,6 +1248,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
|
@ -15,4 +14,3 @@ warn: instruction 'mcr bpiallis' unimplemented
|
|||
warn: LCD dual screen mode not supported
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:36:42
|
||||
gem5 started Oct 16 2013 02:18:35
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 23 2014 00:17:38
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1104038330000 because m5_exit instruction encountered
|
||||
Exiting @ tick 1104766159000 because m5_exit instruction encountered
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 1.104766 # Nu
|
|||
sim_ticks 1104766159000 # Number of ticks simulated
|
||||
final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49697 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 63978 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 891289209 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 450492 # Number of bytes of host memory used
|
||||
host_seconds 1239.51 # Real time elapsed on the host
|
||||
host_inst_rate 77156 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 99328 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1383749494 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 406496 # Number of bytes of host memory used
|
||||
host_seconds 798.39 # Real time elapsed on the host
|
||||
sim_insts 61600257 # Number of instructions simulated
|
||||
sim_ops 79301805 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
|
||||
|
@ -799,6 +801,7 @@ system.membus.respLayer1.occupancy 4838543340 # La
|
|||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 72740 # number of replacements
|
||||
system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks.
|
||||
|
@ -822,6 +825,18 @@ system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130
|
|||
system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65179 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 8680 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 53038 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.994553 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 18564692 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 18564692 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits
|
||||
|
@ -1696,8 +1711,8 @@ system.cpu0.int_regfile_reads 171854579 # nu
|
|||
system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes
|
||||
system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads
|
||||
system.cpu0.fp_regfile_writes 904 # number of floating regfile writes
|
||||
system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads
|
||||
system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes
|
||||
system.cpu0.misc_regfile_reads 13200315 # number of misc regfile reads
|
||||
system.cpu0.misc_regfile_writes 451289 # number of misc regfile writes
|
||||
system.cpu0.icache.tags.replacements 392190 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks.
|
||||
|
@ -1707,6 +1722,14 @@ system.cpu0.icache.tags.warmup_cycle 7054061250 # Cy
|
|||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 4608911 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 4608911 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits
|
||||
|
@ -1799,6 +1822,13 @@ system.cpu0.dcache.tags.warmup_cycle 43491250 # Cy
|
|||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 45150578 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 45150578 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits
|
||||
|
@ -2267,8 +2297,8 @@ system.cpu1.int_regfile_reads 384897666 # nu
|
|||
system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes
|
||||
system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads
|
||||
system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes
|
||||
system.cpu1.misc_regfile_reads 18454230 # number of misc regfile reads
|
||||
system.cpu1.misc_regfile_writes 405462 # number of misc regfile writes
|
||||
system.cpu1.misc_regfile_reads 18630847 # number of misc regfile reads
|
||||
system.cpu1.misc_regfile_writes 405526 # number of misc regfile writes
|
||||
system.cpu1.icache.tags.replacements 595825 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks.
|
||||
|
@ -2278,6 +2308,12 @@ system.cpu1.icache.tags.warmup_cycle 74918873000 # Cy
|
|||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id
|
||||
system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu1.icache.tags.tag_accesses 8173146 # Number of tag accesses
|
||||
system.cpu1.icache.tags.data_accesses 8173146 # Number of data accesses
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits
|
||||
|
@ -2370,6 +2406,11 @@ system.cpu1.dcache.tags.warmup_cycle 70967078000 # Cy
|
|||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.291027 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924397 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.924397 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
|
||||
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
|
||||
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
|
||||
system.cpu1.dcache.tags.tag_accesses 58866831 # Number of tag accesses
|
||||
system.cpu1.dcache.tags.data_accesses 58866831 # Number of data accesses
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 8309635 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 8309635 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 4139080 # number of WriteReq hits
|
||||
|
@ -2529,6 +2570,8 @@ system.iocache.tags.total_refs 0 # To
|
|||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 0 # Number of data accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
@ -23,7 +23,7 @@ eventq_index=0
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
@ -75,7 +75,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
@ -204,6 +204,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -220,6 +221,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -559,6 +561,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -575,6 +578,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -629,6 +633,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -645,6 +650,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -698,6 +704,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -714,6 +721,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
|
@ -14,4 +13,3 @@ warn: instruction 'mcr icimvau' unimplemented
|
|||
warn: LCD dual screen mode not supported
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:36:42
|
||||
gem5 started Oct 16 2013 02:15:54
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 23 2014 00:04:18
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2524309551500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2525131633500 because m5_exit instruction encountered
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 2.525132 # Nu
|
|||
sim_ticks 2525131633500 # Number of ticks simulated
|
||||
final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49653 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 63890 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2079077169 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 446400 # Number of bytes of host memory used
|
||||
host_seconds 1214.54 # Real time elapsed on the host
|
||||
host_inst_rate 76415 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 98325 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3199664494 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 402400 # Number of bytes of host memory used
|
||||
host_seconds 789.19 # Real time elapsed on the host
|
||||
sim_insts 60305678 # Number of instructions simulated
|
||||
sim_ops 77596684 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||
|
@ -928,6 +930,7 @@ system.iobus.respLayer0.occupancy 2374785000 # La
|
|||
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 14384927 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect
|
||||
|
@ -1287,6 +1290,14 @@ system.cpu.icache.tags.warmup_cycle 6918450250 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits
|
||||
|
@ -1387,6 +1398,19 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6962 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54965 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18784884 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18784884 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits
|
||||
|
@ -1642,6 +1666,13 @@ system.cpu.dcache.tags.warmup_cycle 42430250 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits
|
||||
|
@ -1801,6 +1832,8 @@ system.iocache.tags.total_refs 0 # To
|
|||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 0 # Number of data accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
@ -23,12 +23,12 @@ eventq_index=0
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
@ -75,7 +75,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
@ -137,6 +137,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
|
@ -153,6 +154,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
@ -185,6 +187,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
|
@ -201,6 +204,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
|
@ -819,6 +823,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -835,6 +840,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
|
@ -852,6 +858,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
|
@ -868,6 +875,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
|
|
|
@ -1,14 +1,12 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
|
@ -27,3 +25,5 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -4,25 +4,15 @@ sim_seconds 2.403659 # Nu
|
|||
sim_ticks 2403658742000 # Number of ticks simulated
|
||||
final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 141358 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 181555 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5632122143 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 447420 # Number of bytes of host memory used
|
||||
host_seconds 426.78 # Real time elapsed on the host
|
||||
host_inst_rate 228698 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 293732 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 9112018126 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 403420 # Number of bytes of host memory used
|
||||
host_seconds 263.79 # Real time elapsed on the host
|
||||
sim_insts 60328128 # Number of instructions simulated
|
||||
sim_ops 77483556 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
|
||||
|
@ -530,6 +520,18 @@ system.physmem.writeRowHitRate 88.14 # Ro
|
|||
system.physmem.avgGap 172554.83 # Average gap between requests
|
||||
system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55672581 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 13813538 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13813538 # Transaction distribution
|
||||
|
@ -566,6 +568,7 @@ system.membus.respLayer1.occupancy 1598779620 # La
|
|||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 63253 # number of replacements
|
||||
system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks.
|
||||
|
@ -597,6 +600,18 @@ system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015
|
|||
system.l2c.tags.occ_percent::cpu2.inst 0.025666 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.024115 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.768925 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65394 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 2645 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 6480 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 55890 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.997833 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 17683343 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 17683343 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 8706 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 3165 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 467858 # number of ReadReq hits
|
||||
|
@ -1235,6 +1250,14 @@ system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964278
|
|||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015011 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019937 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 158 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 45450915 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 45450915 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 31849634 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 8050768 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 3742157 # number of ReadReq hits
|
||||
|
@ -1365,6 +1388,13 @@ system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970753
|
|||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015892 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013350 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 98826136 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 98826136 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6861592 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 1819766 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu2.data 4641843 # number of ReadReq hits
|
||||
|
@ -1988,6 +2018,8 @@ system.iocache.tags.total_refs 0 # To
|
|||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 0 # Number of data accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
@ -23,7 +23,7 @@ eventq_index=0
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
@ -75,7 +75,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
@ -204,6 +204,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
|
@ -220,6 +221,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
@ -559,6 +561,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
|
@ -575,6 +578,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
|
@ -1114,6 +1118,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -1130,6 +1135,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
|
@ -1147,6 +1153,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
|
@ -1163,6 +1170,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
|
|
|
@ -1,14 +1,12 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
|
@ -17,9 +15,3 @@ warn: instruction 'mcr icialluis' unimplemented
|
|||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -4,13 +4,15 @@ sim_seconds 2.549345 # Nu
|
|||
sim_ticks 2549345168000 # Number of ticks simulated
|
||||
final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 48945 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 62980 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2068782078 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 448444 # Number of bytes of host memory used
|
||||
host_seconds 1232.29 # Real time elapsed on the host
|
||||
host_inst_rate 76720 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 98719 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3242754050 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 404480 # Number of bytes of host memory used
|
||||
host_seconds 786.17 # Real time elapsed on the host
|
||||
sim_insts 60314699 # Number of instructions simulated
|
||||
sim_ops 77609228 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
|
||||
|
@ -639,6 +641,7 @@ system.membus.respLayer1.occupancy 4736419263 # La
|
|||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 64357 # number of replacements
|
||||
system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks.
|
||||
|
@ -662,6 +665,18 @@ system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000207
|
|||
system.l2c.tags.occ_percent::cpu1.inst 0.051046 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.044272 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.785114 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65363 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 3051 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 6862 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 55068 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.997360 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 18937227 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 18937227 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 32950 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 7107 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 506567 # number of ReadReq hits
|
||||
|
@ -1517,6 +1532,13 @@ system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915
|
|||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 12566622 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 12566622 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 5233615 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 5282125 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 10515740 # number of ReadReq hits
|
||||
|
@ -1644,6 +1666,13 @@ system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.286930
|
|||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497473 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502514 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 101674783 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 101674783 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6830201 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 6949651 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 13779852 # number of ReadReq hits
|
||||
|
@ -2200,6 +2229,8 @@ system.iocache.tags.total_refs 0 # To
|
|||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 0 # Number of data accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=256
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
@ -23,12 +23,12 @@ eventq_index=0
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
@ -75,7 +75,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
@ -130,6 +130,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
|
@ -146,6 +147,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
@ -178,6 +180,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
|
@ -194,6 +197,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
|
@ -352,6 +356,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -368,6 +373,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
|
@ -385,6 +391,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
|
@ -401,6 +408,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
|
|
|
@ -1,12 +1,10 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: The ccsidr register isn't implemented and always reads as 0.
|
||||
hack: be nice to actually delete the event here
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
|
@ -33,3 +31,13 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -4,25 +4,15 @@ sim_seconds 2.629717 # Nu
|
|||
sim_ticks 2629717216500 # Number of ticks simulated
|
||||
final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 340896 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 433786 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 14888327014 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 445372 # Number of bytes of host memory used
|
||||
host_seconds 176.63 # Real time elapsed on the host
|
||||
host_inst_rate 592417 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 753843 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25873243563 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401372 # Number of bytes of host memory used
|
||||
host_seconds 101.64 # Real time elapsed on the host
|
||||
sim_insts 60212334 # Number of instructions simulated
|
||||
sim_ops 76619433 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory
|
||||
|
@ -509,6 +499,18 @@ system.physmem.writeRowHitRate 85.11 # Ro
|
|||
system.physmem.avgGap 159351.16 # Average gap between requests
|
||||
system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 54426353 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 16743636 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 16743636 # Transaction distribution
|
||||
|
@ -553,6 +555,7 @@ system.membus.respLayer1.occupancy 4990533473 # La
|
|||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 62046 # number of replacements
|
||||
system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks.
|
||||
|
@ -574,6 +577,15 @@ system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000
|
|||
system.l2c.tags.occ_percent::cpu1.inst 0.065179 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.049955 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 17277508 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 17277508 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 9827 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 412393 # number of ReadReq hits
|
||||
|
@ -1124,6 +1136,14 @@ system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.610060
|
|||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424303 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573457 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.997760 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 62363171 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 62363171 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 30192721 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 30456964 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 60649685 # number of ReadReq hits
|
||||
|
@ -1246,6 +1266,13 @@ system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.082879
|
|||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360927 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638834 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999760 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 97784680 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 97784680 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6519451 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 6679636 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 13199087 # number of ReadReq hits
|
||||
|
@ -1503,6 +1530,8 @@ system.iocache.tags.total_refs 0 # To
|
|||
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 0 # Number of data accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
|
@ -20,7 +20,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
|
@ -211,6 +211,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -227,6 +228,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -259,6 +261,7 @@ mshrs=10
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.cpu.dtb_walker_cache.tags
|
||||
|
@ -275,6 +278,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.cpu.fuPool]
|
||||
|
@ -599,6 +603,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -615,6 +620,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -663,6 +669,7 @@ mshrs=10
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.cpu.itb_walker_cache.tags
|
||||
|
@ -679,6 +686,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
@ -696,6 +704,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -712,6 +721,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -1178,6 +1188,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -1194,6 +1205,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.membus]
|
||||
|
@ -1523,7 +1535,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
@ -1546,7 +1558,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
warn: add_child('terminal'): child 'terminal' already has parent
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
@ -10,4 +9,3 @@ warn: x86 cpuid: unimplemented function 8
|
|||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:35:57
|
||||
gem5 started Oct 16 2013 01:57:32
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 22:15:55
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5149801602000 because m5_exit instruction encountered
|
||||
Exiting @ tick 5133933067000 because m5_exit instruction encountered
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 5.133933 # Nu
|
|||
sim_ticks 5133933067000 # Number of ticks simulated
|
||||
final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 121984 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 241126 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1535878817 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 781700 # Number of bytes of host memory used
|
||||
host_seconds 3342.67 # Real time elapsed on the host
|
||||
host_inst_rate 186687 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 369023 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2350538489 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 736008 # Number of bytes of host memory used
|
||||
host_seconds 2184.15 # Real time elapsed on the host
|
||||
sim_insts 407751929 # Number of instructions simulated
|
||||
sim_ops 806002693 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
|
@ -473,6 +475,11 @@ system.iocache.tags.warmup_cycle 4992951939000 # C
|
|||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 428679 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 428679 # Number of data accesses
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
|
@ -670,6 +677,7 @@ system.iobus.respLayer1.occupancy 53080252 # La
|
|||
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 85602749 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect
|
||||
|
@ -679,6 +687,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu
|
|||
system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions.
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.numCycles 453810576 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
@ -986,6 +995,13 @@ system.cpu.icache.tags.warmup_cycle 147611306250 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 9447804 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 9447804 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits
|
||||
|
@ -1070,6 +1086,13 @@ system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500
|
|||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.004704 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375294 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.375294 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
||||
system.cpu.itb_walker_cache.tags.tag_accesses 70243 # Number of tag accesses
|
||||
system.cpu.itb_walker_cache.tags.data_accesses 70243 # Number of data accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20415 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 20415 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
|
@ -1154,6 +1177,13 @@ system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000
|
|||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 390650 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 390650 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits
|
||||
|
@ -1234,6 +1264,13 @@ system.cpu.dcache.tags.warmup_cycle 39724250 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 87846935 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 87846935 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits
|
||||
|
@ -1362,6 +1399,15 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045815 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.167251 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989141 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63963 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 514 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3380 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54576 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975998 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 34635418 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 34635418 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64096 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7642 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 942107 # number of ReadReq hits
|
||||
|
|
|
@ -20,7 +20,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
|
@ -968,7 +968,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
@ -991,7 +991,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
warn: add_child('terminal'): child 'terminal' already has parent
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
@ -10,4 +9,3 @@ warn: x86 cpuid: unknown family 0x8086
|
|||
hack: Assuming logical destinations are 1 << id.
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:55:52
|
||||
gem5 started Oct 16 2013 01:57:05
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
|
||||
gem5 compiled Jan 22 2014 17:16:50
|
||||
gem5 started Jan 22 2014 22:26:32
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5304492233500 because m5_exit instruction encountered
|
||||
Exiting @ tick 5300435735500 because m5_exit instruction encountered
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 5.300436 # Nu
|
|||
sim_ticks 5300435735500 # Number of ticks simulated
|
||||
final_tick 5300435735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 127150 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 243807 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6308537728 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 832728 # Number of bytes of host memory used
|
||||
host_seconds 840.20 # Real time elapsed on the host
|
||||
host_inst_rate 165870 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 318050 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8229583651 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 786300 # Number of bytes of host memory used
|
||||
host_seconds 644.07 # Real time elapsed on the host
|
||||
sim_insts 106831806 # Number of instructions simulated
|
||||
sim_ops 204847037 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory
|
||||
|
@ -364,6 +366,7 @@ system.piobus.respLayer3.occupancy 151500 # La
|
|||
system.piobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer4.occupancy 151500 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.ruby.clk_domain.clock 500 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 2 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 19 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 10855755 # delay histogram for all message
|
||||
|
@ -489,6 +492,7 @@ system.ruby.network.routers2.msg_bytes.Response_Control::2 14052096
|
|||
system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41308992
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867440
|
||||
system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 317877 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 175365 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 142512 # Number of memory writes
|
||||
|
@ -566,6 +570,8 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
|
|||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu0.numCycles 10600871471 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
@ -592,6 +598,7 @@ system.cpu0.not_idle_fraction 0.048149 # Pe
|
|||
system.cpu0.idle_fraction 0.951851 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu1.numCycles 10598039537 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
|
|
@ -20,7 +20,7 @@ eventq_index=0
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
|
@ -144,6 +144,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.dcache.tags
|
||||
|
@ -160,6 +161,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
@ -192,6 +194,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.icache.tags
|
||||
|
@ -208,6 +211,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
|
@ -1205,6 +1209,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
system=system
|
||||
tags=system.iocache.tags
|
||||
|
@ -1221,6 +1226,7 @@ block_size=64
|
|||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
[system.l2c]
|
||||
|
@ -1238,6 +1244,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
|
@ -1254,6 +1261,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
|
@ -1583,7 +1591,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
@ -1606,7 +1614,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
@ -1,9 +1,7 @@
|
|||
warn: add_child('terminal'): child 'terminal' already has parent
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
hack: be nice to actually delete the event here
|
||||
warn: x86 cpuid: unknown family 0xbacc
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -4,13 +4,15 @@ sim_seconds 5.137456 # Nu
|
|||
sim_ticks 5137456264000 # Number of ticks simulated
|
||||
final_tick 5137456264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 176189 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 350219 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3709429360 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 1030148 # Number of bytes of host memory used
|
||||
host_seconds 1384.97 # Real time elapsed on the host
|
||||
host_inst_rate 293296 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 582999 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6174974039 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 983548 # Number of bytes of host memory used
|
||||
host_seconds 831.98 # Real time elapsed on the host
|
||||
sim_insts 244016231 # Number of instructions simulated
|
||||
sim_ops 485043652 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2422400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 383808 # Number of bytes read from this memory
|
||||
|
@ -444,6 +446,7 @@ system.membus.respLayer2.occupancy 1658568572 # La
|
|||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer4.occupancy 223775499 # Layer occupancy (ticks)
|
||||
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 103968 # number of replacements
|
||||
system.l2c.tags.tagsinuse 64819.095791 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 3669692 # Total number of references to valid blocks.
|
||||
|
@ -471,6 +474,15 @@ system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015
|
|||
system.l2c.tags.occ_percent::cpu2.inst 0.020633 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.071328 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.989061 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 64275 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 7385 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 52859 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.980759 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 33713228 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 33713228 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 21716 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 11486 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 326601 # number of ReadReq hits
|
||||
|
@ -855,6 +867,11 @@ system.iocache.tags.warmup_cycle 5000213887009 # C
|
|||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092731 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005796 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.005796 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 428661 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 428661 # Number of data accesses
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
|
@ -1070,6 +1087,7 @@ system.iobus.respLayer1.occupancy 29747501 # La
|
|||
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer2.occupancy 957000 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu0.numCycles 1152461068 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
@ -1109,6 +1127,13 @@ system.cpu0.icache.tags.occ_percent::cpu0.inst 0.593342
|
|||
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.263409 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.140938 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.997689 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 130343050 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 130343050 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 87032678 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 38704601 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 2869740 # number of ReadReq hits
|
||||
|
@ -1239,6 +1264,13 @@ system.cpu0.dcache.tags.occ_percent::cpu0.data 0.392288
|
|||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.594149 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013563 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 88202622 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 88202622 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 5007486 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 2456211 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu2.data 4066814 # number of ReadReq hits
|
||||
|
|
|
@ -159,6 +159,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -175,6 +176,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -514,6 +516,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -530,6 +533,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -584,6 +588,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -600,6 +605,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -626,9 +632,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:36:42
|
||||
gem5 started Oct 16 2013 01:59:02
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 22 2014 22:37:28
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
@ -23,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 26877484000 because target called exit()
|
||||
Exiting @ tick 26911413000 because target called exit()
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.026911 # Nu
|
|||
sim_ticks 26911413000 # Number of ticks simulated
|
||||
final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 116759 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 117598 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34685583 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 427272 # Number of bytes of host memory used
|
||||
host_seconds 775.87 # Real time elapsed on the host
|
||||
host_inst_rate 180996 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 182296 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53768206 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 381936 # Number of bytes of host memory used
|
||||
host_seconds 500.51 # Real time elapsed on the host
|
||||
sim_insts 90589798 # Number of instructions simulated
|
||||
sim_ops 91240351 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 993152 # Number of bytes read from this memory
|
||||
|
@ -303,6 +305,7 @@ system.membus.reqLayer0.occupancy 19253000 # La
|
|||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 26686306 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect
|
||||
|
@ -648,6 +651,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 732 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.357422 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 27691521 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 27691521 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits
|
||||
|
@ -736,6 +747,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.301529
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018879 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.327483 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1300 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13618 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.473053 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15189018 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15189018 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 903618 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 903642 # number of ReadReq hits
|
||||
|
@ -893,6 +913,13 @@ system.cpu.dcache.tags.warmup_cycle 8006035000 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 448 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3128 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 59988680 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 59988680 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
|
|||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
@ -108,18 +117,21 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -129,9 +141,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -143,11 +156,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -160,6 +175,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -169,5 +185,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:18:17
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 22 2014 22:39:34
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.054241 # Nu
|
|||
sim_ticks 54240661000 # Number of ticks simulated
|
||||
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2267620 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2283902 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1357548360 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 366572 # Number of bytes of host memory used
|
||||
host_seconds 39.95 # Real time elapsed on the host
|
||||
host_inst_rate 2327254 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2343964 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1393249116 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 371180 # Number of bytes of host memory used
|
||||
host_seconds 38.93 # Real time elapsed on the host
|
||||
sim_insts 90602407 # Number of instructions simulated
|
||||
sim_ops 91252960 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory
|
||||
|
@ -36,6 +38,7 @@ system.physmem.bw_total::total 9960199711 # To
|
|||
system.membus.throughput 9960199711 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 540247816 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
@ -71,6 +76,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -79,6 +85,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -93,18 +100,22 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
@ -115,6 +126,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -123,6 +135,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -137,14 +150,18 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
@ -163,12 +180,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
@ -179,6 +198,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
@ -187,6 +207,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -201,12 +222,15 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -225,9 +250,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -239,11 +265,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -256,6 +284,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -265,5 +294,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 09:24:43
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 22 2014 22:40:24
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.147136 # Nu
|
|||
sim_ticks 147135976000 # Number of ticks simulated
|
||||
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 529408 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 533204 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 859987474 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 373720 # Number of bytes of host memory used
|
||||
host_seconds 171.09 # Real time elapsed on the host
|
||||
host_inst_rate 1334589 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1344158 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2167949307 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 379884 # Number of bytes of host memory used
|
||||
host_seconds 67.87 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91226312 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
|
||||
|
@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 15340000 # La
|
|||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
@ -116,6 +119,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 215662141 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
|
||||
|
@ -198,6 +209,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.270902
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15179780 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits
|
||||
|
@ -330,6 +350,14 @@ system.cpu.dcache.tags.warmup_cycle 54472394000 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1322 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2583 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 55531122 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55531122 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
@ -74,20 +79,25 @@ icache_port=system.membus.slave[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -97,9 +107,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/sparc/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -111,11 +122,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -128,6 +141,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -137,5 +151,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,3 +1 @@
|
|||
warn: CoherentBus system.membus has no snooping ports attached!
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 22 2013 06:07:13
|
||||
gem5 started Sep 22 2013 06:07:55
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:04:27
|
||||
gem5 started Jan 22 2014 19:41:52
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.122216 # Nu
|
|||
sim_ticks 122215823500 # Number of ticks simulated
|
||||
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2226348 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2226440 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1115942635 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 357000 # Number of bytes of host memory used
|
||||
host_seconds 109.52 # Real time elapsed on the host
|
||||
host_inst_rate 3086610 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3086737 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1547143112 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 361240 # Number of bytes of host memory used
|
||||
host_seconds 78.99 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory
|
||||
|
@ -38,6 +40,7 @@ system.physmem.bw_total::total 11438503207 # To
|
|||
system.membus.throughput 11438757576 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 1397997177 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 244431648 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
@ -71,6 +76,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -79,6 +85,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -93,11 +100,14 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
|
@ -106,6 +116,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -114,6 +125,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -128,17 +140,22 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.l2cache]
|
||||
|
@ -147,6 +164,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
@ -155,6 +173,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -169,12 +188,15 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -193,9 +216,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/sparc/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -207,11 +231,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -224,6 +250,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -233,5 +260,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 22 2013 06:07:13
|
||||
gem5 started Sep 22 2013 06:07:47
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:04:27
|
||||
gem5 started Jan 22 2014 19:43:22
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.361489 # Nu
|
|||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 810264 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 810297 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1201274596 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 365008 # Number of bytes of host memory used
|
||||
host_seconds 300.92 # Real time elapsed on the host
|
||||
host_inst_rate 1454320 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1454380 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2156135283 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 371132 # Number of bytes of host memory used
|
||||
host_seconds 167.66 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
|
||||
|
@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 15603000 # La
|
|||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 722977060 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
@ -74,6 +77,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
|
||||
|
@ -156,6 +167,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.270009
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
|
||||
|
@ -288,6 +308,14 @@ system.cpu.dcache.tags.warmup_cycle 134366265000 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
||||
|
|
|
@ -165,6 +165,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -181,6 +182,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -520,6 +522,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -536,6 +539,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -584,6 +588,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -600,6 +605,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -626,9 +632,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:35:57
|
||||
gem5 started Oct 16 2013 01:42:09
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 19:53:01
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
@ -16,12 +16,12 @@ All Rights Reserved.
|
|||
nodes : 500
|
||||
active arcs : 1905
|
||||
simplex iterations : 1502
|
||||
info: Increasing stack size by one page.
|
||||
flow value : 4990014995
|
||||
new implicit arcs : 23867
|
||||
active arcs : 25772
|
||||
simplex iterations : 2663
|
||||
info: Increasing stack size by one page.
|
||||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 65497052500 because target called exit()
|
||||
Exiting @ tick 65613727000 because target called exit()
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.065614 # Nu
|
|||
sim_ticks 65613727000 # Number of ticks simulated
|
||||
final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72100 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 126957 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29943715 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 436724 # Number of bytes of host memory used
|
||||
host_seconds 2191.24 # Real time elapsed on the host
|
||||
host_inst_rate 111661 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 196618 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46373693 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 390932 # Number of bytes of host memory used
|
||||
host_seconds 1414.89 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory
|
||||
|
@ -300,6 +302,7 @@ system.membus.reqLayer0.occupancy 34950500 # La
|
|||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 33859770 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect
|
||||
|
@ -309,6 +312,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu
|
|||
system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions.
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 131227460 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
@ -599,6 +603,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 867 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 51151797 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 51151797 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits
|
||||
|
@ -687,6 +699,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.607028
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020463 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007473 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.634964 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29922 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27646 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913147 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33268796 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33268796 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1993866 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1993883 # number of ReadReq hits
|
||||
|
@ -821,6 +842,13 @@ system.cpu.dcache.tags.warmup_cycle 20690834250 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 593 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3349 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 150351466 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 150351466 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
@ -76,16 +81,19 @@ icache_port=system.membus.slave[1]
|
|||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
@ -93,6 +101,7 @@ port=system.membus.slave[4]
|
|||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
@ -103,22 +112,26 @@ pio=system.membus.master[1]
|
|||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -128,9 +141,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -142,11 +156,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -159,6 +175,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -168,5 +185,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:35:57
|
||||
gem5 started Oct 16 2013 01:43:36
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 20:16:46
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.168950 # Nu
|
|||
sim_ticks 168950040000 # Number of ticks simulated
|
||||
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1229454 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2164871 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1314755229 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 378084 # Number of bytes of host memory used
|
||||
host_seconds 128.50 # Real time elapsed on the host
|
||||
host_inst_rate 1603557 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2823605 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1714813271 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 379092 # Number of bytes of host memory used
|
||||
host_seconds 98.52 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory
|
||||
|
@ -36,6 +38,8 @@ system.physmem.bw_total::total 15992825110 # To
|
|||
system.membus.throughput 15992825110 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2701988442 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 337900081 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
@ -76,6 +82,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -84,6 +91,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -98,18 +106,22 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
@ -120,6 +132,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -128,6 +141,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -142,12 +156,15 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
@ -158,16 +175,19 @@ pio=system.membus.master[1]
|
|||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
@ -178,6 +198,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
@ -186,6 +207,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -200,12 +222,15 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -224,9 +250,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -238,11 +265,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -255,6 +284,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -264,5 +294,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:35:57
|
||||
gem5 started Oct 16 2013 01:48:06
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 20:18:36
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.365989 # Nu
|
|||
sim_ticks 365989065000 # Number of ticks simulated
|
||||
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 746941 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1315244 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1730329772 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 386536 # Number of bytes of host memory used
|
||||
host_seconds 211.51 # Real time elapsed on the host
|
||||
host_inst_rate 696180 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1225861 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1612738645 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388852 # Number of bytes of host memory used
|
||||
host_seconds 226.94 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
|
||||
|
@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy 30980000 # La
|
|||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 731978130 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
@ -86,6 +90,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
|
||||
|
@ -168,6 +179,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.589916
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
|
||||
|
@ -302,6 +322,14 @@ system.cpu.dcache.tags.warmup_cycle 126079701000 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
|
||||
|
|
|
@ -159,6 +159,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -175,6 +176,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -514,6 +516,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -530,6 +533,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -584,6 +588,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -600,6 +605,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -626,9 +632,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:36:42
|
||||
gem5 started Oct 16 2013 02:08:48
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 22 2014 22:41:42
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 202349747500 because target called exit()
|
||||
Exiting @ tick 202741893000 because target called exit()
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.202742 # Nu
|
|||
sim_ticks 202741893000 # Number of ticks simulated
|
||||
final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 95210 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 107343 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38205910 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298452 # Number of bytes of host memory used
|
||||
host_seconds 5306.56 # Real time elapsed on the host
|
||||
host_inst_rate 148118 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 166994 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59436990 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253144 # Number of bytes of host memory used
|
||||
host_seconds 3411.04 # Real time elapsed on the host
|
||||
sim_insts 505237723 # Number of instructions simulated
|
||||
sim_ops 569624283 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory
|
||||
|
@ -287,6 +289,7 @@ system.membus.reqLayer0.occupancy 1083331500 # La
|
|||
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 182821881 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect
|
||||
|
@ -631,6 +634,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1849 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 293 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.902832 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 229105594 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 229105594 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits
|
||||
|
@ -719,6 +731,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.702196
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31255 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7669 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21321 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953827 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 19093617 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 19093617 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits
|
||||
|
@ -878,6 +899,14 @@ system.cpu.dcache.tags.warmup_cycle 4256684250 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 391502938 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 391502938 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
|
|||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
@ -108,18 +117,21 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -129,9 +141,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -143,11 +156,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -160,6 +175,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -169,5 +185,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 09:00:02
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 22 2014 22:44:24
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.290499 # Nu
|
|||
sim_ticks 290498967000 # Number of ticks simulated
|
||||
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1591705 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1794011 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 912762441 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237748 # Number of bytes of host memory used
|
||||
host_seconds 318.26 # Real time elapsed on the host
|
||||
host_inst_rate 2346027 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2644207 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1345327991 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241300 # Number of bytes of host memory used
|
||||
host_seconds 215.93 # Real time elapsed on the host
|
||||
sim_insts 506581607 # Number of instructions simulated
|
||||
sim_ops 570968167 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory
|
||||
|
@ -36,6 +38,7 @@ system.physmem.bw_total::total 9312824252 # To
|
|||
system.membus.throughput 9312824252 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2705365825 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
@ -71,6 +76,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -79,6 +85,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -93,18 +100,22 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
@ -115,6 +126,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
|
@ -123,6 +135,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -137,14 +150,18 @@ type=LRU
|
|||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
|
@ -163,12 +180,14 @@ midr=890224640
|
|||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
@ -179,6 +198,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
|
@ -187,6 +207,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -201,12 +222,15 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
|
|||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -225,9 +250,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -239,11 +265,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -256,6 +284,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -265,5 +294,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 22 2013 07:58:15
|
||||
gem5 started Sep 22 2013 08:48:54
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:24:06
|
||||
gem5 started Jan 22 2014 22:45:59
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.717366 # Nu
|
|||
sim_ticks 717366012000 # Number of ticks simulated
|
||||
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1130634 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1274033 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1606137434 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243872 # Number of bytes of host memory used
|
||||
host_seconds 446.64 # Real time elapsed on the host
|
||||
host_inst_rate 1243497 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1401211 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1766466230 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251064 # Number of bytes of host memory used
|
||||
host_seconds 406.10 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
|
||||
|
@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 1006226000 # La
|
|||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
@ -124,6 +127,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
|
|||
system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
|
||||
|
@ -206,6 +218,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.713558
|
|||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits
|
||||
|
@ -340,6 +360,15 @@ system.cpu.dcache.tags.warmup_cycle 11885124000 # Cy
|
|||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
|
|
|
@ -165,6 +165,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
|
@ -181,6 +182,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
@ -520,6 +522,7 @@ mshrs=4
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
|
@ -536,6 +539,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
|
@ -584,6 +588,7 @@ mshrs=20
|
|||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
|
@ -600,6 +605,7 @@ block_size=64
|
|||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
@ -626,9 +632,9 @@ env=
|
|||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,28 +1,15 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:35:57
|
||||
gem5 started Oct 16 2013 02:08:50
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 20:22:33
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *********info: Increasing stack size by one page.
|
||||
**********************************info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
******
|
||||
****************************************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
|
@ -34,8 +21,18 @@ Processing sentences in batch mode
|
|||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
|
@ -75,9 +72,11 @@ Echoing of input sentence turned on.
|
|||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 458276279000 because target called exit()
|
||||
Exiting @ tick 459105675500 because target called exit()
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,7 +1,9 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
|
|||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
|
@ -45,6 +49,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
@ -76,16 +81,19 @@ icache_port=system.membus.slave[1]
|
|||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
@ -93,6 +101,7 @@ port=system.membus.slave[4]
|
|||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
|
@ -103,22 +112,26 @@ pio=system.membus.master[1]
|
|||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
@ -128,9 +141,10 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
eventq_index=0
|
||||
executable=/dist/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
@ -142,11 +156,13 @@ uid=100
|
|||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
eventq_index=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
@ -159,6 +175,7 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
|
@ -168,5 +185,6 @@ port=system.membus.master[0]
|
|||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
|
@ -1,2 +1 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 16 2013 01:35:57
|
||||
gem5 started Oct 16 2013 01:44:23
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 22 2014 17:10:34
|
||||
gem5 started Jan 22 2014 20:48:32
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
@ -4,13 +4,15 @@ sim_seconds 0.885229 # Nu
|
|||
sim_ticks 885229328000 # Number of ticks simulated
|
||||
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1293065 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2391022 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1384315331 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251216 # Number of bytes of host memory used
|
||||
host_seconds 639.47 # Real time elapsed on the host
|
||||
host_inst_rate 1633857 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3021184 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1749156833 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252248 # Number of bytes of host memory used
|
||||
host_seconds 506.09 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 2285655658 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10832432178 # Number of bytes read from this memory
|
||||
|
@ -36,6 +38,8 @@ system.physmem.bw_total::total 13357308966 # To
|
|||
system.membus.throughput 13357308966 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 11824281640 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1770458657 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue