1029 lines
116 KiB
Plaintext
1029 lines
116 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.202742 # Number of seconds simulated
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sim_ticks 202741893000 # Number of ticks simulated
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final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 148118 # Simulator instruction rate (inst/s)
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host_op_rate 166994 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 59436990 # Simulator tick rate (ticks/s)
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host_mem_usage 253144 # Number of bytes of host memory used
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host_seconds 3411.04 # Real time elapsed on the host
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sim_insts 505237723 # Number of instructions simulated
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sim_ops 569624283 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 148209 # Number of read requests accepted
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system.physmem.writeReqs 97655 # Number of write requests accepted
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system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9585 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9243 # Per bank write bursts
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system.physmem.perBankRdBursts::2 9257 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8972 # Per bank write bursts
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system.physmem.perBankRdBursts::4 9761 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9639 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9125 # Per bank write bursts
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system.physmem.perBankRdBursts::7 8321 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8799 # Per bank write bursts
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system.physmem.perBankRdBursts::9 8911 # Per bank write bursts
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system.physmem.perBankRdBursts::10 8951 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9736 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9644 # Per bank write bursts
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system.physmem.perBankRdBursts::13 9766 # Per bank write bursts
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system.physmem.perBankRdBursts::14 8945 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9461 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6262 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6160 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6087 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5881 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6253 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6276 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6048 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5555 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5811 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5907 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5994 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6518 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6370 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6328 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6055 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6145 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 202741873000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 148209 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 97655 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation
|
|
system.physmem.totQLat 1735354000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks
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|
system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.61 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 118629 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 57942 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 824609.84 # Average gap between requests
|
|
system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.membus.throughput 77612139 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 46927 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 46926 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 97655 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 9 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 101282 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 101282 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 15735232 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 182821881 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 405483787 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued
|
|
system.cpu.iq.rate 1.640858 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1558919 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 138505177 # Number of branches executed
|
|
system.cpu.iew.exec_stores 62475461 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.617619 # Inst execution rate
|
|
system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 374710129 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
|
|
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 182890032 # Number of memory references committed
|
|
system.cpu.commit.loads 126029555 # Number of loads committed
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
system.cpu.commit.branches 121548301 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 1104828701 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1548619548 # The number of ROB writes
|
|
system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
|
|
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 752019512 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 15017 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1849 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 293 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.902832 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 229105594 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 229105594 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 114523215 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 21116 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 115463 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 27089.747444 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1781862 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 146718 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 12.144808 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 23009.564484 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.930795 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 3719.252164 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31255 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7669 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21321 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953827 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 19093617 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 19093617 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1110997 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1110997 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 57 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 57 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 13491 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1051959 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1065450 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 13491 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1051959 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1065450 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3369 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 43584 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 46953 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3369 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 144867 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3369 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 144867 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 148236 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260130750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3496707000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3756837750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7547454999 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7547454999 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 260130750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11044161999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 11304292749 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 260130750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11044161999 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 11304292749 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 16860 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 847968 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 864828 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1110997 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1110997 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 65 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 65 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 348858 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 348858 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 16860 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1196826 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1213686 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 16860 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1196826 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1213686 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.199822 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051398 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.054292 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.123077 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.123077 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290327 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.290327 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199822 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.121043 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199822 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.121043 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77213.045414 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80229.143722 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80012.730816 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74518.477918 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74518.477918 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 76258.754614 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 76258.754614 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 97655 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 97655 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3364 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43563 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 46927 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3364 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 144846 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 148210 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3364 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 144846 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 148210 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 217499500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2949813250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3167312750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262853501 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262853501 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217499500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9212666751 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9430166251 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217499500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9212666751 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9430166251 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051373 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054262 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.123077 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.123077 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290327 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290327 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.122116 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.122116 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64655.023781 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67713.730689 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67494.464807 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1192730 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 391502938 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 391502938 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 187223724 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 4951929 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1110997 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|