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arch: Make all register index flattening const

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This patch makes all the register index flattening methods const for
all the ISAs. As part of this, readMiscRegNoEffect for ARM is also
made const.
This commit is contained in:
Andreas Hansson 2014-01-24 15:29:30 -06:00
parent 9633282fc8
commit cfc4a99982
7 changed files with 26 additions and 26 deletions
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8
src/arch/alpha/isa.hh
View file

@ -96,26 +96,26 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
int
flattenIntIndex(int reg)
flattenIntIndex(int reg) const
{
return reg;
}
int
flattenFloatIndex(int reg)
flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
flattenCCIndex(int reg)
flattenCCIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg)
flattenMiscIndex(int reg) const
{
return reg;
}

2
src/arch/arm/isa.cc
View file

@ -177,7 +177,7 @@ ISA::clear()
}
MiscReg
ISA::readMiscRegNoEffect(int misc_reg)
ISA::readMiscRegNoEffect(int misc_reg) const
{
assert(misc_reg < NumMiscRegs);

10
src/arch/arm/isa.hh
View file

@ -96,13 +96,13 @@ namespace ArmISA
public:
void clear();
MiscReg readMiscRegNoEffect(int misc_reg);
MiscReg readMiscRegNoEffect(int misc_reg) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
int
flattenIntIndex(int reg)
flattenIntIndex(int reg) const
{
assert(reg >= 0);
if (reg < NUM_ARCH_INTREGS) {
@ -135,20 +135,20 @@ namespace ArmISA
}
int
flattenFloatIndex(int reg)
flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
flattenCCIndex(int reg)
flattenCCIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg)
flattenMiscIndex(int reg) const
{
if (reg == MISCREG_SPSR) {
int spsr_idx = NUM_MISCREGS;

8
src/arch/mips/isa.hh
View file

@ -167,26 +167,26 @@ namespace MipsISA
ISA(Params *p);
int
flattenIntIndex(int reg)
flattenIntIndex(int reg) const
{
return reg;
}
int
flattenFloatIndex(int reg)
flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
flattenCCIndex(int reg)
flattenCCIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg)
flattenMiscIndex(int reg) const
{
return reg;
}

8
src/arch/power/isa.hh
View file

@ -87,26 +87,26 @@ class ISA : public SimObject
}
int
flattenIntIndex(int reg)
flattenIntIndex(int reg) const
{
return reg;
}
int
flattenFloatIndex(int reg)
flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
flattenCCIndex(int reg)
flattenCCIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg)
flattenMiscIndex(int reg) const
{
return reg;
}

8
src/arch/sparc/isa.hh
View file

@ -191,7 +191,7 @@ class ISA : public SimObject
ThreadContext *tc);
int
flattenIntIndex(int reg)
flattenIntIndex(int reg) const
{
assert(reg < TotalInstIntRegs);
RegIndex flatIndex = intRegMap[reg];
@ -200,20 +200,20 @@ class ISA : public SimObject
}
int
flattenFloatIndex(int reg)
flattenFloatIndex(int reg) const
{
return reg;
}
// dummy
int
flattenCCIndex(int reg)
flattenCCIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg)
flattenMiscIndex(int reg) const
{
return reg;
}

8
src/arch/x86/isa.hh
View file

@ -70,13 +70,13 @@ namespace X86ISA
void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
int
flattenIntIndex(int reg)
flattenIntIndex(int reg) const
{
return reg & ~IntFoldBit;
}
int
flattenFloatIndex(int reg)
flattenFloatIndex(int reg) const
{
if (reg >= NUM_FLOATREGS) {
reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
@ -86,13 +86,13 @@ namespace X86ISA
}
int
flattenCCIndex(int reg)
flattenCCIndex(int reg) const
{
return reg;
}
int
flattenMiscIndex(int reg)
flattenMiscIndex(int reg) const
{
return reg;
}