stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
This commit is contained in:
Andreas Hansson
parent
3bc4ecdcb4
commit
74553c7d3f
135 changed files with 52519 additions and 41496 deletions
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@ -1,121 +1,121 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.205149 # Number of seconds simulated
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sim_ticks 5205148879000 # Number of ticks simulated
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final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_ticks 5205149326500 # Number of ticks simulated
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final_tick 5205149326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 131600 # Simulator instruction rate (inst/s)
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host_op_rate 252290 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6421585329 # Simulator tick rate (ticks/s)
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host_mem_usage 872300 # Number of bytes of host memory used
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host_seconds 810.57 # Real time elapsed on the host
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sim_insts 106671342 # Number of instructions simulated
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sim_ops 204498751 # Number of ops (including micro ops) simulated
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host_inst_rate 156279 # Simulator instruction rate (inst/s)
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host_op_rate 299599 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7625516175 # Simulator tick rate (ticks/s)
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host_mem_usage 825184 # Number of bytes of host memory used
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host_seconds 682.60 # Real time elapsed on the host
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sim_insts 106675228 # Number of instructions simulated
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sim_ops 204505420 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 160408 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 562944184 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 41978278 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 62896 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 563007384 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 41989554 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 62960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 30152 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 448071240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 51341424 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1104699086 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 562944184 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 448071240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1011015424 # Number of instructions bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 448053480 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 51339228 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1104753734 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 563007384 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 448053480 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1011060864 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 33612947 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 34199698 # Number of bytes written to this memory
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system.physmem.bytes_written::total 70803765 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 33620576 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 34199208 # Number of bytes written to this memory
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system.physmem.bytes_written::total 70810904 # Number of bytes written to this memory
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system.physmem.num_reads::pc.south_bridge.ide 821 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 20043 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 20051 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 9416 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 70368023 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 6999506 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 7862 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 70375923 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 7001118 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 7870 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 3769 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 56008905 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 8662168 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 142080513 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 56006685 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 8661478 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 142087131 # Number of read requests responded to by this memory
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system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 5025316 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 4781707 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 9853761 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 5026389 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 4781632 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 9854759 # Number of write requests responded to by this memory
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system.physmem.bw_read::pc.south_bridge.ide 6770 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 30805 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 30817 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 14472 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 108151409 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 8064760 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 12083 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 108163541 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 8066926 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 12096 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 5793 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 86082310 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 9863584 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 212231986 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 108151409 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 86082310 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 194233719 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 86078891 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 9863161 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 212242467 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 108163541 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 86078891 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 194242432 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::pc.south_bridge.ide 574643 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6457634 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 6570359 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 13602640 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 581414 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 30805 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6459099 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 6570265 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 13604010 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 581413 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 30817 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 14475 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 108151409 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 14522394 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 12083 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 108163541 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 14526025 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 12096 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 5793 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 86082310 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 16433943 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 225834626 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 86078891 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 16433426 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 225846477 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 821 # Total number of read requests seen
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system.physmem.writeReqs 46736 # Total number of write requests seen
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system.physmem.cpureqs 47279 # Reqs generatd by CPU via cache - shady
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system.physmem.cpureqs 47259 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 52544 # Total number of bytes read from memory
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system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 35240 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 64 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 64 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::0 80 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 80 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 2992 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 2832 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 3024 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 2944 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 2992 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 2968 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 2992 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 2864 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 2896 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 2800 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 2960 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 2928 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::0 2816 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 2864 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 2640 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 2768 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 2768 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 3064 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 2648 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 3232 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 3312 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 3248 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 3024 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 2976 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 2672 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 2880 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 3008 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 31 # Number of times wr buffer was full causing retry
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system.physmem.totGap 64277169000 # Total gap between requests
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system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry
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system.physmem.totGap 64277565999 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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@ -162,15 +162,15 @@ system.physmem.rdQLenPdf::28 2 # Wh
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system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1997 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1997 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1997 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1997 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1998 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2010 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2020 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2020 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2020 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2020 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2020 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2020 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2021 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2021 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see
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@ -185,23 +185,66 @@ system.physmem.wrQLenPdf::19 2032 # Wh
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system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 58 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 35 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 35 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 41690522 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 53523022 # Sum of mem lat for all requests
|
||||
system.physmem.wrQLenPdf::23 22 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 539 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 5552.207792 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 3362.695639 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 3316.858883 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 30 5.57% 5.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 2 0.37% 5.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 6 1.11% 7.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-257 9 1.67% 8.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 2 0.37% 9.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 3 0.56% 9.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 1 0.19% 9.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-513 1 0.19% 10.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 1 0.19% 10.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-641 2 0.37% 10.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704-705 2 0.37% 10.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-769 1 0.19% 11.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832-833 2 0.37% 11.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-897 1 0.19% 11.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960-961 2 0.37% 12.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1025 69 12.80% 24.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088-1089 1 0.19% 25.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 3 0.56% 25.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 2 0.37% 25.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 2 0.37% 26.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1408-1409 1 0.19% 26.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536-1537 1 0.19% 26.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600-1601 1 0.19% 26.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2048-2049 11 2.04% 28.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2816-2817 1 0.19% 29.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3072-3073 9 1.67% 30.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3200-3201 1 0.19% 30.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3904-3905 1 0.19% 31.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3968-3969 1 0.19% 31.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4096-4097 41 7.61% 38.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5120-5121 6 1.11% 40.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5888-5889 1 0.19% 40.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6144-6145 4 0.74% 41.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6656-6657 1 0.19% 41.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7168-7169 5 0.93% 42.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7552-7553 1 0.19% 42.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7808-7809 1 0.19% 42.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 310 57.51% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 539 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 47710768 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 58058268 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 4105000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7727500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 50780.17 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 9412.30 # Average bank access latency per request
|
||||
system.physmem.totBankLat 6242500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 58112.99 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 7603.53 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 65192.48 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 70716.53 # Average memory access latency
|
||||
system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -210,11 +253,207 @@ system.physmem.peakBW 12800.00 # Th
|
|||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.15 # Average write queue length over time
|
||||
system.physmem.readRowHits 704 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 45223 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.75 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1351581.66 # Average gap between requests
|
||||
system.physmem.readRowHits 756 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 46262 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 92.08 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 98.99 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1351590.01 # Average gap between requests
|
||||
system.piobus.throughput 974238 # Throughput (bytes/s)
|
||||
system.piobus.trans_dist::ReadReq 863748 # Transaction distribution
|
||||
system.piobus.trans_dist::ReadResp 863748 # Transaction distribution
|
||||
system.piobus.trans_dist::WriteReq 83560 # Transaction distribution
|
||||
system.piobus.trans_dist::WriteResp 83560 # Transaction distribution
|
||||
system.piobus.trans_dist::MessageReq 1915 # Transaction distribution
|
||||
system.piobus.trans_dist::MessageResp 1915 # Transaction distribution
|
||||
system.piobus.pkt_count_system.pc.south_bridge.ide.dma::system.physmem.port 95114 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1680 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1624 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 6496 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 732 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 90 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1000 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 15614 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1714112 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 4730 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 632 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 31770 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 328 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 31858 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 10796 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 85390 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 330 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 330 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 196 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 196 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.physmem.port 95114 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11226 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pit.pio 31800 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1328 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.i_dont_exist.pio 31948 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.com_1.pio 26410 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu0.interrupts.int_slave 1876 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu1.interrupts.int_slave 1954 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::total 1898446 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 3698 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 366 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 45 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 7807 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1985488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3066 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 316 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 2 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 15885 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 15929 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 5398 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 51561 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 660 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 660 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6764 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15900 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 15974 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.com_1.pio 13205 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 3752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 3908 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::total 5071053 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.data_through_bus 5071053 # Total data (bytes)
|
||||
system.piobus.reqLayer0.occupancy 421750668 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer1.occupancy 46000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer3.occupancy 10348000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer5.occupancy 1063000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer6.occupancy 95500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer7.occupancy 56000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer8.occupancy 21210500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer9.occupancy 586857500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer10.occupancy 1290500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer11.occupancy 39914000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer13.occupancy 23057500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer18.occupancy 470748000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer19.occupancy 2244320 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer20.occupancy 5358000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer21.occupancy 2333580 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer22.occupancy 1074500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer0.occupancy 52258179 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer1.occupancy 2331400 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer2.occupancy 1919239500 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer3.occupancy 68175500 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer4.occupancy 210500 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.respLayer5.occupancy 121000 # Layer occupancy (ticks)
|
||||
system.piobus.respLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -227,12 +466,12 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
|
|||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 11503621 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 550662 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12054283 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 70015833 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 352190 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 70368023 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 11506236 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 550740 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12056976 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 70023521 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 352402 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 70375923 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
|
||||
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
|
||||
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
|
||||
|
|
@ -242,12 +481,12 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.l1_cntrl1.L1Dcache.demand_hits 12163827 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291679 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13455506 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl1.L1Icache.demand_hits 55549058 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl1.L1Icache.demand_misses 459847 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl1.L1Icache.demand_accesses 56008905 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl1.L1Dcache.demand_hits 12162992 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291757 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13454749 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl1.L1Icache.demand_hits 55546818 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl1.L1Icache.demand_misses 459867 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl1.L1Icache.demand_accesses 56006685 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
|
||||
system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
|
||||
system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
|
||||
|
|
@ -257,55 +496,55 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 2426575 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 227803 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 2654378 # Number of cache demand accesses
|
||||
system.cpu0.numCycles 10410297758 # number of cpu cycles simulated
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 2426890 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 227876 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 2654766 # Number of cache demand accesses
|
||||
system.cpu0.numCycles 10410298653 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 60288276 # Number of instructions committed
|
||||
system.cpu0.committedOps 115773079 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses
|
||||
system.cpu0.committedInsts 60294243 # Number of instructions committed
|
||||
system.cpu0.committedOps 115784968 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 108743289 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1065656 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 108731496 # number of integer instructions
|
||||
system.cpu0.num_func_calls 1066196 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 10278204 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 108743289 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 0 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 267473663 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 137108635 # number of times the integer registers were written
|
||||
system.cpu0.num_int_register_reads 267504308 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 137121782 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 12880520 # number of memory refs
|
||||
system.cpu0.num_load_insts 7843945 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5036575 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 9879714305.974102 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 530583452.025898 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.050967 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.949033 # Percentage of idle cycles
|
||||
system.cpu0.num_mem_refs 12883291 # number of memory refs
|
||||
system.cpu0.num_load_insts 7845612 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5037679 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 9879654975.894102 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 530643677.105898 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.050973 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.949027 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.numCycles 10407399002 # number of cpu cycles simulated
|
||||
system.cpu1.numCycles 10407399919 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 46383066 # Number of instructions committed
|
||||
system.cpu1.committedOps 88725672 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses
|
||||
system.cpu1.committedInsts 46380985 # Number of instructions committed
|
||||
system.cpu1.committedOps 88720452 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 85213748 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 1670749 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 85218419 # number of integer instructions
|
||||
system.cpu1.num_func_calls 1670555 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 7954622 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 85213748 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 0 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 213998429 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 102139748 # number of times the integer registers were written
|
||||
system.cpu1.num_int_register_reads 213988355 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 102135039 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 13480502 # number of memory refs
|
||||
system.cpu1.num_load_insts 8673583 # Number of load instructions
|
||||
system.cpu1.num_store_insts 4806919 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10081113907.619320 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 326285094.380681 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.031351 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.968649 # Percentage of idle cycles
|
||||
system.cpu1.num_mem_refs 13479662 # number of memory refs
|
||||
system.cpu1.num_load_insts 8672840 # Number of load instructions
|
||||
system.cpu1.num_store_insts 4806822 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10081140022.903200 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 326259896.096799 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.031349 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.968651 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,419 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.233778 # Number of seconds simulated
|
||||
sim_ticks 4467555024 # Number of ticks simulated
|
||||
final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3081772 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3082983 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6178737 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 519228 # Number of bytes of host memory used
|
||||
host_seconds 723.05 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
|
||||
system.physmem.num_other::total 14 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 0 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 0 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat nan # Average queueing delay per request
|
||||
system.physmem.avgBankLat nan # Average bank access latency per request
|
||||
system.physmem.avgBusLat nan # Average bus latency per request
|
||||
system.physmem.avgMemAccLat nan # Average memory access latency
|
||||
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 0 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap nan # Average gap between requests
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
|
||||
system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
|
||||
system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.readReqs 0 # Total number of read requests seen
|
||||
system.physmem2.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem2.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem2.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem2.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem2.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem2.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem2.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem2.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem2.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::2 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::3 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::4 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::5 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::6 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::7 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::8 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::9 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::10 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::11 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::12 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::13 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::14 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankRdReqs::15 0 # Track reads on a per bank basis
|
||||
system.physmem2.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::3 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::4 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::5 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::6 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::7 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::8 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::9 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::10 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::11 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::12 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::13 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::14 0 # Track writes on a per bank basis
|
||||
system.physmem2.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem2.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem2.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem2.totGap 0 # Total gap between requests
|
||||
system.physmem2.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem2.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem2.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem2.readPktSize::3 0 # Categorize read packet sizes
|
||||
system.physmem2.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem2.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem2.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem2.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem2.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem2.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem2.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem2.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem2.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem2.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem2.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem2.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem2.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem2.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem2.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem2.totBusLat 0 # Total cycles spent in databus access
|
||||
system.physmem2.totBankLat 0 # Total cycles spent in bank access
|
||||
system.physmem2.avgQLat nan # Average queueing delay per request
|
||||
system.physmem2.avgBankLat nan # Average bank access latency per request
|
||||
system.physmem2.avgBusLat nan # Average bus latency per request
|
||||
system.physmem2.avgMemAccLat nan # Average memory access latency
|
||||
system.physmem2.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
|
||||
system.physmem2.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem2.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
||||
system.physmem2.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem2.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem2.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem2.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem2.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem2.readRowHits 0 # Number of row buffer hits during reads
|
||||
system.physmem2.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem2.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem2.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem2.avgGap nan # Average gap between requests
|
||||
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
|
||||
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
|
||||
system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2228284650 # Number of instructions committed
|
||||
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1839325658 # number of integer instructions
|
||||
system.cpu.num_fp_insts 14608322 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 547951940 # number of memory refs
|
||||
system.cpu.num_load_insts 349807670 # Number of load instructions
|
||||
system.cpu.num_store_insts 198144270 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.269669 # Number of seconds simulated
|
||||
sim_ticks 269668883500 # Number of ticks simulated
|
||||
final_tick 269668883500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.269772 # Number of seconds simulated
|
||||
sim_ticks 269771922500 # Number of ticks simulated
|
||||
final_tick 269771922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49435 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 49435 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22150100 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271532 # Number of bytes of host memory used
|
||||
host_seconds 12174.61 # Real time elapsed on the host
|
||||
host_inst_rate 152624 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 152624 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68411173 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225196 # Number of bytes of host memory used
|
||||
host_seconds 3943.39 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu
|
|||
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 199593 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6040712 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6240305 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199593 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199593 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240651 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240651 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240651 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6040712 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6480955 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 199517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6038405 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6237921 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199517 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199517 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240559 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240559 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6038405 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6478480 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 26294 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1014 # Total number of write requests seen
|
||||
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by
|
|||
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 1672 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1579 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 1680 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 1732 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 1812 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 1867 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 1778 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 1658 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 1444 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 1431 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 1493 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 1505 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 63 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 49 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 70 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 71 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 70 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 79 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 64 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 89 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 33 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 38 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 48 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 269668831500 # Total gap between requests
|
||||
system.physmem.totGap 269771850500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 1014 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 16677 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6779 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1891 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 17534 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6823 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1475 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 445 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 40 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 45 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
|
||||
|
|
@ -147,8 +147,8 @@ system.physmem.wrQLenPdf::19 44 # Wh
|
|||
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
|
|
@ -156,14 +156,96 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 383236250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1095312500 # Sum of mem lat for all requests
|
||||
system.physmem.bytesPerActivate::samples 8692 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 200.548550 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 81.216882 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 827.235747 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 7745 89.10% 89.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 118 1.36% 90.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 74 0.85% 91.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-257 56 0.64% 91.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 40 0.46% 92.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 23 0.26% 92.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 20 0.23% 92.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-513 390 4.49% 97.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 4 0.05% 97.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-641 9 0.10% 97.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704-705 7 0.08% 97.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-769 6 0.07% 97.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832-833 2 0.02% 97.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-897 4 0.05% 97.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960-961 7 0.08% 97.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1025 4 0.05% 97.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088-1089 3 0.03% 97.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152-1153 2 0.02% 97.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 1 0.01% 97.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 9 0.10% 98.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1472-1473 4 0.05% 98.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1792-1793 3 0.03% 98.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1920-1921 3 0.03% 98.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1984-1985 4 0.05% 98.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2304-2305 3 0.03% 98.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2688-2689 2 0.02% 98.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2816-2817 2 0.02% 98.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2944-2945 2 0.02% 98.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3072-3073 4 0.05% 98.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3328-3329 2 0.02% 98.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3584-3585 2 0.02% 98.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4480-4481 2 0.02% 98.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4544-4545 3 0.03% 98.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4608-4609 1 0.01% 98.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4864-4865 3 0.03% 98.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5440-5441 2 0.02% 98.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5568-5569 1 0.01% 98.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5888-5889 2 0.02% 98.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5952-5953 1 0.01% 98.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6080-6081 1 0.01% 98.99% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6272-6273 2 0.02% 99.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6720-6721 4 0.05% 99.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6912-6913 2 0.02% 99.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7616-7617 1 0.01% 99.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7680-7681 44 0.51% 99.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7744-7745 9 0.10% 99.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7808-7809 5 0.06% 99.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 11 0.13% 99.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8576-8577 2 0.02% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 8692 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 332225750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 999160750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 131400000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 580676250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 14582.81 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 22095.75 # Average bank access latency per request
|
||||
system.physmem.totBankLat 535535000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 12641.77 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 20378.04 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 41678.56 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 38019.82 # Average memory access latency
|
||||
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -172,36 +254,52 @@ system.physmem.peakBW 12800.00 # Th
|
|||
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 12.19 # Average write queue length over time
|
||||
system.physmem.readRowHits 16315 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 296 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9875085.38 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 86401588 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81471319 # Number of conditional branches predicted
|
||||
system.physmem.readRowHits 18015 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 585 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 68.55 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 57.69 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9878857.86 # Average gap between requests
|
||||
system.membus.throughput 6478480 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4966 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4966 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1014 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 21328 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 21328 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 53602 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 53602 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1747712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 1747712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1747712 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 40219500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 248608250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 86401392 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81471121 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 45048223 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 34648139 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 45048026 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 34648141 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 76.913442 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 76.913783 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114517866 # DTB read hits
|
||||
system.cpu.dtb.read_hits 114525360 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114520497 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39453488 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 114527991 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39455215 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39455790 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153971354 # DTB hits
|
||||
system.cpu.dtb.write_accesses 39457517 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153980575 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 153976287 # DTB accesses
|
||||
system.cpu.dtb.data_accesses 153985508 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 24966979 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -219,34 +317,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 539337768 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 539543846 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 37213741 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49187847 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541069811 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 37213743 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49187649 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541069671 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1004924657 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1004924517 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 255160339 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 255160482 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 154930401 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412134920 # Number of Instructions Executed.
|
||||
system.cpu.execution_unit.executions 412134922 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 535759851 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 535782792 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 296128 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 50805895 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488531873 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.579949 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 294264 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 51002909 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488540937 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.547032 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
|
|
@ -258,124 +356,144 @@ system.cpu.committedInsts 601856964 # Nu
|
|||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.896123 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.896465 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.896123 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115918 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.896465 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115492 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.115918 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200608412 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338729356 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.804679 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 228909431 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310428337 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.557315 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197773731 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341564037 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.330265 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 427958956 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111378812 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.651031 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192540057 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346797711 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.300654 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.115492 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200810173 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338733673 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.781491 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 229113520 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310430326 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.535700 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197979216 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341564630 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.306186 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 428164340 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111379506 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.643272 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192742225 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346801621 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.276819 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 30 # number of replacements
|
||||
system.cpu.icache.tagsinuse 729.833568 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 24965946 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 729.672642 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 24965940 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29199.936842 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29199.929825 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.833568 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24965946 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24965946 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24965946 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24965946 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24965946 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24965946 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1033 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1033 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1033 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1033 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55677000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 55677000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 55677000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 55677000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 55677000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 55677000 # number of overall miss cycles
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.672642 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.356285 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.356285 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24965940 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24965940 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24965940 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24965940 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24965940 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24965940 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1039 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 73110500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 73110500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 73110500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 73110500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 73110500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 73110500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24966979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24966979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24966979 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24966979 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24966979 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24966979 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53898.354308 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53898.354308 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70366.217517 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70366.217517 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70366.217517 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70366.217517 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 267 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 133.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 178 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 178 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 178 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 178 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 178 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 184 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 184 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 184 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 184 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45946500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 45946500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45946500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 45946500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45946500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 45946500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 60213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60213000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 60213000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60213000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 60213000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53738.596491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53738.596491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70424.561404 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70424.561404 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 211885535 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 202062 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 202062 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 254188 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 254188 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1710 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1349387 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 57160768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 57160768 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 883455500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1282500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 683092999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 1042 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22879.137372 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 22873.227488 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21684.500481 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.953671 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 475.683220 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21678.205650 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.794355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 476.227482 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.661566 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021936 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014533 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698036 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
|
||||
|
|
@ -400,17 +518,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44941500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470659500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 515601000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1197956000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1197956000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 44941500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1668615500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1713557000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 44941500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1668615500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1713557000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59208000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 554748000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 613956000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1528945500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1528945500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 59208000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 2083693500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 2142901500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 59208000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 2083693500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 2142901500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -435,17 +553,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53438.168847 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.272727 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103826.218284 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56168.229557 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56168.229557 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65169.126036 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65169.126036 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70401.902497 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 134484.363636 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 123631.896899 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71687.242123 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71687.242123 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81497.737126 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81497.737126 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -467,17 +585,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34505688 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418277231 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452782919 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932478797 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932478797 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34505688 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350756028 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1385261716 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34505688 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350756028 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1385261716 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48784500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 502370250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 551154750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1264256500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1264256500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48784500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1766626750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1815411250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48784500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1766626750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1815411250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -489,51 +607,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41029.355529 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.540848 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91176.584575 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43720.873828 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43720.873828 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58007.728894 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 121786.727273 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 110985.652437 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59276.842648 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59276.842648 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.423663 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786149 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4093.048176 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151792699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 333.306578 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.423663 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120800 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120800 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37665349 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37665349 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151786149 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151786149 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151786149 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151786149 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393242 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393242 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1785972 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1785972 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2179214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2179214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2179214 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2179214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984700000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5984700000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23169621500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23169621500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29154321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29154321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29154321500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29154321500 # number of overall miss cycles
|
||||
system.cpu.dcache.avg_refs 333.320961 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 382930000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.048176 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114127941 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114127941 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37664758 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37664758 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151792699 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151792699 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151792699 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151792699 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 386101 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 386101 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1786563 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1786563 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2172664 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2172664 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2172664 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2172664 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6056986500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6056986500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25183645000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25183645000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31240631500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31240631500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31240631500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31240631500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -542,40 +660,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 #
|
|||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15218.872857 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15218.872857 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.115760 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.115760 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 191067 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6052 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.570886 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003372 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003372 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045285 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.045285 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014111 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014111 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014111 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014111 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15687.570092 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15687.570092 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14096.141586 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 14096.141586 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14378.952061 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14378.952061 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 376840 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 954 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 17814 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.154148 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 95.400000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436887 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192010 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192010 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531809 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1531809 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1723819 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1723819 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1723819 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1723819 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 184869 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 184869 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1532400 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1532400 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1717269 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1717269 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1717269 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1717269 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
|
|
@ -584,14 +702,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643678500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643678500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782203500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782203500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6425882000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6425882000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6425882000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6425882000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2727636001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2727636001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4113048000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4113048000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6840684001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6840684001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6840684001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6840684001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -600,14 +718,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.465711 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.465711 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.015333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.015333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13554.683157 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13554.683157 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16182.717390 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16182.717390 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.300931 # Nu
|
|||
sim_ticks 300930958000 # Number of ticks simulated
|
||||
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2641824 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2641824 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1320922836 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264040 # Number of bytes of host memory used
|
||||
host_seconds 227.82 # Real time elapsed on the host
|
||||
host_inst_rate 3984763 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3984763 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1992397518 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217612 # Number of bytes of host memory used
|
||||
host_seconds 151.04 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 507324022 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9755262308 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2935660432 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.762403 # Nu
|
|||
sim_ticks 762403375000 # Number of ticks simulated
|
||||
final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1151537 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1151537 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1458711281 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272496 # Number of bytes of host memory used
|
||||
host_seconds 522.66 # Real time elapsed on the host
|
||||
host_inst_rate 1417339 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1417339 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1795416637 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225056 # Number of bytes of host memory used
|
||||
host_seconds 424.64 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 84449 # To
|
|||
system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 2286664 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4910 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4910 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1006 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 21324 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 21324 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 53474 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 53474 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1743360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 1743360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1743360 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 35288000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 236106000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 74969406 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 202027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 202027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 254163 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 254163 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1590 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1349267 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 57156928 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 57156928 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 883425500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1192500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 683092500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu
|
|||
sim_ticks 301191365000 # Number of ticks simulated
|
||||
final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1714897 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1812090 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 906079333 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278712 # Number of bytes of host memory used
|
||||
host_seconds 332.41 # Real time elapsed on the host
|
||||
host_inst_rate 1664644 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1758990 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 879528148 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233480 # Number of bytes of host memory used
|
||||
host_seconds 342.45 # Real time elapsed on the host
|
||||
sim_insts 570051636 # Number of instructions simulated
|
||||
sim_ops 602359842 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 784748962 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9683278042 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2916519731 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.793670 # Nu
|
|||
sim_ticks 793670137000 # Number of ticks simulated
|
||||
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 904187 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 954854 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1262227313 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287296 # Number of bytes of host memory used
|
||||
host_seconds 628.79 # Real time elapsed on the host
|
||||
host_inst_rate 583678 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 616385 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 814802699 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241980 # Number of bytes of host memory used
|
||||
host_seconds 974.06 # Real time elapsed on the host
|
||||
sim_insts 568539335 # Number of instructions simulated
|
||||
sim_ops 600398272 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 201031 # To
|
|||
system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 2360195 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4941 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4941 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 2493 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 21835 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 21835 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 56045 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 56045 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1873216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 1873216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1873216 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 49213000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 240984000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 69093329 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 190459 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 190459 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 418626 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 247748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 247748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1286 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1293754 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1295040 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 41152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 54796160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 54837312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 54837312 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 847042500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 964500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 656346000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.744764 # Nu
|
|||
sim_ticks 744764112500 # Number of ticks simulated
|
||||
final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2243211 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2249879 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1124943447 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273192 # Number of bytes of host memory used
|
||||
host_seconds 662.05 # Real time elapsed on the host
|
||||
host_inst_rate 3917871 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3929519 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1964765726 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224984 # Number of bytes of host memory used
|
||||
host_seconds 379.06 # Real time elapsed on the host
|
||||
sim_insts 1485108088 # Number of instructions simulated
|
||||
sim_ops 1489523282 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory
|
||||
|
|
@ -35,6 +35,9 @@ system.physmem.bw_write::total 825324492 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10662372316 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 7940952255 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 1489528226 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.061066 # Nu
|
|||
sim_ticks 2061066313000 # Number of ticks simulated
|
||||
final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1083437 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1086658 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1503618533 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 281644 # Number of bytes of host memory used
|
||||
host_seconds 1370.74 # Real time elapsed on the host
|
||||
host_inst_rate 684045 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 686079 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 949333559 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233488 # Number of bytes of host memory used
|
||||
host_seconds 2171.07 # Real time elapsed on the host
|
||||
sim_insts 1485108088 # Number of instructions simulated
|
||||
sim_ops 1489523282 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 78189 # To
|
|||
system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 921310 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 5293 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5293 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 2518 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 21859 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 21859 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 56822 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 56822 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1898880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 1898880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1898880 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 49814000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 244368000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 4122132626 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -393,5 +409,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 27625902 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 194593 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 194593 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 435341 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 259735 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 259735 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2214 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1341783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1343997 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 70848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56867968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 56938816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 56938816 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 880175500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 679831500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 896740221 # Wr
|
|||
system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 12654699384 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 12199037473 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1927985345 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 89270 # To
|
|||
system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 1049487 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 5039 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5039 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 2511 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 21970 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 21970 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1889280 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 3600386796 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -370,5 +390,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu
|
|||
sim_ticks 54240661000 # Number of ticks simulated
|
||||
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1585065 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1596445 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 948925064 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411788 # Number of bytes of host memory used
|
||||
host_seconds 57.16 # Real time elapsed on the host
|
||||
host_inst_rate 2267620 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2283902 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1357548360 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 366572 # Number of bytes of host memory used
|
||||
host_seconds 39.95 # Real time elapsed on the host
|
||||
sim_insts 90602407 # Number of instructions simulated
|
||||
sim_ops 91252960 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 348597116 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9960199711 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 540247816 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
|
|||
sim_ticks 147135976000 # Number of ticks simulated
|
||||
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 836188 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 842183 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1358330065 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 420368 # Number of bytes of host memory used
|
||||
host_seconds 108.32 # Real time elapsed on the host
|
||||
host_inst_rate 662214 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 666963 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1075722156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 375060 # Number of bytes of host memory used
|
||||
host_seconds 136.78 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91226312 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 251414 # In
|
|||
system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 6672467 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 981760 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 821979690 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu
|
|||
sim_ticks 122215823500 # Number of ticks simulated
|
||||
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2097981 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2098068 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1051599524 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 405208 # Number of bytes of host memory used
|
||||
host_seconds 116.22 # Real time elapsed on the host
|
||||
host_inst_rate 2226348 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2226440 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1115942635 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 357000 # Number of bytes of host memory used
|
||||
host_seconds 109.52 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
|
||||
|
|
@ -35,6 +35,9 @@ system.physmem.bw_write::total 749543606 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11438757576 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 1397997177 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 244431648 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu
|
|||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1027753 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1027796 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1523718944 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 413792 # Number of bytes of host memory used
|
||||
host_seconds 237.24 # Real time elapsed on the host
|
||||
host_inst_rate 653861 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 653888 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 969395755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 365508 # Number of bytes of host memory used
|
||||
host_seconds 372.90 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 155623 # In
|
|||
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 2762444 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 998592 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 722977060 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -384,5 +399,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 1439319677 # Wr
|
|||
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 15992825110 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2701988442 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 337900081 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 17487 # To
|
|||
system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 5272114 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1025 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1025 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 100 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1929536 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 731978130 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -373,5 +393,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu
|
|||
sim_ticks 290498967000 # Number of ticks simulated
|
||||
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1613323 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1818377 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 925159382 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282068 # Number of bytes of host memory used
|
||||
host_seconds 314.00 # Real time elapsed on the host
|
||||
host_inst_rate 1591705 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1794011 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 912762441 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237748 # Number of bytes of host memory used
|
||||
host_seconds 318.26 # Real time elapsed on the host
|
||||
sim_insts 506581607 # Number of instructions simulated
|
||||
sim_ops 570968167 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 743781041 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9312824252 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2705365825 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu
|
|||
sim_ticks 717366012000 # Number of ticks simulated
|
||||
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 858996 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 967944 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1220258898 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290524 # Number of bytes of host memory used
|
||||
host_seconds 587.88 # Real time elapsed on the host
|
||||
host_inst_rate 611042 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 688541 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 868024183 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246240 # Number of bytes of host memory used
|
||||
host_seconds 826.44 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 8560472 # To
|
|||
system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 21286941 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 41855 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 41855 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 95953 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15270528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3342741 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3365783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 1120443517 # Wr
|
|||
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13357308966 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 11824281640 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1770458657 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 11351788 # To
|
|||
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 26154600 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 174452 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 174452 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 292286 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206691 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 43099456 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3295745698 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -373,5 +393,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.139855 # Number of seconds simulated
|
||||
sim_ticks 139855372500 # Number of ticks simulated
|
||||
final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.139913 # Number of seconds simulated
|
||||
sim_ticks 139912878500 # Number of ticks simulated
|
||||
final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 118034 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 118034 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41407532 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230404 # Number of bytes of host memory used
|
||||
host_seconds 3377.53 # Real time elapsed on the host
|
||||
host_inst_rate 81894 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 81894 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 28740964 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231128 # Number of bytes of host memory used
|
||||
host_seconds 4868.07 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7328 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 468992 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 139855320500 # Total gap between requests
|
||||
system.physmem.totGap 139912806500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -149,14 +149,84 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 47654000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests
|
||||
system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 37727500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 36640000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 113038750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6503.00 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15425.59 # Average bank access latency per request
|
||||
system.physmem.totBankLat 98463750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5148.40 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13436.65 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26928.60 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 23585.05 # Average memory access latency
|
||||
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -165,40 +235,55 @@ system.physmem.peakBW 12800.00 # Th
|
|||
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 6132 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6626 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 19085060.11 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 53489671 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted
|
||||
system.physmem.avgGap 19092904.82 # Average gap between requests
|
||||
system.membus.throughput 3352029 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 468992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 53489761 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 94754610 # DTB read hits
|
||||
system.cpu.dtb.read_hits 94754611 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94754631 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521101 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 94754632 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521122 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73521136 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275711 # DTB hits
|
||||
system.cpu.dtb.write_accesses 73521157 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275733 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168275767 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611339 # ITB hits
|
||||
system.cpu.dtb.data_accesses 168275789 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611325 # ITB hits
|
||||
system.cpu.itb.fetch_misses 44520 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 48655859 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 48655845 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -212,18 +297,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 279710746 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 279825758 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631956 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828437 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484572 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -234,12 +319,12 @@ system.cpu.execution_unit.executions 205475782 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.207865 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7883 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13519017 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306741 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.168773 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -251,124 +336,144 @@ system.cpu.committedInsts 398664595 # Nu
|
|||
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651735 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 180966170 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.302389 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90242832 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467914 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.737088 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.424689 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78078009 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747749 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.097633 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107174029 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.699727 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102610556 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215202 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.330554 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 181081179 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744579 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.287880 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90357849 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467909 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1831.214739 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 48606831 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1830.982662 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 48606794 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12453.710223 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12453.700743 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.894148 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.894148 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606831 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606831 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606831 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606831 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606831 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606831 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4508 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 205410000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 205410000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 205410000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 205410000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 205410000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 205410000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611339 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611339 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611339 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611339 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611339 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611339 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1830.982662 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.894035 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.894035 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606794 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606794 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606794 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606794 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606794 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606794 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4531 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 268165000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 268165000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 268165000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 268165000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 268165000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 268165000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611325 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611325 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611325 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611325 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611325 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611325 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 45565.661047 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59184.506731 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 59184.506731 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 59184.506731 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 326 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 68.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 108.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 605 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 605 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 605 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 605 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 605 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 605 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 628 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 628 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179905000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 179905000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179905000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 179905000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179905000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 179905000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234852500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 234852500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234852500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 234852500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234852500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 234852500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46094.030233 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46094.030233 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60172.303356 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60172.303356 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7806 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 16759 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 249792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 557056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2909.305713 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.697804 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119252 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.554458 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2908.829780 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.591520 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119231 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
|
||||
|
|
@ -393,17 +498,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 170516000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45771500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 216287500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 159323000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 159323000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 170516000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 205094500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 375610500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 170516000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 205094500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 375610500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 225463500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58932500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 284396000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 213301500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 213301500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 225463500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 272234000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 497697500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 225463500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 272234000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 497697500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -428,17 +533,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50763.917833 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55547.936893 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51706.311260 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50659.141494 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50659.141494 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51256.891376 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51256.891376 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67122.208991 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71520.024272 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67988.524982 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67822.416534 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67822.416534 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67917.235262 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67917.235262 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -458,17 +563,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128894552 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549355 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164443907 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120757665 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120757665 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128894552 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156307020 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 285201572 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128894552 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156307020 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 285201572 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183879500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 48740750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 232620250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174684500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174684500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183879500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 223425250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 407304750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183879500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 223425250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 407304750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -480,51 +585,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38372.894314 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43142.421117 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39312.432943 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38396.713831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38396.713831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54742.334028 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59151.395631 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55610.865408 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55543.561208 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55543.561208 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168254397 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3284.992544 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168254254 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40523.698699 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40523.664258 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3285.521075 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802129 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802129 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753186 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753186 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501211 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501211 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254397 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254397 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254397 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254397 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1303 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1303 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19518 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19518 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20821 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20821 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20821 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20821 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65740000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 65740000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 753340000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 753340000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 819080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 819080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 819080000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 819080000 # number of overall miss cycles
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3284.992544 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802000 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802000 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501073 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501073 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254254 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254254 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254254 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254254 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19656 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19656 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20964 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20964 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20964 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20964 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 84017000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 84017000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1065172500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1065172500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1149189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1149189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1149189500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1149189500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -535,38 +640,38 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218
|
|||
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50452.801228 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50452.801228 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38597.192335 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 38597.192335 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 39339.128764 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 18390 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64233.180428 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 64233.180428 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54190.705128 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54190.705128 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54817.282007 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28818 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 537 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 562 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.245810 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.277580 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 353 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 353 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16316 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16316 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16669 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16669 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16669 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16669 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16454 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16454 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16812 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16812 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16812 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 16812 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
||||
|
|
@ -575,14 +680,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48200500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163094000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 163094000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211294500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -591,14 +696,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu
|
|||
sim_ticks 199332411500 # Number of ticks simulated
|
||||
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2294613 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2294613 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1147307033 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269948 # Number of bytes of host memory used
|
||||
host_seconds 173.74 # Real time elapsed on the host
|
||||
host_inst_rate 1715563 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1715563 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 857781835 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222488 # Number of bytes of host memory used
|
||||
host_seconds 232.38 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 2470028804 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13793364824 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2749464673 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
|
|||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 853902 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 853902 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1215178011 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278532 # Number of bytes of host memory used
|
||||
host_seconds 466.87 # Real time elapsed on the host
|
||||
host_inst_rate 1715092 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1715091 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2440727076 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230984 # Number of bytes of host memory used
|
||||
host_seconds 232.45 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 361550 # In
|
|||
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 809285 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 459136 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -396,5 +411,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7346 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 16299 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu
|
|||
sim_ticks 212344043000 # Number of ticks simulated
|
||||
final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1130367 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1445119 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 879097302 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286212 # Number of bytes of host memory used
|
||||
host_seconds 241.55 # Real time elapsed on the host
|
||||
host_inst_rate 1381175 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1765765 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1074152891 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241892 # Number of bytes of host memory used
|
||||
host_seconds 197.69 # Real time elapsed on the host
|
||||
sim_insts 273037663 # Number of instructions simulated
|
||||
sim_ops 349065399 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 1883960470 # Wr
|
|||
system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10715621794 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2275398455 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu
|
|||
sim_ticks 525834342000 # Number of ticks simulated
|
||||
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 589682 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 753887 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1136891744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294668 # Number of bytes of host memory used
|
||||
host_seconds 462.52 # Real time elapsed on the host
|
||||
host_inst_rate 442791 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 566092 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 853689730 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250392 # Number of bytes of host memory used
|
||||
host_seconds 615.96 # Real time elapsed on the host
|
||||
sim_insts 272739283 # Number of instructions simulated
|
||||
sim_ops 348687122 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 317545 # In
|
|||
system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 831532 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 437248 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 41160 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 1.004711 # Nu
|
|||
sim_ticks 1004710587000 # Number of ticks simulated
|
||||
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2509174 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2509174 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1254857691 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273968 # Number of bytes of host memory used
|
||||
host_seconds 800.66 # Real time elapsed on the host
|
||||
host_inst_rate 3493388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3493388 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1747070946 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225488 # Number of bytes of host memory used
|
||||
host_seconds 575.08 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 1578689409 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13131370496 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 13193226959 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.769740 # Nu
|
|||
sim_ticks 2769739533000 # Number of ticks simulated
|
||||
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 964642 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 964642 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1329927483 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 281524 # Number of bytes of host memory used
|
||||
host_seconds 2082.62 # Real time elapsed on the host
|
||||
host_inst_rate 1559352 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1559352 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2149839105 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233980 # Number of bytes of host memory used
|
||||
host_seconds 1288.35 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 1546034 # To
|
|||
system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 12529860 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 408476 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 408476 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66908 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66873 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66873 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34704448 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 21192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3156417 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3177609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 678144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104081472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 104759616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu
|
|||
sim_ticks 945613126000 # Number of ticks simulated
|
||||
final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1270703 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1730522 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 867964073 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286692 # Number of bytes of host memory used
|
||||
host_seconds 1089.46 # Real time elapsed on the host
|
||||
host_inst_rate 1181509 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1609052 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 807039161 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242488 # Number of bytes of host memory used
|
||||
host_seconds 1171.71 # Real time elapsed on the host
|
||||
sim_insts 1384381606 # Number of instructions simulated
|
||||
sim_ops 1885336358 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 1188602786 # Wr
|
|||
system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9675679644 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 9149449674 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu
|
|||
sim_ticks 2326118592000 # Number of ticks simulated
|
||||
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 664911 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 901999 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1119467924 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296296 # Number of bytes of host memory used
|
||||
host_seconds 2077.88 # Real time elapsed on the host
|
||||
host_inst_rate 575384 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 780549 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 968736790 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250996 # Number of bytes of host memory used
|
||||
host_seconds 2401.19 # Real time elapsed on the host
|
||||
sim_insts 1381604339 # Number of instructions simulated
|
||||
sim_ops 1874244941 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 1818624 # To
|
|||
system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 14864384 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 408063 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 408063 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66099 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34576320 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 39606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3163563 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3203169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1267392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104314240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 105581632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu
|
|||
sim_ticks 44221003000 # Number of ticks simulated
|
||||
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2426632 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2426631 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1214706702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272072 # Number of bytes of host memory used
|
||||
host_seconds 36.40 # Real time elapsed on the host
|
||||
host_inst_rate 2564036 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2564035 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1283487470 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224620 # Number of bytes of host memory used
|
||||
host_seconds 34.45 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 2072610067 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 12937468537 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 572107835 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu
|
|||
sim_ticks 133634727000 # Number of ticks simulated
|
||||
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 996502 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 996501 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1507427540 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280652 # Number of bytes of host memory used
|
||||
host_seconds 88.65 # Real time elapsed on the host
|
||||
host_inst_rate 671194 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 671194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1015328507 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233108 # Number of bytes of host memory used
|
||||
host_seconds 131.62 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 54587966 # To
|
|||
system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 133682617 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 34272 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 34272 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 113982 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17864640 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 152872 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 729935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23854016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28745920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu
|
|||
sim_ticks 53932157000 # Number of ticks simulated
|
||||
final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1242714 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1763527 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 945130731 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286616 # Number of bytes of host memory used
|
||||
host_seconds 57.06 # Real time elapsed on the host
|
||||
host_inst_rate 2080365 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2952231 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1582195312 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241268 # Number of bytes of host memory used
|
||||
host_seconds 34.09 # Real time elapsed on the host
|
||||
sim_insts 70913181 # Number of instructions simulated
|
||||
sim_ops 100632428 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 1458502967 # Wr
|
|||
system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9230371187 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 497813828 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu
|
|||
sim_ticks 132689045000 # Number of ticks simulated
|
||||
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 652363 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 925068 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1230026759 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295072 # Number of bytes of host memory used
|
||||
host_seconds 107.88 # Real time elapsed on the host
|
||||
host_inst_rate 438025 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 621131 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 825892843 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249772 # Number of bytes of host memory used
|
||||
host_seconds 160.66 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 99791654 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 40471887 # To
|
|||
system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 102119538 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 25532 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 25532 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 83909 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13550144 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 37816 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 448235 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 486051 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18447168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu
|
|||
sim_ticks 68148672000 # Number of ticks simulated
|
||||
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2091817 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2118902 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1060681468 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 281256 # Number of bytes of host memory used
|
||||
host_seconds 64.25 # Real time elapsed on the host
|
||||
host_inst_rate 2813738 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2850169 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1426739476 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233072 # Number of bytes of host memory used
|
||||
host_seconds 47.77 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
|
||||
|
|
@ -35,6 +35,9 @@ system.physmem.bw_write::total 1318924454 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11383698247 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 775783918 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 136297345 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu
|
|||
sim_ticks 202242260000 # Number of ticks simulated
|
||||
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1033030 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1046406 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1554493166 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289840 # Number of bytes of host memory used
|
||||
host_seconds 130.10 # Real time elapsed on the host
|
||||
host_inst_rate 840510 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 851393 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1264790801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241580 # Number of bytes of host memory used
|
||||
host_seconds 159.90 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 26223758 # To
|
|||
system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 67847660 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 30277 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 30277 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 82868 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13721664 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 404484520 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -393,5 +409,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374048 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 425326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 799374 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 17577472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
|
|||
sim_ticks 913189263000 # Number of ticks simulated
|
||||
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2288605 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2288605 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1148451794 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263992 # Number of bytes of host memory used
|
||||
host_seconds 795.15 # Real time elapsed on the host
|
||||
host_inst_rate 4050769 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4050768 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2032728095 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217548 # Number of bytes of host memory used
|
||||
host_seconds 449.24 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 906468506 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11068994882 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 10108087278 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
|
|||
sim_ticks 2623386226000 # Number of ticks simulated
|
||||
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1056521 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1056521 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1523075909 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272444 # Number of bytes of host memory used
|
||||
host_seconds 1722.43 # Real time elapsed on the host
|
||||
host_inst_rate 781919 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 781919 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1127211275 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225028 # Number of bytes of host memory used
|
||||
host_seconds 2327.32 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 24836956 # To
|
|||
system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 72644797 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190575360 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -402,5 +418,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu
|
|||
sim_ticks 861538200000 # Number of ticks simulated
|
||||
final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1602478 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1787682 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 893842215 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278712 # Number of bytes of host memory used
|
||||
host_seconds 963.86 # Real time elapsed on the host
|
||||
host_inst_rate 2812355 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3137389 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1568696760 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234512 # Number of bytes of host memory used
|
||||
host_seconds 549.21 # Real time elapsed on the host
|
||||
sim_insts 1544563041 # Number of instructions simulated
|
||||
sim_ops 1723073853 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 724469782 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9731209155 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 8383808419 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu
|
|||
sim_ticks 2391205115000 # Number of ticks simulated
|
||||
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 809589 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 903509 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1258086461 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287292 # Number of bytes of host memory used
|
||||
host_seconds 1900.67 # Real time elapsed on the host
|
||||
host_inst_rate 1401168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2177389973 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243008 # Number of bytes of host memory used
|
||||
host_seconds 1098.20 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1717270334 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
|
|
@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 27225047 # To
|
|||
system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 79651138 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190462208 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 542745211 # Wr
|
|||
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13588998587 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 38674388193 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 5692014456 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 11079992 # To
|
|||
system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 32392097 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018421 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190549120 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 11765161052 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -370,5 +390,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.041622 # Number of seconds simulated
|
||||
sim_ticks 41622221000 # Number of ticks simulated
|
||||
final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.041671 # Number of seconds simulated
|
||||
sim_ticks 41671058000 # Number of ticks simulated
|
||||
final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 47594 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 47594 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21554846 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275256 # Number of bytes of host memory used
|
||||
host_seconds 1930.99 # Real time elapsed on the host
|
||||
host_inst_rate 79080 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79080 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35856814 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228800 # Number of bytes of host memory used
|
||||
host_seconds 1162.15 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 316032 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 41622168000 # Total gap between requests
|
||||
system.physmem.totGap 41670985500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1195 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 440 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -149,56 +149,135 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 23362750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 122110250 # Sum of mem lat for all requests
|
||||
system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 21938250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 74057500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4731.22 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14997.47 # Average bank access latency per request
|
||||
system.physmem.totBankLat 64198750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4442.74 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13000.96 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24728.69 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 22443.70 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 0.06 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 4243 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4578 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 8428952.61 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 13412628 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
|
||||
system.physmem.avgGap 8438838.70 # Average gap between requests
|
||||
system.membus.throughput 7583969 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 316032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 13412467 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 19996247 # DTB read hits
|
||||
system.cpu.dtb.read_hits 19996249 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 19996257 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501860 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 19996259 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501862 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6501883 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498107 # DTB hits
|
||||
system.cpu.dtb.write_accesses 6501885 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498111 # DTB hits
|
||||
system.cpu.dtb.data_misses 33 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 26498140 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956943 # ITB hits
|
||||
system.cpu.dtb.data_accesses 26498144 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9957259 # ITB hits
|
||||
system.cpu.itb.fetch_misses 49 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 9956992 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 9957308 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -212,34 +291,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 83244443 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 83342117 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570548 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146020 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521871 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058018 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521724 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722400 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469281 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799226 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 82970150 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 82971475 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10684 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7636716 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607727 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.826155 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 10802 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7733735 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75608382 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.720496 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -251,72 +330,72 @@ system.cpu.committedInsts 91903056 # Nu
|
|||
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.906848 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.906848 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102720 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29384710 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859733 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.700695 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.649281 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.102720 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27661043 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55681074 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.810247 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34090230 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251887 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.096035 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33490685 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851432 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.815414 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65315589 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026528 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.629554 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29482268 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859849 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.625007 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 7633 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.272065 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945862 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 9518 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.952931 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.649281 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945578 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945578 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11365 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259163500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 259163500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 259163500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 259163500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 259163500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 259163500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9956943 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22803.651562 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22803.651562 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.272065 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728648 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728648 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945862 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945862 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945862 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945862 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945862 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945862 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11397 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11397 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11397 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11397 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11397 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11397 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 317452000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 317452000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 317452000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 317452000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 317452000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 317452000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9957259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9957259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9957259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9957259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9957259 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9957259 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27853.996666 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27853.996666 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27853.996666 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -325,63 +404,83 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209587500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 209587500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209587500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 209587500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209587500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 209587500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9518 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 9518 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 9518 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 9518 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9518 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9518 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260091000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 260091000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260091000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 260091000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260091000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 260091000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22015.493697 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22015.493697 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27326.223997 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27326.223997 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 18196610 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 9993 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 9993 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19036 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 23589 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 758272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 758272 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6031000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 14277000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2190.263303 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 2189.717368 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6791 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.069165 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.839003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.325102 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.099198 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.843612 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1820.867359 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.006398 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6724 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6777 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 6724 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 6803 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 6724 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 6805 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 6803 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
|
||||
|
|
@ -393,52 +492,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132531500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24055000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 156586500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84148000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 84148000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 132531500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 108203000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 240734500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 132531500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 108203000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 240734500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183057000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30189500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 213246500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114689000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 114689000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 183057000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 144878500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 327935500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 183057000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 144878500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 327935500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9518 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9993 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 9518 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 11741 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 9518 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 11741 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293549 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.321825 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293549 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.420577 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293549 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47434.323550 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57002.369668 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48689.832090 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48866.434379 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48866.434379 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48751.417578 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48751.417578 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420577 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65517.895490 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71539.099526 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66307.991294 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66602.206736 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66602.206736 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66410.591333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66410.591333 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -458,73 +557,73 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97814921 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18797852 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116612773 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63183937 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63183937 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97814921 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81981789 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 179796710 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97814921 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81981789 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 179796710 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 148372000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24939500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 173311500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93717750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93717750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 148372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118657250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 267029250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 148372000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118657250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 267029250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321825 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.420577 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35008.919470 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44544.672986 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36260.190609 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36692.181765 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36692.181765 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420577 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53103.793844 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59098.341232 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53890.391791 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54423.780488 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54423.780488 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.801421 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1441.455577 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488507 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.657670 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.801421 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6493002 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6493002 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488625 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488625 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488625 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488625 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8101 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8101 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8676 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8676 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31369500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31369500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 377418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 377418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 377418000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 377418000 # number of overall miss cycles
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.455577 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.351918 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492885 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492885 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488507 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488507 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488507 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488507 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8218 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8218 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8794 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8794 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8794 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8794 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38984000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 38984000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 463524000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 463524000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 502508000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 502508000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 502508000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 502508000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -535,38 +634,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301
|
|||
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54555.652174 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54555.652174 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001264 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.001264 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67680.555556 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67680.555556 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56403.504502 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
|
|
@ -575,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25078500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 25078500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111244000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 111244000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111244000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 111244000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -591,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52796.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52796.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu
|
|||
sim_ticks 45951567500 # Number of ticks simulated
|
||||
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1141309 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1141309 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 570654979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267644 # Number of bytes of host memory used
|
||||
host_seconds 80.52 # Real time elapsed on the host
|
||||
host_inst_rate 3944537 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3944535 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1972268010 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220188 # Number of bytes of host memory used
|
||||
host_seconds 23.30 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 672903574 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11030545389 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 506870851 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu
|
|||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1044383 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1044383 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1349235521 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276220 # Number of bytes of host memory used
|
||||
host_seconds 88.00 # Real time elapsed on the host
|
||||
host_inst_rate 852211 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 852211 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1100968725 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228676 # Number of bytes of host memory used
|
||||
host_seconds 107.84 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 1412827 # In
|
|||
system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 2568532 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 304960 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -396,5 +411,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu
|
|||
sim_ticks 103106766000 # Number of ticks simulated
|
||||
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1465257 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1604314 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 876741604 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282008 # Number of bytes of host memory used
|
||||
host_seconds 117.60 # Real time elapsed on the host
|
||||
host_inst_rate 2813934 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3080985 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1683727447 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236772 # Number of bytes of host memory used
|
||||
host_seconds 61.24 # Real time elapsed on the host
|
||||
sim_insts 172317409 # Number of instructions simulated
|
||||
sim_ops 188670891 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 438893991 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 8876496088 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 915226805 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu
|
|||
sim_ticks 232072304000 # Number of ticks simulated
|
||||
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 817822 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 895603 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1104464333 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290584 # Number of bytes of host memory used
|
||||
host_seconds 210.12 # Real time elapsed on the host
|
||||
host_inst_rate 1198657 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1618778979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245268 # Number of bytes of host memory used
|
||||
host_seconds 143.36 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 188185920 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 476817 # In
|
|||
system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 952255 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 220992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu
|
|||
sim_ticks 96722945000 # Number of ticks simulated
|
||||
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1868868 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1868870 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 934440193 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277724 # Number of bytes of host memory used
|
||||
host_seconds 103.51 # Real time elapsed on the host
|
||||
host_inst_rate 3763101 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3763105 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1881563141 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229516 # Number of bytes of host memory used
|
||||
host_seconds 51.41 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
|
||||
|
|
@ -35,6 +35,9 @@ system.physmem.bw_write::total 745070490 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11057254439 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 1069490213 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 401 # Number of system calls
|
||||
system.cpu.numCycles 193445891 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu
|
|||
sim_ticks 270563082000 # Number of ticks simulated
|
||||
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1012263 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1012264 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1415810765 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286308 # Number of bytes of host memory used
|
||||
host_seconds 191.10 # Real time elapsed on the host
|
||||
host_inst_rate 942019 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 942020 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1317563963 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238020 # Number of bytes of host memory used
|
||||
host_seconds 205.35 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 850848 # In
|
|||
system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 1223641 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 331072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 401 # Number of system calls
|
||||
system.cpu.numCycles 541126164 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -379,5 +394,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 24576 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3154 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 27730 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 759721898 # Wr
|
|||
system.physmem.bw_total::cpu.inst 10563380223 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3122279959 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13685660183 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13685660183 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 1798200879 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 262786137 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -27,6 +27,25 @@ system.physmem.bw_inst_read::total 724276 # In
|
|||
system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 1207552 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 303040 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 501907914 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -364,5 +383,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu
|
|||
sim_ticks 1870325497500 # Number of ticks simulated
|
||||
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3609656 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 106905838632 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305660 # Number of bytes of host memory used
|
||||
host_seconds 17.50 # Real time elapsed on the host
|
||||
host_inst_rate 3096593 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3096591 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 91710635166 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308248 # Number of bytes of host memory used
|
||||
host_seconds 20.39 # Real time elapsed on the host
|
||||
sim_insts 63151114 # Number of instructions simulated
|
||||
sim_ops 63151114 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
|
||||
|
|
@ -170,6 +170,9 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -191,6 +194,9 @@ system.physmem.writeRowHits 0 # Nu
|
|||
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap nan # Average gap between requests
|
||||
system.membus.throughput 42148404 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 78831234 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.l2c.replacements 1000406 # number of replacements
|
||||
system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2465980 # Total number of references to valid blocks.
|
||||
|
|
@ -550,6 +556,11 @@ system.tsunami.ethernet.totalRxOrn 0 # to
|
|||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.toL2Bus.throughput 131960056 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 246797826 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 10432 # Total snoop data (bytes)
|
||||
system.iobus.throughput 1460513 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 2731634 # Total data (bytes)
|
||||
system.cpu0.icache.replacements 883989 # number of replacements
|
||||
system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu
|
|||
sim_ticks 1829330593000 # Number of ticks simulated
|
||||
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3233953 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3233951 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98537371937 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303612 # Number of bytes of host memory used
|
||||
host_seconds 18.56 # Real time elapsed on the host
|
||||
host_inst_rate 1529223 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1529222 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46594888750 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306208 # Number of bytes of host memory used
|
||||
host_seconds 39.26 # Real time elapsed on the host
|
||||
sim_insts 60037737 # Number of instructions simulated
|
||||
sim_ops 60037737 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
|
||||
|
|
@ -160,6 +160,9 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -181,6 +184,9 @@ system.physmem.writeRowHits 0 # Nu
|
|||
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap nan # Average gap between requests
|
||||
system.membus.throughput 42552299 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 77842222 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.replacements 41686 # number of replacements
|
||||
system.iocache.tagsinuse 1.225558 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
@ -407,6 +413,8 @@ system.tsunami.ethernet.totalRxOrn 0 # to
|
|||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.iobus.throughput 1480182 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 2707742 # Total data (bytes)
|
||||
system.cpu.icache.replacements 919577 # number of replacements
|
||||
system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks.
|
||||
|
|
@ -593,5 +601,8 @@ system.cpu.dcache.cache_copies 0 # nu
|
|||
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833491 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 132867618 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 243048686 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu
|
|||
sim_ticks 912096763500 # Number of ticks simulated
|
||||
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1025890 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15183699019 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 392232 # Number of bytes of host memory used
|
||||
host_seconds 60.07 # Real time elapsed on the host
|
||||
host_inst_rate 749434 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 964895 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11092016800 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 399496 # Number of bytes of host memory used
|
||||
host_seconds 82.23 # Real time elapsed on the host
|
||||
sim_insts 61625970 # Number of instructions simulated
|
||||
sim_ops 79343340 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
|
||||
|
|
@ -188,6 +188,9 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -227,6 +230,9 @@ system.realview.nvmem.bw_inst_read::total 75 # I
|
|||
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 64986577 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 59274047 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.l2c.replacements 70658 # number of replacements
|
||||
system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1623339 # Total number of references to valid blocks.
|
||||
|
|
@ -409,6 +415,11 @@ system.cf0.dma_read_txs 0 # Nu
|
|||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.toL2Bus.throughput 154009014 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 140471123 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iobus.throughput 45730949 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 41711051 # Total data (bytes)
|
||||
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu0.dtb.read_hits 7975768 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810264000 # Number of ticks simulated
|
||||
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1712706 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66139785958 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 391204 # Number of bytes of host memory used
|
||||
host_seconds 35.27 # Real time elapsed on the host
|
||||
host_inst_rate 692273 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 890221 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26733610702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 396420 # Number of bytes of host memory used
|
||||
host_seconds 87.26 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
|
|
@ -171,6 +171,9 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -204,12 +207,17 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9
|
|||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55969585 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566422 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.iobus.throughput 48895252 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 114063346 # Total data (bytes)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 14971214 # DTB read hits
|
||||
|
|
@ -490,6 +498,9 @@ system.cpu.dcache.cache_copies 0 # nu
|
|||
system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 592643 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,25 +4,13 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810264000 # Number of ticks simulated
|
||||
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1307768 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1681709 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50502250863 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 395644 # Number of bytes of host memory used
|
||||
host_seconds 46.19 # Real time elapsed on the host
|
||||
host_inst_rate 662335 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 851722 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25577480180 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 396424 # Number of bytes of host memory used
|
||||
host_seconds 91.21 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
|
||||
|
|
@ -196,6 +184,9 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -217,6 +208,21 @@ system.physmem.writeRowHits 0 # Nu
|
|||
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap nan # Average gap between requests
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55969561 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566366 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.l2c.replacements 62242 # number of replacements
|
||||
system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1678485 # Total number of references to valid blocks.
|
||||
|
|
@ -379,6 +385,11 @@ system.cf0.dma_read_txs 0 # Nu
|
|||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.toL2Bus.throughput 59119250 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 137913994 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iobus.throughput 48895252 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 114063346 # Total data (bytes)
|
||||
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu0.dtb.read_hits 7929205 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112100 # Nu
|
|||
sim_ticks 5112099860500 # Number of ticks simulated
|
||||
final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1019592 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2087576 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26073588986 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 631672 # Number of bytes of host memory used
|
||||
host_seconds 196.06 # Real time elapsed on the host
|
||||
host_inst_rate 794426 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1626557 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 20315509625 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 586244 # Number of bytes of host memory used
|
||||
host_seconds 251.64 # Real time elapsed on the host
|
||||
sim_insts 199905607 # Number of instructions simulated
|
||||
sim_ops 409299132 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory
|
||||
|
|
@ -168,6 +168,9 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -189,6 +192,9 @@ system.physmem.writeRowHits 0 # Nu
|
|||
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap nan # Average gap between requests
|
||||
system.membus.throughput 9632717 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 49243411 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.replacements 47568 # number of replacements
|
||||
system.iocache.tagsinuse 0.042441 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
@ -245,6 +251,8 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
|
|||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iobus.throughput 2555194 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 13062406 # Total data (bytes)
|
||||
system.cpu.numCycles 10224199744 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
|
@ -455,6 +463,9 @@ system.cpu.dcache.cache_copies 0 # nu
|
|||
system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535700 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 54622198 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 279208723 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 25408 # Total snoop data (bytes)
|
||||
system.cpu.l2cache.replacements 105930 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64819.953901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3456506 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 19476000 # Number of ticks simulated
|
||||
final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000025 # Number of seconds simulated
|
||||
sim_ticks 24560000 # Number of ticks simulated
|
||||
final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1322 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1322 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4028719 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223696 # Number of bytes of host memory used
|
||||
host_seconds 4.83 # Real time elapsed on the host
|
||||
host_inst_rate 1785 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1785 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6860090 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225432 # Number of bytes of host memory used
|
||||
host_seconds 3.58 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu
|
|||
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29952 # by
|
|||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 19461500 # Total gap between requests
|
||||
system.physmem.totGap 24545500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -149,27 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2627750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests
|
||||
system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1607750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2345000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8401250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5602.88 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17913.11 # Average bank access latency per request
|
||||
system.physmem.totBankLat 7576250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3428.04 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16154.05 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 28515.99 # Average memory access latency
|
||||
system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 24582.09 # Average memory access latency
|
||||
system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 12.01 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.69 # Average read queue length over time
|
||||
system.physmem.busUtil 9.53 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.47 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 377 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 402 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 41495.74 # Average gap between requests
|
||||
system.physmem.avgGap 52335.82 # Average gap between requests
|
||||
system.membus.throughput 1219543974 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 29952 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.8 # Layer utilization (%)
|
||||
system.cpu.branchPred.lookups 1632 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
|
||||
|
|
@ -183,18 +218,18 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1183 # DTB read hits
|
||||
system.cpu.dtb.read_hits 1184 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1190 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 866 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 1191 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 893 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 869 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2049 # DTB hits
|
||||
system.cpu.dtb.write_accesses 896 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2077 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2059 # DTB accesses
|
||||
system.cpu.dtb.data_accesses 2087 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 915 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -212,18 +247,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 38953 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 49121 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 5174 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 9741 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 2976 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 2152 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -234,12 +269,12 @@ system.cpu.execution_unit.executions 4448 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7375 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 18.933073 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7376 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 15.015981 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 1183 # Number of Load instructions committed
|
||||
system.cpu.comStores 865 # Number of Store instructions committed
|
||||
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
||||
|
|
@ -251,36 +286,36 @@ system.cpu.committedInsts 6390 # Nu
|
|||
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
|
||||
|
|
@ -293,12 +328,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n
|
|||
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 355 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
|
||||
|
|
@ -311,17 +346,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978
|
|||
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -337,36 +372,55 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302
|
|||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52524.834437 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52524.834437 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67756.622517 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67756.622517 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1222149837 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 451500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 197.103662 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 140.828803 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.274859 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -384,17 +438,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15544000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5344500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 20888500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8903000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24447000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15544000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8903000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24447000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20144000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6932500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27076500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4877500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4877500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20144000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11810000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31954000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20144000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11810000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31954000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -417,17 +471,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51641.196013 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56257.894737 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52748.737374 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48746.575342 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48746.575342 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52125.799574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52125.799574 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66923.588040 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72973.684211 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68375 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66815.068493 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66815.068493 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68132.196162 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68132.196162 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -447,17 +501,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16417750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5764000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22181750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16417750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9750750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26168500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16417750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9750750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26168500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -469,27 +523,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54544.019934 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60673.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56014.520202 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 102.747723 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 104.433203 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025496 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025496 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 102.747723 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.025085 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.025085 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
|
||||
|
|
@ -506,14 +560,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n
|
|||
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 447 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5722500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15380500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 15380500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21103000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21103000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7336500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7336500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21108000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21108000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28444500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28444500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28444500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28444500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -530,19 +584,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58994.845361 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58994.845361 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43944.285714 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 43944.285714 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47210.290828 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75634.020619 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75634.020619 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60308.571429 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60308.571429 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63634.228188 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -562,14 +616,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3636000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3636000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9082000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9082000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9082000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9082000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7034000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7034000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4955000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4955000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11989000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11989000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11989000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11989000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -578,14 +632,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 3208000 # Number of ticks simulated
|
||||
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 84722 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84702 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42507676 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261184 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 2502 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2502 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1255935 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215792 # Number of bytes of host memory used
|
||||
host_seconds 2.55 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
|
||||
|
|
@ -33,6 +33,9 @@ system.physmem.bw_write::total 2087281796 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 12806733167 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 41084 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu
|
|||
sim_ticks 32544000 # Number of ticks simulated
|
||||
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 97330 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 97300 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 495402774 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269640 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 19861 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 101141711 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224276 # Number of bytes of host memory used
|
||||
host_seconds 0.32 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
|
||||
|
|
@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 546705998 # In
|
|||
system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 877089479 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -383,5 +398,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Reference in a new issue