gem5/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
Andreas Hansson 74553c7d3f stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00

105 lines
11 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 0.103107 # Number of seconds simulated
sim_ticks 103106766000 # Number of ticks simulated
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2813934 # Simulator instruction rate (inst/s)
host_op_rate 3080985 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1683727447 # Simulator tick rate (ticks/s)
host_mem_usage 236772 # Number of bytes of host memory used
host_seconds 61.24 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated
sim_ops 188670891 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory
system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29622453 # Number of read requests responded to by this memory
system.physmem.num_reads::total 219482504 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7365570985 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1072031112 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8437602097 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7365570985 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7365570985 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 438893991 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 438893991 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 8876496088 # Throughput (bytes/s)
system.membus.data_through_bus 915226805 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 206213533 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317409 # Number of instructions committed
system.cpu.committedOps 188670891 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3545028 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106218 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read
system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_mem_refs 42494119 # number of memory refs
system.cpu.num_load_insts 29849484 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 206213533 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------