74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
423 lines
48 KiB
Text
423 lines
48 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.361489 # Number of seconds simulated
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sim_ticks 361488530000 # Number of ticks simulated
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final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 653861 # Simulator instruction rate (inst/s)
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host_op_rate 653888 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 969395755 # Simulator tick rate (ticks/s)
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host_mem_usage 365508 # Number of bytes of host memory used
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host_seconds 372.90 # Real time elapsed on the host
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sim_insts 243825150 # Number of instructions simulated
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sim_ops 243835265 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
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system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 2762444 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 1036 # Transaction distribution
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system.membus.trans_dist::ReadResp 1036 # Transaction distribution
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system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
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system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 998592 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.workload.num_syscalls 443 # Number of system calls
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system.cpu.numCycles 722977060 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 243825150 # Number of instructions committed
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system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
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system.cpu.num_func_calls 4252956 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
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system.cpu.num_int_insts 194726494 # number of integer instructions
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system.cpu.num_fp_insts 11630 # number of float instructions
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system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
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system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
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system.cpu.num_mem_refs 105711441 # number of memory refs
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system.cpu.num_load_insts 82803521 # Number of load instructions
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system.cpu.num_store_insts 22907920 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 722977060 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 25 # number of replacements
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system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use
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system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
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system.cpu.icache.overall_hits::total 244420617 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
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system.cpu.icache.overall_misses::total 882 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
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system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
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system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
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|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 935475 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
|
|
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
|
|
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
|
|
system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
|
|
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 935266 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
|
|
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|