74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
433 lines
49 KiB
Text
433 lines
49 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.061066 # Number of seconds simulated
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sim_ticks 2061066313000 # Number of ticks simulated
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final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 684045 # Simulator instruction rate (inst/s)
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host_op_rate 686079 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 949333559 # Simulator tick rate (ticks/s)
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host_mem_usage 233488 # Number of bytes of host memory used
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host_seconds 2171.07 # Real time elapsed on the host
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sim_insts 1485108088 # Number of instructions simulated
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sim_ops 1489523282 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1672512 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1737728 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 161152 # Number of bytes written to this memory
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system.physmem.bytes_written::total 161152 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 26133 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 27152 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 2518 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 2518 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 31642 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 811479 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 843121 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 31642 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 31642 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 78189 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 78189 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 78189 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 921310 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 5293 # Transaction distribution
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system.membus.trans_dist::ReadResp 5293 # Transaction distribution
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system.membus.trans_dist::Writeback 2518 # Transaction distribution
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system.membus.trans_dist::ReadExReq 21859 # Transaction distribution
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system.membus.trans_dist::ReadExResp 21859 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 56822 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 56822 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1898880 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 1898880 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 1898880 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 49814000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 244368000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.workload.num_syscalls 49 # Number of system calls
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system.cpu.numCycles 4122132626 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 1485108088 # Number of instructions committed
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system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
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system.cpu.num_func_calls 1207835 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1319481286 # number of integer instructions
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system.cpu.num_fp_insts 8454127 # number of float instructions
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system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1234343144 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
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system.cpu.num_mem_refs 569365766 # number of memory refs
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system.cpu.num_load_insts 402515345 # Number of load instructions
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system.cpu.num_store_insts 166850421 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 4122132626 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 118 # number of replacements
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system.cpu.icache.tagsinuse 906.468716 # Cycle average of tags in use
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system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 906.468716 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 1485111892 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 1485111892 # number of overall hits
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system.cpu.icache.overall_hits::total 1485111892 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
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system.cpu.icache.overall_misses::total 1107 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 57199000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 57199000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 57199000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 57199000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 57199000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 57199000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 1485112999 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 1485112999 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 1485112999 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51670.280036 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 51670.280036 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 51670.280036 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 51670.280036 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54985000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 54985000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54985000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 54985000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54985000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 54985000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49670.280036 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49670.280036 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 2539 # number of replacements
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system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 23989 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 22.292926 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 20839.325928 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 913.017348 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 501.206640 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.635966 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.027863 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.015296 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.679124 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 88 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 189300 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 435341 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 237876 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 237876 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 88 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 427088 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 427176 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 88 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 427088 # number of overall hits
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system.cpu.l2cache.overall_hits::total 427176 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 4274 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 5293 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 21859 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 21859 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 26133 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 27152 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 26133 # number of overall misses
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system.cpu.l2cache.overall_misses::total 27152 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52998000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 275246000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136668000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 1136668000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 52998000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 1358916000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 1411914000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 52998000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 1358916000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 1411914000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::writebacks 435341 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 435341 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 453221 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 454328 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.920506 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084159 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.084159 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920506 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.057661 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.059763 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920506 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.057661 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.059763 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.813543 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.889288 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 52000.368297 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 52000.368297 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 2518 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 2518 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5293 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21859 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21859 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 26133 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 27152 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 26133 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 27152 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40770000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 211730000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874360000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874360000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40770000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045320000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1086090000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40770000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045320000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1086090000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084159 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084159 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059763 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059763 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.813543 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.889288 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 449125 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 568906445 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
|
|
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
|
|
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles
|
|
system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
|
|
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 435341 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
|
|
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 27625902 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 194593 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 194593 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 435341 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 259735 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 259735 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2214 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1341783 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 1343997 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 70848 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56867968 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 56938816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 56938816 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 880175500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 679831500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|