74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
936 lines
106 KiB
Plaintext
936 lines
106 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.026877 # Number of seconds simulated
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sim_ticks 26876770500 # Number of ticks simulated
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final_tick 26876770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 124105 # Simulator instruction rate (inst/s)
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host_op_rate 124996 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 36820237 # Simulator tick rate (ticks/s)
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host_mem_usage 379416 # Number of bytes of host memory used
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host_seconds 729.95 # Real time elapsed on the host
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sim_insts 90589798 # Number of instructions simulated
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sim_ops 91240351 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
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system.physmem.bytes_read::total 992448 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1666867 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 35258998 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 36925865 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1666867 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1666867 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1666867 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 35258998 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 36925865 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15507 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 15509 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 992448 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 992448 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 885 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 1078 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 957 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 935 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 26876578500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 15507 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 11266 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 4119 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 3465.175627 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 823.608896 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 3831.300006 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 21 7.53% 31.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 17 6.09% 37.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 11 3.94% 41.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 11 3.94% 45.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 5 1.79% 47.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 1 0.36% 48.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 3 1.08% 49.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3201 1 0.36% 59.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation
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system.physmem.totQLat 33774250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 291406750 # Sum of mem lat for all requests
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system.physmem.totBusLat 77535000 # Total cycles spent in databus access
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system.physmem.totBankLat 180097500 # Total cycles spent in bank access
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system.physmem.avgQLat 2178.00 # Average queueing delay per request
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system.physmem.avgBankLat 11613.95 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 18791.95 # Average memory access latency
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system.physmem.avgRdBW 36.93 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 36.93 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.29 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 15228 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 1733190.08 # Average gap between requests
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system.membus.throughput 36925865 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 969 # Transaction distribution
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system.membus.trans_dist::ReadResp 969 # Transaction distribution
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system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
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system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
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system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
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system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 31018 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 31018 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992448 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 992448 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 992448 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 19245500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.membus.respLayer1.occupancy 145771998 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
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system.cpu.branchPred.lookups 26679971 # Number of BP lookups
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system.cpu.branchPred.condPredicted 21999923 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 841486 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 11361779 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 11280277 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 99.282665 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 69760 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 186 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
|
system.cpu.numCycles 53753542 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 14168054 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 127857393 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 26679971 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 11350037 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 24029267 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 4759146 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 11320906 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 13839868 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 53419540 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.409911 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.214764 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 29428601 55.09% 55.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 3388763 6.34% 61.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 2027589 3.80% 65.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 1554197 2.91% 68.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 1665441 3.12% 71.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 2919869 5.47% 76.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 1510771 2.83% 79.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1090381 2.04% 81.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 9833928 18.41% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 53419540 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.496339 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.378585 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 16932063 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 9167037 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 22428085 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 999775 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 3892580 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 4442872 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 8651 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 126035469 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 42652 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 3892580 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 18713289 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 3601391 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 176810 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 21544043 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 5491427 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 123129214 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 413620 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4613636 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 1365 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 143579054 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 536328979 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 536324233 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 4746 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 36164868 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4608 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 4606 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12537284 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 29472276 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 5518407 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2148723 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1268677 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 118148285 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 105144607 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 78560 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 26719178 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 65548353 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 53419540 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.968280 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.909780 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 15372134 28.78% 28.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 11649287 21.81% 50.58% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 8266991 15.48% 66.06% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 6802353 12.73% 78.79% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 4948394 9.26% 88.06% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2939644 5.50% 93.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 2464571 4.61% 98.17% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 534271 1.00% 99.17% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 441895 0.83% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 53419540 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 45832 6.94% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 27 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 339714 51.41% 58.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 275235 41.65% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 74415665 70.77% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 126 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 171 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 25604813 24.35% 95.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 5112854 4.86% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 105144607 # Type of FU issued
|
|
system.cpu.iq.rate 1.956050 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 660808 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.006285 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 264447444 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 144880593 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 102675373 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 678 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 959 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 105805083 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 332 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 440146 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6898310 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6801 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 6412 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 773563 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 31426 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3892580 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 959936 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 127408 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 118169460 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 310371 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 29472276 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 5518407 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 66175 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 6842 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 6412 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 445895 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 445553 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 891448 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 104166950 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 25284184 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 977657 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 12698 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 30340262 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 21325081 # Number of branches executed
|
|
system.cpu.iew.exec_stores 5056078 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.937862 # Inst execution rate
|
|
system.cpu.iew.wb_sent 102951696 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 102675661 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 62239721 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 104280591 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.910119 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.596849 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 26919455 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 832928 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 49526960 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.842491 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.540649 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 20031869 40.45% 40.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13152738 26.56% 67.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4167621 8.41% 75.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 3431174 6.93% 82.35% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1533592 3.10% 85.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 731516 1.48% 86.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 947722 1.91% 88.83% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 252646 0.51% 89.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5278082 10.66% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 49526960 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
|
|
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27318810 # Number of memory references committed
|
|
system.cpu.commit.loads 22573966 # Number of loads committed
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
|
system.cpu.commit.branches 18732304 # Number of branches committed
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 5278082 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 162415559 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 240257118 # The number of ROB writes
|
|
system.cpu.timesIdled 46037 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 334002 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
|
|
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.593373 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.593373 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.685281 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.685281 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 495496517 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 120533542 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 149 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 362 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 29086571 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 4503595847 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 904588 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 904588 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 942920 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 43775 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 43775 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1457 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838192 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 2839649 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120995392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 121041920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 121041920 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 1888563000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1095499 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1421456489 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
|
|
system.cpu.icache.replacements 4 # number of replacements
|
|
system.cpu.icache.tagsinuse 627.794494 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 13838883 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 727 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 19035.602476 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 627.794494 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.306540 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.306540 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 13838883 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 13838883 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 13838883 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 13838883 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 13838883 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 13838883 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 984 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 66043999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 66043999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 66043999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 66043999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 66043999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 66043999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 13839867 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 13839867 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 13839867 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 13839867 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 13839867 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 13839867 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67117.885163 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 67117.885163 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 67117.885163 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 67117.885163 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 62.300000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 730 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 730 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 730 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 730 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 730 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 730 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49961500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 49961500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49961500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 49961500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49961500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 49961500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68440.410959 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68440.410959 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68440.410959 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 68440.410959 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 10730.679646 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1831381 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 15490 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 118.229890 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 9888.279908 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 613.185142 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 229.214596 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.301766 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.018713 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.006995 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.327474 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 903579 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 903605 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 942920 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 942920 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 29237 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 29237 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 932816 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 932842 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 932816 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 932842 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 701 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 980 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 15518 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 15518 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48961500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19173000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 68134500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 895149000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 895149000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 48961500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 914322000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 963283500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 48961500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 914322000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 963283500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 727 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 903858 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 904585 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 942920 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 942920 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43775 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 43775 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 727 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 947633 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 948360 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 727 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 947633 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 948360 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964237 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332107 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.332107 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964237 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.016363 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964237 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.016363 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69845.221113 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68720.430108 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69525 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61573.049938 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61573.049938 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69845.221113 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61707.633124 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 62075.235211 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69845.221113 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61707.633124 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 62075.235211 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 700 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 15507 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40240750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15233500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55474250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714861250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714861250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40240750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730094750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 770335500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40240750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730094750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 770335500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332107 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332107 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57486.785714 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56630.111524 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57248.968008 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49171.911542 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49171.911542 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 943537 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3672.136580 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 28138091 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 947633 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 29.693026 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 7986158000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3672.136580 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.896518 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.896518 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23597541 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 23597541 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4532751 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4532751 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3906 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3906 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 28130292 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 28130292 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 28130292 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 28130292 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1173737 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1173737 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 202230 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 202230 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1375967 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1375967 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1375967 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1375967 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887682000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 13887682000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7842358356 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 7842358356 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 236000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 236000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 21730040356 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 21730040356 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 21730040356 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 21730040356 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24771278 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 24771278 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3913 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3913 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 29506259 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 29506259 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 29506259 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 29506259 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047383 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.047383 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042710 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.042710 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.046633 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.046633 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.046633 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.046633 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11832.021995 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11832.021995 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38779.401454 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38779.401454 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33714.285714 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33714.285714 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 15792.559237 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 15792.559237 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 153985 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 23865 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.452336 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 942920 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 942920 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269859 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 269859 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158472 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 158472 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 428331 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 428331 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 428331 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 428331 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903878 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 903878 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43758 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 43758 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 947636 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 947636 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 947636 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 947636 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9991782011 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9991782011 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1252450464 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1252450464 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11244232475 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 11244232475 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11244232475 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 11244232475 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036489 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009241 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.348055 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.348055 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28622.205402 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28622.205402 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|