74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
414 lines
47 KiB
Text
414 lines
47 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.800193 # Number of seconds simulated
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sim_ticks 1800193398000 # Number of ticks simulated
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final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 510604 # Simulator instruction rate (inst/s)
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host_op_rate 940816 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1044499940 # Simulator tick rate (ticks/s)
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host_mem_usage 295340 # Number of bytes of host memory used
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host_seconds 1723.50 # Real time elapsed on the host
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sim_insts 880025278 # Number of instructions simulated
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sim_ops 1621493928 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 160704 # Number of bytes written to this memory
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system.physmem.bytes_written::total 160704 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 2511 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 2511 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 934548 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 89270 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 89270 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 89270 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 1049487 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 5039 # Transaction distribution
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system.membus.trans_dist::ReadResp 5039 # Transaction distribution
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system.membus.trans_dist::Writeback 2511 # Transaction distribution
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system.membus.trans_dist::ReadExReq 21970 # Transaction distribution
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system.membus.trans_dist::ReadExResp 21970 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 1889280 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.numCycles 3600386796 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 880025278 # Number of instructions committed
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system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 2123381 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1621354440 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 607228180 # number of memory refs
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system.cpu.num_load_insts 419042122 # Number of load instructions
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system.cpu.num_store_insts 188186058 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 3600386796 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 4 # number of replacements
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system.cpu.icache.tagsinuse 660.197305 # Cycle average of tags in use
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system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 660.197305 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 1186515974 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 1186515974 # number of overall hits
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system.cpu.icache.overall_hits::total 1186515974 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
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system.cpu.icache.overall_misses::total 722 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 39712000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 39712000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 39712000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 39712000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 39712000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 39712000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 1186516696 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 1186516696 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 1186516696 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55002.770083 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 55002.770083 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 55002.770083 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 55002.770083 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38268000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 38268000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38268000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 38268000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38268000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 38268000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53002.770083 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53002.770083 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 2532 # number of replacements
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system.cpu.l2cache.tagsinuse 22211.029315 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 21021.301343 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.677827 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 422980 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 222752 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 222752 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.data 415761 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 415761 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 415761 # number of overall hits
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system.cpu.l2cache.overall_hits::total 415761 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 4317 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 5039 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 21970 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 21970 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 26287 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 27009 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses
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system.cpu.l2cache.overall_misses::total 27009 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37546000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 262030000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143343000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 1143343000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 37546000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 1367827000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 1405373000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 37546000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 1367827000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 1405373000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::writebacks 422980 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 422980 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 442048 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 442770 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021878 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.025443 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089775 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.089775 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.059466 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.061000 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.770083 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.396904 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52041.101502 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52041.101502 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 52033.507349 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 52033.507349 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 2511 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 2511 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21970 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21970 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 26287 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 27009 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 26287 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 27009 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28882000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201562000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879703000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879703000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28882000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052383000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1081265000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28882000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052383000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1081265000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089775 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089775 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.770083 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.396904 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.101502 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40041.101502 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 437952 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4094.905740 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 606786132 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 1372.670235 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 771788000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.905740 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 418844796 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 418844796 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 606786132 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 606786132 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 606786132 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 606786132 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 419042122 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 419042122 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 607228180 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 607228180 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 607228180 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 607228180 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 422980 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|