x86 regressions: updates due to new instructions and cpuid
This commit is contained in:
Nilay Vaish
parent
f2bcf4f01c
commit
4526f33062
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@ -1,26 +1,26 @@
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Real time: Jan/14/2013 10:13:32
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Real time: Jan/14/2013 22:52:15
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 413
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Elapsed_time_in_minutes: 6.88333
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Elapsed_time_in_hours: 0.114722
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Elapsed_time_in_days: 0.00478009
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Elapsed_time_in_seconds: 462
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Elapsed_time_in_minutes: 7.7
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Elapsed_time_in_hours: 0.128333
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Elapsed_time_in_days: 0.00534722
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Virtual_time_in_seconds: 413.38
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Virtual_time_in_minutes: 6.88967
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Virtual_time_in_hours: 0.114828
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Virtual_time_in_days: 0.00478449
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Virtual_time_in_seconds: 461.58
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Virtual_time_in_minutes: 7.693
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Virtual_time_in_hours: 0.128217
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Virtual_time_in_days: 0.00534236
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Ruby_current_time: 10410012988
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Ruby_current_time: 10409964586
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Ruby_start_time: 0
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Ruby_cycles: 10410012988
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Ruby_cycles: 10409964586
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mbytes_resident: 588.977
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mbytes_total: 828.605
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resident_ratio: 0.710814
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mbytes_resident: 590.25
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mbytes_total: 829.625
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resident_ratio: 0.711475
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ruby_cycles_executed: [ 10410012989 10410012989 ]
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ruby_cycles_executed: [ 10409964587 10409964587 ]
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Busy Controller Counts:
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L1Cache-0:0 L1Cache-1:0
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@ -30,18 +30,18 @@ DMA-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154767676 average: 1.00012 | standard deviation: 0.0109603 | 0 154749082 18594 ]
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sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154388062 average: 1.00012 | standard deviation: 0.0108509 | 0 154369882 18180 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 2 max: 236 count: 154767675 average: 3.45133 | standard deviation: 5.08508 | 0 152082948 0 0 0 0 0 0 0 926780 2045 1452598 1543 98967 1815 27128 360 207 3 49 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3362 5780 7262 9598 51179 184 505 82 107 136 4 29 2 7 6 6 11 4 5 23 4 17 8 9 15 11 471 4264 10010 17502 13223 43114 813 894 2364 288 781 16 18 42 15 24 13 21 50 10 30 9 26 49 14 23 11 21 20 81 147 128 144 237 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 2 max: 216 count: 15353007 average: 5.08842 | standard deviation: 8.50498 | 0 13922473 0 0 0 0 0 0 0 116145 265 1232650 928 35561 1127 12313 285 170 3 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 887 725 2463 2782 1967 61 77 31 29 29 1 1 0 0 0 2 3 2 2 2 1 2 4 2 0 3 0 1320 2750 4751 6080 5745 316 282 232 119 113 8 7 4 7 5 6 6 7 1 3 2 8 3 7 3 5 7 6 22 13 57 47 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 2 max: 236 count: 9752758 average: 5.12122 | standard deviation: 15.1327 | 0 9401253 0 0 0 0 0 0 0 27237 27 167380 295 28892 378 2214 46 13 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3337 3550 6358 49095 86 397 40 70 107 2 26 2 2 6 3 7 2 2 21 3 13 3 3 13 5 469 953 2931 8561 6761 36978 325 523 2027 157 663 8 10 37 5 16 3 11 42 4 25 4 15 44 4 20 5 11 11 20 101 56 96 215 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 2 max: 212 count: 128448361 average: 3.11278 | standard deviation: 1.97284 | 0 127661323 0 0 0 0 0 0 0 767930 1689 1597 184 154 39 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1612 1614 805 34 43 19 27 6 1 0 1 2 0 5 0 1 1 0 1 0 0 2 0 4 1 2 2 1978 4253 4132 218 194 166 78 102 6 2 0 1 1 3 3 4 3 1 4 2 3 3 2 3 0 1 3 3 39 33 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read: [binsize: 2 max: 214 count: 526633 average: 6.20648 | standard deviation: 9.4774 | 0 453002 0 0 0 0 0 0 0 10683 54 32916 31 18977 59 9489 9 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 86 385 383 51 15 4 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 51 15 121 166 3 9 3 6 2 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 343458 average: 5.69413 | standard deviation: 7.99933 | 0 301439 0 0 0 0 0 0 0 4785 10 18055 105 15383 212 3112 20 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 18 59 41 23 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 25 43 43 31 3 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 343458 average: 3 | standard deviation: 0 | 0 0 0 343458 ]
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miss_latency_NULL: [binsize: 2 max: 236 count: 154767675 average: 3.45133 | standard deviation: 5.08508 | 0 152082948 0 0 0 0 0 0 0 926780 2045 1452598 1543 98967 1815 27128 360 207 3 49 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3362 5780 7262 9598 51179 184 505 82 107 136 4 29 2 7 6 6 11 4 5 23 4 17 8 9 15 11 471 4264 10010 17502 13223 43114 813 894 2364 288 781 16 18 42 15 24 13 21 50 10 30 9 26 49 14 23 11 21 20 81 147 128 144 237 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency: [binsize: 2 max: 273 count: 154388061 average: 3.45295 | standard deviation: 5.08106 | 0 151690537 0 0 0 0 0 0 0 932040 1703 1471533 1379 91424 1420 25290 352 173 9 51 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3364 5598 7271 9474 50989 163 513 82 90 127 6 24 4 6 9 8 14 4 5 25 4 18 6 7 12 11 470 4229 10028 17505 13231 42632 784 872 2277 305 815 8 29 37 18 24 23 26 53 8 26 13 20 33 16 22 11 24 27 83 131 126 141 264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 2 max: 216 count: 15287552 average: 5.10334 | standard deviation: 8.51891 | 0 13850933 0 0 0 0 0 0 0 114268 255 1245097 853 32879 910 11079 294 137 7 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 911 726 2346 2634 1956 44 90 30 21 27 1 2 1 1 2 2 4 3 3 2 2 3 5 1 1 4 0 1351 2838 4647 6042 5788 291 264 240 135 110 0 10 3 8 6 12 9 4 3 5 5 4 3 7 8 2 6 4 27 18 45 48 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 2 max: 273 count: 9717504 average: 5.12149 | standard deviation: 15.1012 | 0 9364126 0 0 0 0 0 0 0 26595 28 173015 272 26742 292 2182 35 8 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3242 3694 6375 48918 84 398 40 60 99 3 20 3 1 7 4 9 1 1 23 2 13 0 4 10 4 468 868 2785 8639 6835 36479 336 487 1937 162 695 8 13 32 7 16 4 11 46 3 18 3 12 29 5 11 6 13 18 15 84 59 91 238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 2 max: 212 count: 128175950 average: 3.11389 | standard deviation: 1.98122 | 0 127382199 0 0 0 0 0 0 0 775103 1366 1499 157 150 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1597 1530 790 33 43 20 20 6 2 0 2 2 0 4 0 1 1 0 1 0 0 2 0 2 0 2 2 1997 4318 4166 202 165 151 106 98 1 6 0 5 1 3 2 7 6 3 1 3 5 4 1 4 3 3 5 5 41 29 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read: [binsize: 2 max: 214 count: 522203 average: 6.16921 | standard deviation: 9.47561 | 0 450065 0 0 0 0 0 0 0 10577 45 32980 16 17715 77 9308 9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 83 382 379 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 68 17 113 166 3 12 2 7 2 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 342426 average: 5.64732 | standard deviation: 7.89763 | 0 300788 0 0 0 0 0 0 0 5497 9 18942 81 13938 94 2721 14 18 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 53 20 2 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5 19 36 39 34 3 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 342426 average: 3 | standard deviation: 0 | 0 0 0 342426 ]
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miss_latency_NULL: [binsize: 2 max: 273 count: 154388061 average: 3.45295 | standard deviation: 5.08106 | 0 151690537 0 0 0 0 0 0 0 932040 1703 1471533 1379 91424 1420 25290 352 173 9 51 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3364 5598 7271 9474 50989 163 513 82 90 127 6 24 4 6 9 8 14 4 5 25 4 18 6 7 12 11 470 4229 10028 17505 13231 42632 784 872 2277 305 815 8 29 37 18 24 23 26 53 8 26 13 20 33 16 22 11 24 27 83 131 126 141 264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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@ -52,12 +52,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 0
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miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15353007 average: 5.08842 | standard deviation: 8.50498 | 0 13922473 0 0 0 0 0 0 0 116145 265 1232650 928 35561 1127 12313 285 170 3 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 887 725 2463 2782 1967 61 77 31 29 29 1 1 0 0 0 2 3 2 2 2 1 2 4 2 0 3 0 1320 2750 4751 6080 5745 316 282 232 119 113 8 7 4 7 5 6 6 7 1 3 2 8 3 7 3 5 7 6 22 13 57 47 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 2 max: 236 count: 9752758 average: 5.12122 | standard deviation: 15.1327 | 0 9401253 0 0 0 0 0 0 0 27237 27 167380 295 28892 378 2214 46 13 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3337 3550 6358 49095 86 397 40 70 107 2 26 2 2 6 3 7 2 2 21 3 13 3 3 13 5 469 953 2931 8561 6761 36978 325 523 2027 157 663 8 10 37 5 16 3 11 42 4 25 4 15 44 4 20 5 11 11 20 101 56 96 215 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 128448361 average: 3.11278 | standard deviation: 1.97284 | 0 127661323 0 0 0 0 0 0 0 767930 1689 1597 184 154 39 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1612 1614 805 34 43 19 27 6 1 0 1 2 0 5 0 1 1 0 1 0 0 2 0 4 1 2 2 1978 4253 4132 218 194 166 78 102 6 2 0 1 1 3 3 4 3 1 4 2 3 3 2 3 0 1 3 3 39 33 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 526633 average: 6.20648 | standard deviation: 9.4774 | 0 453002 0 0 0 0 0 0 0 10683 54 32916 31 18977 59 9489 9 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 86 385 383 51 15 4 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 51 15 121 166 3 9 3 6 2 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 343458 average: 5.69413 | standard deviation: 7.99933 | 0 301439 0 0 0 0 0 0 0 4785 10 18055 105 15383 212 3112 20 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 18 59 41 23 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 25 43 43 31 3 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 343458 average: 3 | standard deviation: 0 | 0 0 0 343458 ]
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miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15287552 average: 5.10334 | standard deviation: 8.51891 | 0 13850933 0 0 0 0 0 0 0 114268 255 1245097 853 32879 910 11079 294 137 7 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 911 726 2346 2634 1956 44 90 30 21 27 1 2 1 1 2 2 4 3 3 2 2 3 5 1 1 4 0 1351 2838 4647 6042 5788 291 264 240 135 110 0 10 3 8 6 12 9 4 3 5 5 4 3 7 8 2 6 4 27 18 45 48 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 2 max: 273 count: 9717504 average: 5.12149 | standard deviation: 15.1012 | 0 9364126 0 0 0 0 0 0 0 26595 28 173015 272 26742 292 2182 35 8 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3242 3694 6375 48918 84 398 40 60 99 3 20 3 1 7 4 9 1 1 23 2 13 0 4 10 4 468 868 2785 8639 6835 36479 336 487 1937 162 695 8 13 32 7 16 4 11 46 3 18 3 12 29 5 11 6 13 18 15 84 59 91 238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 128175950 average: 3.11389 | standard deviation: 1.98122 | 0 127382199 0 0 0 0 0 0 0 775103 1366 1499 157 150 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1597 1530 790 33 43 20 20 6 2 0 2 2 0 4 0 1 1 0 1 0 0 2 0 2 0 2 2 1997 4318 4166 202 165 151 106 98 1 6 0 5 1 3 2 7 6 3 1 3 5 4 1 4 3 3 5 5 41 29 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 522203 average: 6.16921 | standard deviation: 9.47561 | 0 450065 0 0 0 0 0 0 0 10577 45 32980 16 17715 77 9308 9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 83 382 379 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 68 17 113 166 3 12 2 7 2 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 342426 average: 5.64732 | standard deviation: 7.89763 | 0 300788 0 0 0 0 0 0 0 5497 9 18942 81 13938 94 2721 14 18 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 53 20 2 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5 19 36 39 34 3 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 342426 average: 3 | standard deviation: 0 | 0 0 0 342426 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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@ -71,11 +71,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 37 count: 11102774 average: 0.602872 | standard deviation: 1.4337 | 9428519 3298 1963 3123 1660358 3178 362 299 341 1114 46 54 45 70 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4899179 average: 0.0429682 | standard deviation: 0.408932 | 4844093 1818 1298 2395 49214 270 22 12 25 32 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 37 count: 6203595 average: 1.04505 | standard deviation: 1.76171 | 4584426 1480 665 728 1611144 2908 340 287 316 1082 46 54 45 70 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4764254 average: 0.043552 | standard deviation: 0.412206 | 4710335 1474 1074 2162 48904 216 21 12 25 31 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 134925 average: 0.0223532 | standard deviation: 0.268086 | 133758 344 224 233 310 54 1 0 0 1 ]
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Total_delay_cycles: [binsize: 1 max: 20 count: 11148135 average: 0.604011 | standard deviation: 1.43412 | 9463752 2800 1716 2621 1672813 2611 326 245 267 831 14 9 33 96 0 0 0 0 0 0 1 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4908600 average: 0.0392664 | standard deviation: 0.391117 | 4858225 1610 1216 1960 45293 234 18 5 15 24 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 6239535 average: 1.04829 | standard deviation: 1.7624 | 4605527 1190 500 661 1627520 2377 308 240 252 807 14 9 33 96 0 0 0 0 0 0 1 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783054 average: 0.0397181 | standard deviation: 0.3938 | 4733713 1359 968 1776 44998 181 18 4 15 22 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 125546 average: 0.0220557 | standard deviation: 0.26914 | 124512 251 248 184 295 53 0 1 0 2 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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@ -87,82 +87,82 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4899179 average: 0.0429682 |
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Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 413
|
||||
user_time: 461
|
||||
system_time: 0
|
||||
page_reclaims: 142263
|
||||
page_reclaims: 142165
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 16
|
||||
block_outputs: 504
|
||||
block_inputs: 0
|
||||
block_outputs: 544
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 8573871 68590968
|
||||
total_msg_count_Request_Control: 402900 3223200
|
||||
total_msg_count_Response_Data: 8871192 638725824
|
||||
total_msg_count_Response_Control: 11214789 89718312
|
||||
total_msg_count_Writeback_Data: 4845120 348848640
|
||||
total_msg_count_Writeback_Control: 241380 1931040
|
||||
total_msgs: 34149252 total_bytes: 1151037984
|
||||
total_msg_count_Control: 8609013 68872104
|
||||
total_msg_count_Request_Control: 374943 2999544
|
||||
total_msg_count_Response_Data: 8904417 641118024
|
||||
total_msg_count_Response_Control: 11255862 90046896
|
||||
total_msg_count_Writeback_Data: 4892238 352241136
|
||||
total_msg_count_Writeback_Control: 242529 1940232
|
||||
total_msgs: 34279002 total_bytes: 1157217936
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0911536
|
||||
links_utilized_percent_switch_0_link_0: 0.0987886 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.0835187 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.0914405
|
||||
links_utilized_percent_switch_0_link_0: 0.0993568 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.0835242 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 70808 566464 [ 70808 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 2104978 151558416 [ 0 2104978 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 1552199 12417592 [ 0 1552199 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 2125604 17004832 [ 2125604 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 64998 4679856 [ 0 64998 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 1603807 12830456 [ 0 30257 1573550 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1445625 104085000 [ 1445565 60 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 63591 508728 [ 63591 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 66162 529296 [ 66162 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 2118929 152562888 [ 0 2118929 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 1549489 12395912 [ 0 1549489 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 2137847 17102776 [ 2137847 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 60658 4367376 [ 0 60658 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 1598104 12784832 [ 0 28048 1570056 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1449697 104378184 [ 1449587 110 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 60538 484304 [ 60538 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0193523
|
||||
links_utilized_percent_switch_1_link_0: 0.0246033 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.0141014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.0196
|
||||
links_utilized_percent_switch_1_link_0: 0.0247412 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.0144589 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 64117 512936 [ 64117 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 536143 38602296 [ 0 536143 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 233007 1864056 [ 0 233007 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 559123 4472984 [ 559123 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 62234 4480848 [ 0 62234 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 275077 2200616 [ 0 25012 250065 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 169415 12197880 [ 169228 187 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 16869 134952 [ 16869 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 59384 475072 [ 59384 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 538601 38779272 [ 0 538601 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 244316 1954528 [ 0 244316 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 559677 4477416 [ 559677 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 57457 4136904 [ 0 57457 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 283787 2270296 [ 0 23091 260696 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 181049 13035528 [ 180829 220 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 20305 162440 [ 20305 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.113347
|
||||
links_utilized_percent_switch_2_link_0: 0.10197 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.124723 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.11409
|
||||
links_utilized_percent_switch_2_link_0: 0.10253 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.12565 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 2684727 21477816 [ 2684727 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 221053 15915816 [ 0 221053 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1940242 15521936 [ 0 116627 1823615 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 1615040 116282880 [ 1614793 247 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 80460 643680 [ 80460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 173230 1385840 [ 173230 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 133050 1064400 [ 133050 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 2656602 191275344 [ 0 2656602 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1751674 14013392 [ 0 1751674 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Control: 2697524 21580192 [ 2697524 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 216185 15565320 [ 0 216185 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1945956 15567648 [ 0 115204 1830752 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 1630746 117413712 [ 1630416 330 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 123851 990808 [ 123851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 2677877 192807144 [ 0 2677877 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1763446 14107568 [ 0 1763446 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 0.00650054
|
||||
links_utilized_percent_switch_3_link_0: 0.00499545 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.00800563 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.00646039
|
||||
links_utilized_percent_switch_3_link_0: 0.00496714 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.00795363 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Control: 173230 1385840 [ 173230 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 94890 6832080 [ 0 94890 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 12815 102520 [ 0 12815 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 173230 12472560 [ 0 173230 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 107705 861640 [ 0 107705 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 172147 12394584 [ 0 172147 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 106617 852936 [ 0 106617 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
|
|
@ -173,117 +173,117 @@ links_utilized_percent_switch_4: 0
|
|||
|
||||
switch_5_inlinks: 5
|
||||
switch_5_outlinks: 5
|
||||
links_utilized_percent_switch_5: 0.0460715
|
||||
links_utilized_percent_switch_5_link_0: 0.0987886 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.0246033 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_2: 0.10197 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_3: 0.00499545 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5: 0.0463191
|
||||
links_utilized_percent_switch_5_link_0: 0.0993568 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.0247412 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_2: 0.10253 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_3: 0.00496714 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 70808 566464 [ 70808 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 2104978 151558416 [ 0 2104978 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 1552199 12417592 [ 0 1552199 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Request_Control: 64117 512936 [ 64117 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 536143 38602296 [ 0 536143 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 233007 1864056 [ 0 233007 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Control: 2684727 21477816 [ 2684727 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Data: 221053 15915816 [ 0 221053 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Control: 1940242 15521936 [ 0 116627 1823615 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Data: 1615040 116282880 [ 1614793 247 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Control: 80460 643680 [ 80460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Control: 173230 1385840 [ 173230 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Data: 94890 6832080 [ 0 94890 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Control: 12815 102520 [ 0 12815 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 66162 529296 [ 66162 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 2118929 152562888 [ 0 2118929 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 1549489 12395912 [ 0 1549489 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Request_Control: 59384 475072 [ 59384 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 538601 38779272 [ 0 538601 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 244316 1954528 [ 0 244316 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Control: 2697524 21580192 [ 2697524 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Data: 216185 15565320 [ 0 216185 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Response_Control: 1945956 15567648 [ 0 115204 1830752 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Data: 1630746 117413712 [ 1630416 330 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_2_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_3_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 500458
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 500458
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 519318
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 519318
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 500458 100%
|
||||
system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 519318 100%
|
||||
|
||||
Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 1625146
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1625146
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 1618529
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1618529
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 80.0217%
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 19.9783%
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 80.1036%
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 19.8964%
|
||||
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1625146 100%
|
||||
system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1618529 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [11657148 3695859 ] 15353007
|
||||
Ifetch [108817459 19630908 ] 128448367
|
||||
Store [7712341 3253966 ] 10966307
|
||||
Inv [30317 25199 ] 55516
|
||||
L1_Replacement [2079336 509005 ] 2588341
|
||||
Fwd_GETX [15984 15602 ] 31586
|
||||
Fwd_GETS [24502 23316 ] 47818
|
||||
Load [11524805 3762747 ] 15287552
|
||||
Ifetch [108056114 20119843 ] 128175957
|
||||
Store [7679126 3245433 ] 10924559
|
||||
Inv [28158 23311 ] 51469
|
||||
L1_Replacement [2094944 513621 ] 2608565
|
||||
Fwd_GETX [15350 14689 ] 30039
|
||||
Fwd_GETS [22649 21384 ] 44033
|
||||
Fwd_GET_INSTR [5 0 ] 5
|
||||
Data [1791 950 ] 2741
|
||||
Data_Exclusive [1225558 83079 ] 1308637
|
||||
DataS_fromL1 [23316 24507 ] 47823
|
||||
Data_all_Acks [854313 427607 ] 1281920
|
||||
Ack [20626 22980 ] 43606
|
||||
Ack_all [22417 23930 ] 46347
|
||||
WB_Ack [1509156 186097 ] 1695253
|
||||
Data [1528 1030 ] 2558
|
||||
Data_Exclusive [1226643 92917 ] 1319560
|
||||
DataS_fromL1 [21384 22654 ] 44038
|
||||
Data_all_Acks [869374 422000 ] 1291374
|
||||
Ack [18918 21076 ] 39994
|
||||
Ack_all [20446 22106 ] 42552
|
||||
WB_Ack [1510125 201134 ] 1711259
|
||||
PF_Load [0 0 ] 0
|
||||
PF_Ifetch [0 0 ] 0
|
||||
PF_Store [0 0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [1283896 113817 ] 1397713
|
||||
NP Ifetch [500075 286188 ] 786263
|
||||
NP Store [296389 110024 ] 406413
|
||||
NP Inv [6714 2646 ] 9360
|
||||
NP Load [1280963 125209 ] 1406172
|
||||
NP Ifetch [519207 274210 ] 793417
|
||||
NP Store [295798 115226 ] 411024
|
||||
NP Inv [6575 2932 ] 9507
|
||||
NP L1_Replacement [0 0 ] 0
|
||||
NP PF_Load [0 0 ] 0
|
||||
NP PF_Ifetch [0 0 ] 0
|
||||
NP PF_Store [0 0 ] 0
|
||||
|
||||
I Load [16574 16247 ] 32821
|
||||
I Ifetch [383 392 ] 775
|
||||
I Store [7661 9474 ] 17135
|
||||
I Load [15537 14910 ] 30447
|
||||
I Ifetch [111 223 ] 334
|
||||
I Store [7313 8822 ] 16135
|
||||
I Inv [0 0 ] 0
|
||||
I L1_Replacement [14969 11940 ] 26909
|
||||
I L1_Replacement [13897 11112 ] 25009
|
||||
I PF_Load [0 0 ] 0
|
||||
I PF_Ifetch [0 0 ] 0
|
||||
I PF_Store [0 0 ] 0
|
||||
|
||||
S Load [793915 479736 ] 1273651
|
||||
S Ifetch [108316996 19344327 ] 127661323
|
||||
S Store [20626 22981 ] 43607
|
||||
S Inv [23501 22199 ] 45700
|
||||
S L1_Replacement [555211 310968 ] 866179
|
||||
S Load [750790 485617 ] 1236407
|
||||
S Ifetch [107536791 19845408 ] 127382199
|
||||
S Store [18918 21077 ] 39995
|
||||
S Inv [21405 20030 ] 41435
|
||||
S L1_Replacement [570922 301375 ] 872297
|
||||
S PF_Load [0 0 ] 0
|
||||
S PF_Store [0 0 ] 0
|
||||
|
||||
E Load [3115881 532241 ] 3648122
|
||||
E Load [3053717 595327 ] 3649044
|
||||
E Ifetch [0 0 ] 0
|
||||
E Store [118477 30338 ] 148815
|
||||
E Inv [42 166 ] 208
|
||||
E L1_Replacement [1105264 51360 ] 1156624
|
||||
E Fwd_GETX [95 109 ] 204
|
||||
E Fwd_GETS [1520 1047 ] 2567
|
||||
E Store [120709 32410 ] 153119
|
||||
E Inv [68 128 ] 196
|
||||
E L1_Replacement [1104096 58886 ] 1162982
|
||||
E Fwd_GETX [187 209 ] 396
|
||||
E Fwd_GETS [1490 1115 ] 2605
|
||||
E Fwd_GET_INSTR [1 0 ] 1
|
||||
E PF_Load [0 0 ] 0
|
||||
E PF_Store [0 0 ] 0
|
||||
|
||||
M Load [6446882 2553818 ] 9000700
|
||||
M Load [6423798 2541684 ] 8965482
|
||||
M Ifetch [0 0 ] 0
|
||||
M Store [7269188 3081149 ] 10350337
|
||||
M Inv [60 187 ] 247
|
||||
M L1_Replacement [403892 134737 ] 538629
|
||||
M Fwd_GETX [15889 15493 ] 31382
|
||||
M Fwd_GETS [22982 22269 ] 45251
|
||||
M Store [7236388 3067898 ] 10304286
|
||||
M Inv [110 220 ] 330
|
||||
M L1_Replacement [406029 142248 ] 548277
|
||||
M Fwd_GETX [15163 14480 ] 29643
|
||||
M Fwd_GETS [21159 20269 ] 41428
|
||||
M Fwd_GET_INSTR [4 0 ] 4
|
||||
M PF_Load [0 0 ] 0
|
||||
M PF_Store [0 0 ] 0
|
||||
|
|
@ -293,9 +293,9 @@ IS Ifetch [0 0 ] 0
|
|||
IS Store [0 0 ] 0
|
||||
IS Inv [0 0 ] 0
|
||||
IS L1_Replacement [0 0 ] 0
|
||||
IS Data_Exclusive [1225558 83079 ] 1308637
|
||||
IS DataS_fromL1 [23316 24507 ] 47823
|
||||
IS Data_all_Acks [552054 309058 ] 861112
|
||||
IS Data_Exclusive [1226643 92917 ] 1319560
|
||||
IS DataS_fromL1 [21384 22654 ] 44038
|
||||
IS Data_all_Acks [567791 298981 ] 866772
|
||||
IS PF_Load [0 0 ] 0
|
||||
IS PF_Store [0 0 ] 0
|
||||
|
||||
|
|
@ -304,8 +304,8 @@ IM Ifetch [0 0 ] 0
|
|||
IM Store [0 0 ] 0
|
||||
IM Inv [0 0 ] 0
|
||||
IM L1_Replacement [0 0 ] 0
|
||||
IM Data [1791 950 ] 2741
|
||||
IM Data_all_Acks [302259 118549 ] 420808
|
||||
IM Data [1528 1030 ] 2558
|
||||
IM Data_all_Acks [301583 123019 ] 424602
|
||||
IM Ack [0 0 ] 0
|
||||
IM PF_Load [0 0 ] 0
|
||||
IM PF_Store [0 0 ] 0
|
||||
|
|
@ -315,8 +315,8 @@ SM Ifetch [0 0 ] 0
|
|||
SM Store [0 0 ] 0
|
||||
SM Inv [0 1 ] 1
|
||||
SM L1_Replacement [0 0 ] 0
|
||||
SM Ack [20626 22980 ] 43606
|
||||
SM Ack_all [22417 23930 ] 46347
|
||||
SM Ack [18918 21076 ] 39994
|
||||
SM Ack_all [20446 22106 ] 42552
|
||||
SM PF_Load [0 0 ] 0
|
||||
SM PF_Store [0 0 ] 0
|
||||
|
||||
|
|
@ -332,14 +332,14 @@ IS_I PF_Load [0 0 ] 0
|
|||
IS_I PF_Store [0 0 ] 0
|
||||
|
||||
M_I Load [0 0 ] 0
|
||||
M_I Ifetch [5 1 ] 6
|
||||
M_I Ifetch [5 2 ] 7
|
||||
M_I Store [0 0 ] 0
|
||||
M_I Inv [0 0 ] 0
|
||||
M_I L1_Replacement [0 0 ] 0
|
||||
M_I Fwd_GETX [0 0 ] 0
|
||||
M_I Fwd_GETS [0 0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 0 ] 0
|
||||
M_I WB_Ack [1509156 186097 ] 1695253
|
||||
M_I WB_Ack [1510125 201134 ] 1711259
|
||||
M_I PF_Load [0 0 ] 0
|
||||
M_I PF_Store [0 0 ] 0
|
||||
|
||||
|
|
@ -391,108 +391,108 @@ PF_IS_I DataS_fromL1 [0 0 ] 0
|
|||
PF_IS_I Data_all_Acks [0 0 ] 0
|
||||
|
||||
Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 286580
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 286580
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 274433
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 274433
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 286580 100%
|
||||
system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 274433 100%
|
||||
|
||||
Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 272543
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 272543
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 285244
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 285244
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 47.7224%
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 52.2776%
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 49.1225%
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 50.8775%
|
||||
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 272543 100%
|
||||
system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 285244 100%
|
||||
|
||||
Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 252639
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 252639
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 246224
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 246224
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 31.2133%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.11307%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 62.6732%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_UPGRADE: 0.000395822%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 30.3882%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.26543%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 63.346%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_request_type_UPGRADE: 0.000406134%
|
||||
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 252639 100%
|
||||
system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 246224 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [787039 ] 787039
|
||||
L1_GETS [1430768 ] 1430768
|
||||
L1_GETX [423555 ] 423555
|
||||
L1_UPGRADE [43607 ] 43607
|
||||
L1_PUTX [1695253 ] 1695253
|
||||
L1_GET_INSTR [793751 ] 793751
|
||||
L1_GETS [1436868 ] 1436868
|
||||
L1_GETX [427161 ] 427161
|
||||
L1_UPGRADE [39995 ] 39995
|
||||
L1_PUTX [1711259 ] 1711259
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [94736 ] 94736
|
||||
L2_Replacement_clean [12969 ] 12969
|
||||
Mem_Data [173230 ] 173230
|
||||
Mem_Ack [107705 ] 107705
|
||||
WB_Data [47491 ] 47491
|
||||
WB_Data_clean [579 ] 579
|
||||
Ack [1875 ] 1875
|
||||
Ack_all [7047 ] 7047
|
||||
Unblock [47823 ] 47823
|
||||
L2_Replacement [94211 ] 94211
|
||||
L2_Replacement_clean [12406 ] 12406
|
||||
Mem_Data [172147 ] 172147
|
||||
Mem_Ack [106617 ] 106617
|
||||
WB_Data [43746 ] 43746
|
||||
WB_Data_clean [622 ] 622
|
||||
Ack [1695 ] 1695
|
||||
Ack_all [6892 ] 6892
|
||||
Unblock [44038 ] 44038
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [1775792 ] 1775792
|
||||
Exclusive_Unblock [1786714 ] 1786714
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [15439 ] 15439
|
||||
NP L1_GETS [31039 ] 31039
|
||||
NP L1_GETX [126752 ] 126752
|
||||
NP L1_GET_INSTR [15422 ] 15422
|
||||
NP L1_GETS [30790 ] 30790
|
||||
NP L1_GETX [125935 ] 125935
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR [771381 ] 771381
|
||||
SS L1_GETS [74079 ] 74079
|
||||
SS L1_GETX [2996 ] 2996
|
||||
SS L1_UPGRADE [43606 ] 43606
|
||||
SS L1_GET_INSTR [778075 ] 778075
|
||||
SS L1_GETS [73026 ] 73026
|
||||
SS L1_GETX [2798 ] 2798
|
||||
SS L1_UPGRADE [39994 ] 39994
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [237 ] 237
|
||||
SS L2_Replacement_clean [6602 ] 6602
|
||||
SS L2_Replacement [248 ] 248
|
||||
SS L2_Replacement_clean [6448 ] 6448
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [213 ] 213
|
||||
M L1_GETS [1277598 ] 1277598
|
||||
M L1_GETX [262215 ] 262215
|
||||
M L1_GET_INSTR [249 ] 249
|
||||
M L1_GETS [1288770 ] 1288770
|
||||
M L1_GETX [268388 ] 268388
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [94369 ] 94369
|
||||
M L2_Replacement_clean [6042 ] 6042
|
||||
M L2_Replacement [93815 ] 93815
|
||||
M L2_Replacement_clean [5580 ] 5580
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [5 ] 5
|
||||
MT L1_GETS [47818 ] 47818
|
||||
MT L1_GETX [31586 ] 31586
|
||||
MT L1_PUTX [1695253 ] 1695253
|
||||
MT L1_GETS [44033 ] 44033
|
||||
MT L1_GETX [30039 ] 30039
|
||||
MT L1_PUTX [1711259 ] 1711259
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [130 ] 130
|
||||
MT L2_Replacement_clean [325 ] 325
|
||||
MT L2_Replacement [148 ] 148
|
||||
MT L2_Replacement_clean [378 ] 378
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [1 ] 1
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [2 ] 2
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [107705 ] 107705
|
||||
M_I Mem_Ack [106617 ] 106617
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -501,9 +501,9 @@ MT_I L1_GETX [0 ] 0
|
|||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [93 ] 93
|
||||
MT_I WB_Data [117 ] 117
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [37 ] 37
|
||||
MT_I Ack_all [31 ] 31
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -512,9 +512,9 @@ MCT_I L1_GETX [0 ] 0
|
|||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [154 ] 154
|
||||
MCT_I WB_Data [213 ] 213
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [171 ] 171
|
||||
MCT_I Ack_all [165 ] 165
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
|
|
@ -522,8 +522,8 @@ I_I L1_GETX [0 ] 0
|
|||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [1645 ] 1645
|
||||
I_I Ack_all [6602 ] 6602
|
||||
I_I Ack [1454 ] 1454
|
||||
I_I Ack_all [6448 ] 6448
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
|
|
@ -531,8 +531,8 @@ S_I L1_GETX [0 ] 0
|
|||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [230 ] 230
|
||||
S_I Ack_all [237 ] 237
|
||||
S_I Ack [241 ] 241
|
||||
S_I Ack_all [248 ] 248
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -542,7 +542,7 @@ ISS L1_PUTX [0 ] 0
|
|||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [31039 ] 31039
|
||||
ISS Mem_Data [30790 ] 30790
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -552,7 +552,7 @@ IS L1_PUTX [0 ] 0
|
|||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [15439 ] 15439
|
||||
IS Mem_Data [15422 ] 15422
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -562,11 +562,11 @@ IM L1_PUTX [0 ] 0
|
|||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [126752 ] 126752
|
||||
IM Mem_Data [125935 ] 125935
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [179 ] 179
|
||||
SS_MB L1_GETS [193 ] 193
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [1 ] 1
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
|
|
@ -574,19 +574,19 @@ SS_MB L1_PUTX_old [0 ] 0
|
|||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [46602 ] 46602
|
||||
SS_MB Exclusive_Unblock [42792 ] 42792
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [55 ] 55
|
||||
MT_MB L1_GETX [4 ] 4
|
||||
MT_MB L1_GETS [56 ] 56
|
||||
MT_MB L1_GETX [1 ] 1
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [1729190 ] 1729190
|
||||
MT_MB Exclusive_Unblock [1743922 ] 1743922
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -608,9 +608,9 @@ MT_IIB L1_PUTX [0 ] 0
|
|||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [47176 ] 47176
|
||||
MT_IIB WB_Data_clean [579 ] 579
|
||||
MT_IIB Unblock [68 ] 68
|
||||
MT_IIB WB_Data [43375 ] 43375
|
||||
MT_IIB WB_Data_clean [622 ] 622
|
||||
MT_IIB Unblock [41 ] 41
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -621,7 +621,7 @@ MT_IB L1_PUTX [0 ] 0
|
|||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [68 ] 68
|
||||
MT_IB WB_Data [41 ] 41
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
|
@ -634,41 +634,41 @@ MT_SB L1_PUTX [0 ] 0
|
|||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [47755 ] 47755
|
||||
MT_SB Unblock [43997 ] 43997
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 268120
|
||||
memory_reads: 173230
|
||||
memory_writes: 94890
|
||||
memory_refreshes: 540175
|
||||
memory_total_request_delays: 1021995
|
||||
memory_delays_per_request: 3.81171
|
||||
memory_delays_in_input_queue: 40655
|
||||
memory_delays_behind_head_of_bank_queue: 7571
|
||||
memory_delays_stalled_at_head_of_bank_queue: 973769
|
||||
memory_stalls_for_bank_busy: 964415
|
||||
memory_total_requests: 266571
|
||||
memory_reads: 172147
|
||||
memory_writes: 94424
|
||||
memory_refreshes: 536635
|
||||
memory_total_request_delays: 1016562
|
||||
memory_delays_per_request: 3.81348
|
||||
memory_delays_in_input_queue: 40063
|
||||
memory_delays_behind_head_of_bank_queue: 7489
|
||||
memory_delays_stalled_at_head_of_bank_queue: 969010
|
||||
memory_stalls_for_bank_busy: 959685
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 2119
|
||||
memory_stalls_for_bus: 7204
|
||||
memory_stalls_for_arbitration: 2157
|
||||
memory_stalls_for_bus: 7147
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 20
|
||||
memory_stalls_for_read_read_turnaround: 11
|
||||
accesses_per_bank: 8668 7929 8035 8011 8299 8319 8160 8260 8417 8211 8203 8373 8266 8099 8224 7214 8411 8364 8280 8158 8504 8396 9002 8309 8657 8409 8646 9176 9084 8998 8838 8200
|
||||
memory_stalls_for_read_write_turnaround: 15
|
||||
memory_stalls_for_read_read_turnaround: 6
|
||||
accesses_per_bank: 8989 7974 8010 8055 8487 8273 8235 8188 8380 8237 8148 8446 8268 8048 8068 7184 8265 8304 8191 8114 8382 8281 8178 8162 8416 8296 8511 9107 9086 9056 8973 8259
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [173230 ] 173230
|
||||
Data [94890 ] 94890
|
||||
Memory_Data [173230 ] 173230
|
||||
Memory_Ack [94890 ] 94890
|
||||
Fetch [172147 ] 172147
|
||||
Data [94424 ] 94424
|
||||
Memory_Data [172147 ] 172147
|
||||
Memory_Ack [94424 ] 94424
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [12815 ] 12815
|
||||
CleanReplacement [12193 ] 12193
|
||||
|
||||
- Transitions -
|
||||
I Fetch [173230 ] 173230
|
||||
I Fetch [172147 ] 172147
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -684,20 +684,20 @@ ID_W Memory_Ack [0 ] 0
|
|||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [94890 ] 94890
|
||||
M Data [94424 ] 94424
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [12815 ] 12815
|
||||
M CleanReplacement [12193 ] 12193
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [173230 ] 173230
|
||||
IM Memory_Data [172147 ] 172147
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [94890 ] 94890
|
||||
MI Memory_Ack [94424 ] 94424
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,125 +1,125 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.205006 # Number of seconds simulated
|
||||
sim_ticks 5205006494000 # Number of ticks simulated
|
||||
final_tick 5205006494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 5.204982 # Number of seconds simulated
|
||||
sim_ticks 5204982293000 # Number of ticks simulated
|
||||
final_tick 5204982293000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 261635 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 502023 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 12588404140 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 848496 # Number of bytes of host memory used
|
||||
host_seconds 413.48 # Real time elapsed on the host
|
||||
sim_insts 108179755 # Number of instructions simulated
|
||||
sim_ops 207574747 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 174032 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 86216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 870539632 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 69693671 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 49472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 20312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 157047256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 27202450 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1124848257 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 870539632 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 157047256 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1027586888 # Number of instructions bytes read from this memory
|
||||
host_inst_rate 233342 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 447673 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11247967547 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 849540 # Number of bytes of host memory used
|
||||
host_seconds 462.75 # Real time elapsed on the host
|
||||
sim_insts 107978732 # Number of instructions simulated
|
||||
sim_ops 207159910 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 137616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 65352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 864448872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 69078677 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 87568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 42392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 160958728 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 27339153 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1122193510 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 864448872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 160958728 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1025407600 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 48549554 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 21360352 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 72901026 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 818 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 21754 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 10777 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 108817454 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 12176562 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 6184 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 2539 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 19630907 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 4005282 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 144672277 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_written::cpu0.data 48342743 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 21309608 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 72643471 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 810 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 17202 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 8169 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 108056109 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 12053051 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 10946 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 5299 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 20119841 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 4057514 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 144328941 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 7160394 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 2935820 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 10142952 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 6766 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 33436 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 16564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 167250441 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 13389738 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 9505 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 3902 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 30172346 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 5226209 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 216108906 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 167250441 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 30172346 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 197422787 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 574659 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_writes::cpu0.data 7125507 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 2934421 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 10106666 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 6754 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 26439 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 12556 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 166081040 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 13271645 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 16824 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 8145 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 30923972 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 5252497 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 215599871 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 166081040 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 30923972 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 197005012 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 574662 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 9327472 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 4103809 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 14005943 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 581425 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 33436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 16567 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 167250441 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 22717210 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 9505 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 3902 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 30172346 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 9330018 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 230114849 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 818 # Total number of read requests seen
|
||||
system.physmem.bw_write::cpu0.data 9287782 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 4094079 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13956526 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 581415 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 26439 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 12559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 166081040 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 22559427 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 16824 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 8145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 30923972 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 9346576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 229556397 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 810 # Total number of read requests seen
|
||||
system.physmem.writeReqs 46736 # Total number of write requests seen
|
||||
system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 52352 # Total number of bytes read from memory
|
||||
system.physmem.bytesRead 51840 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 35216 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedRd 35152 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 298 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 48 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 80 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 64 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 322 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 3080 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 3056 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 2944 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 2880 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 2912 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 2640 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 3024 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 2800 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 2800 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 2768 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 2992 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 3152 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 2992 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 3016 # Track writes on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 144 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 2944 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 3168 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 3232 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::3 3264 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::4 3120 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::5 2992 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::6 2960 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::7 3096 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::9 2768 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::10 2640 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::11 2736 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 2640 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 2560 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 2768 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 2992 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 63209426000 # Total gap between requests
|
||||
system.physmem.totGap 63181906000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 306 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 298 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 512 # Categorize read packet sizes
|
||||
|
|
@ -143,7 +143,7 @@ system.physmem.neitherpktsize::5 0 # ca
|
|||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 336 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see
|
||||
|
|
@ -209,14 +209,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
|
|||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 40984666 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 52278666 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 3272000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8022000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 50103.50 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 9806.85 # Average bank access latency per request
|
||||
system.physmem.totQLat 34586744 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 44980744 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 3240000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7154000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 42699.68 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 8832.10 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 63910.35 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 55531.78 # Average memory access latency
|
||||
system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -225,11 +225,11 @@ system.physmem.peakBW 16000.00 # Th
|
|||
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.15 # Average write queue length over time
|
||||
system.physmem.readRowHits 695 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 45891 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 84.96 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 98.19 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1329213.65 # Average gap between requests
|
||||
system.physmem.readRowHits 716 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 45919 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 88.40 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 98.25 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1328858.49 # Average gap between requests
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -290,52 +290,52 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.numCycles 10410012988 # number of cpu cycles simulated
|
||||
system.cpu0.numCycles 10407785201 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 93132190 # Number of instructions committed
|
||||
system.cpu0.committedOps 179521943 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 169453705 # Number of integer alu accesses
|
||||
system.cpu0.committedInsts 92551705 # Number of instructions committed
|
||||
system.cpu0.committedOps 178518504 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 168457719 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 16554212 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 169453705 # number of integer instructions
|
||||
system.cpu0.num_conditional_control_insts 16414006 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 168457719 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 0 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 418670977 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 211662649 # number of times the integer registers were written
|
||||
system.cpu0.num_int_register_reads 415888508 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 210334532 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 20198672 # number of memory refs
|
||||
system.cpu0.num_load_insts 13023532 # Number of load instructions
|
||||
system.cpu0.num_store_insts 7175140 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 9667664508.054142 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 742348479.945857 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.071311 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.928689 # Percentage of idle cycles
|
||||
system.cpu0.num_mem_refs 20039545 # number of memory refs
|
||||
system.cpu0.num_load_insts 12899818 # Number of load instructions
|
||||
system.cpu0.num_store_insts 7139727 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 9669886063.125444 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 737899137.874556 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.070899 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.929101 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.numCycles 10407071288 # number of cpu cycles simulated
|
||||
system.cpu1.numCycles 10409964586 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 15047565 # Number of instructions committed
|
||||
system.cpu1.committedOps 28052804 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 27533880 # Number of integer alu accesses
|
||||
system.cpu1.committedInsts 15427027 # Number of instructions committed
|
||||
system.cpu1.committedOps 28641406 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 28123113 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 1864518 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 27533880 # number of integer instructions
|
||||
system.cpu1.num_conditional_control_insts 1978272 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 28123113 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 0 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 71369326 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 30999444 # number of times the integer registers were written
|
||||
system.cpu1.num_int_register_reads 73027794 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 31865306 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 6973948 # number of memory refs
|
||||
system.cpu1.num_load_insts 4014274 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2959674 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10279858503.692720 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 127212784.307279 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.012224 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.987776 # Percentage of idle cycles
|
||||
system.cpu1.num_mem_refs 7025055 # number of memory refs
|
||||
system.cpu1.num_load_insts 4066664 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2958391 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 10280021112.934025 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 129943473.065975 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.012483 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.987517 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ intel_mp_table=system.intel_mp_table
|
|||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -72,11 +73,10 @@ slave=system.membus.master[1]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache l2cache toL2Bus tracer
|
||||
children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -85,6 +85,7 @@ fastmem=false
|
|||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -95,6 +96,7 @@ profile=0
|
|||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
|
|
@ -109,21 +111,16 @@ assoc=4
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
|
|
@ -148,21 +145,16 @@ assoc=2
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dtb.walker.port
|
||||
|
|
@ -175,21 +167,16 @@ assoc=1
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -202,10 +189,13 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
system=system
|
||||
int_master=system.membus.slave[4]
|
||||
int_master=system.membus.slave[3]
|
||||
int_slave=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -225,21 +215,16 @@ assoc=2
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.itb.walker.port
|
||||
|
|
@ -252,25 +237,20 @@ assoc=8
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[3]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
|
|
@ -666,25 +646,20 @@ assoc=8
|
|||
block_size=64
|
||||
clock=1000
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=50
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[18]
|
||||
mem_side=system.membus.slave[2]
|
||||
mem_side=system.membus.slave[4]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
|
|
@ -696,7 +671,7 @@ use_default_range=false
|
|||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112041 # Number of seconds simulated
|
||||
sim_ticks 5112040968500 # Number of ticks simulated
|
||||
final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 5112040970500 # Number of ticks simulated
|
||||
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 468346 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 958973 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11982395829 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354180 # Number of bytes of host memory used
|
||||
host_seconds 426.63 # Real time elapsed on the host
|
||||
sim_insts 199810236 # Number of instructions simulated
|
||||
sim_ops 409125920 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1661898 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3402855 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42518772648 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 621064 # Number of bytes of host memory used
|
||||
host_seconds 120.23 # Real time elapsed on the host
|
||||
sim_insts 199810242 # Number of instructions simulated
|
||||
sim_ops 409125923 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
|
|
@ -209,7 +209,7 @@ system.iocache.tagsinuse 0.042402 # Cy
|
|||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy
|
||||
|
|
@ -260,57 +260,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
|
|||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.numCycles 10224081960 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 10224081964 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199810236 # Number of instructions committed
|
||||
system.cpu.committedOps 409125920 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374289911 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 199810242 # Number of instructions committed
|
||||
system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39954536 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374289911 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374289914 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 915450709 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480322748 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 35624588 # number of memory refs
|
||||
system.cpu.num_mem_refs 35624590 # number of memory refs
|
||||
system.cpu.num_load_insts 27216588 # Number of load instructions
|
||||
system.cpu.num_store_insts 8408000 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770609595.971962 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453472364.028039 # Number of busy cycles
|
||||
system.cpu.num_store_insts 8408002 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 790732 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
|
||||
system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243360722 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243360727 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791251 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
|
||||
|
|
@ -331,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy
|
|||
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5102019608500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
|
||||
|
|
@ -379,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy
|
|||
system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101206384000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
|
||||
|
|
@ -420,21 +420,21 @@ system.cpu.dtb_walker_cache.writebacks::total 2556
|
|||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1621135 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20138167 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20138169 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses
|
||||
|
|
@ -445,12 +445,12 @@ system.cpu.dcache.overall_misses::cpu.data 1623919 #
|
|||
system.cpu.dcache.overall_misses::total 1623919 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
|
||||
|
|
@ -471,16 +471,16 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu
|
|||
system.cpu.dcache.writebacks::total 1534848 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 106558 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 64822.149247 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10405.564957 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ intel_mp_table=system.intel_mp_table
|
|||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -72,11 +73,10 @@ slave=system.membus.master[1]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache l2cache toL2Bus tracer
|
||||
children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -84,6 +84,7 @@ dtb=system.cpu.dtb
|
|||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -92,6 +93,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
|
|
@ -105,21 +107,16 @@ assoc=4
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
|
|
@ -144,21 +141,16 @@ assoc=2
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dtb.walker.port
|
||||
|
|
@ -171,21 +163,16 @@ assoc=1
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
|
|
@ -198,10 +185,13 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
system=system
|
||||
int_master=system.membus.slave[4]
|
||||
int_master=system.membus.slave[3]
|
||||
int_slave=system.membus.master[3]
|
||||
pio=system.membus.master[2]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
|
|
@ -221,21 +211,16 @@ assoc=2
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.itb.walker.port
|
||||
|
|
@ -248,25 +233,20 @@ assoc=8
|
|||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[3]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentBus
|
||||
|
|
@ -662,25 +642,20 @@ assoc=8
|
|||
block_size=64
|
||||
clock=1000
|
||||
forward_snoops=false
|
||||
hash_delay=1
|
||||
hit_latency=50
|
||||
is_top_level=true
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=50
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.master[18]
|
||||
mem_side=system.membus.slave[2]
|
||||
mem_side=system.membus.slave[4]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentBus
|
||||
|
|
@ -692,7 +667,7 @@ use_default_range=false
|
|||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@ sim_seconds 5.191113 # Nu
|
|||
sim_ticks 5191112864000 # Number of ticks simulated
|
||||
final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1106680 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44796411922 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 384016 # Number of bytes of host memory used
|
||||
host_seconds 115.88 # Real time elapsed on the host
|
||||
sim_insts 128244614 # Number of instructions simulated
|
||||
sim_ops 247214600 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1076481 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43574012985 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 651144 # Number of bytes of host memory used
|
||||
host_seconds 119.13 # Real time elapsed on the host
|
||||
sim_insts 128244620 # Number of instructions simulated
|
||||
sim_ops 247214608 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory
|
||||
|
|
@ -179,14 +179,14 @@ system.physmem.wrQLenPdf::29 1 # Wh
|
|||
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 793712000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 2768514000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 14495.10 # Average queueing delay per request
|
||||
system.physmem.avgQLat 14495.06 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 13952.23 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 32447.33 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 32447.29 # Average memory access latency
|
||||
system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -307,21 +307,21 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1
|
|||
system.cpu.numCycles 10382225728 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 128244614 # Number of instructions committed
|
||||
system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 128244620 # Number of instructions committed
|
||||
system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 231949861 # number of integer instructions
|
||||
system.cpu.num_int_insts 231949869 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 22227093 # number of memory refs
|
||||
system.cpu.num_mem_refs 22227095 # number of memory refs
|
||||
system.cpu.num_load_insts 13866667 # Number of load instructions
|
||||
system.cpu.num_store_insts 8360426 # Number of store instructions
|
||||
system.cpu.num_store_insts 8360428 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles
|
||||
|
|
@ -330,19 +330,19 @@ system.cpu.kern.inst.arm 0 # nu
|
|||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 790930 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks.
|
||||
system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 144455339 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 144455345 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses
|
||||
|
|
@ -355,12 +355,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 10871281000
|
|||
system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses
|
||||
|
|
@ -572,21 +572,21 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838
|
|||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1620901 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 20018690 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.346447 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20016506 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8034928 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20016508 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20016508 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20016508 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20016508 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses
|
||||
|
|
@ -595,22 +595,22 @@ system.cpu.dcache.demand_misses::cpu.data 1623631 # n
|
|||
system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1623631 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313636000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18313636000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 27016353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 27016353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 27016353500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 27016353500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8350412 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21640137 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21640137 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21640137 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21640137 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8350414 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8350414 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21640139 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21640139 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21640139 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21640139 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses
|
||||
|
|
@ -619,14 +619,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.075029
|
|||
system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.698810 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.698810 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16639.466418 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16639.466418 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -645,14 +645,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1623631
|
|||
system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697346000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697346000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769091500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23769091500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769091500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23769091500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles
|
||||
|
|
@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
|
|
@ -736,20 +736,20 @@ system.cpu.l2cache.overall_misses::cpu.data 141963 #
|
|||
system.cpu.l2cache.overall_misses::total 154875 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599602500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2311578500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599594500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2311570500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723743500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5723743500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 711631000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7323346000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8035322000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7323338000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8035314000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 711631000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7323346000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8035322000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7323338000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8035314000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -789,20 +789,20 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.379348 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.311888 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 51882.576271 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 51882.576271 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -831,20 +831,20 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141963
|
|||
system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230976255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775429660 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249333352 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544173395 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480317607 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6024771012 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480309607 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6024763012 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544173395 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480309607 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6024763012 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles
|
||||
|
|
@ -869,20 +869,20 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43293.928006 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42941.822711 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
|
|
|
|||
Loading…
Reference in a new issue