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stats: update stats for ARMv8 changes

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This commit is contained in:
Ali Saidi 2014-01-24 15:29:34 -06:00
parent 612f8f074f
commit cfb805cc71
123 changed files with 22164 additions and 16696 deletions
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166
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -112,6 +122,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -130,6 +141,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -191,13 +203,14 @@ predType=tournament
[system.cpu.checker]
type=O3Checker
children=dtb isa itb tracer
children=dstage2_mmu dtb isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.checker.dstage2_mmu
dtb=system.cpu.checker.dtb
eventq_index=0
exitOnError=false
@ -205,6 +218,7 @@ function_trace=false
function_trace_start=0
interrupts=Null
isa=system.cpu.checker.isa
istage2_mmu=system.cpu.checker.istage2_mmu
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -221,10 +235,35 @@ updateOnError=true
warnOnlyOnLoadError=true
workload=
[system.cpu.checker.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
tlb=system.cpu.checker.dtb
[system.cpu.checker.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
[system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[9]
[system.cpu.checker.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.checker.dtb.walker
@ -232,32 +271,69 @@ walker=system.cpu.checker.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
port=system.cpu.toL2Bus.slave[7]
[system.cpu.checker.isa]
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.checker.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
tlb=system.cpu.checker.itb
[system.cpu.checker.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker
[system.cpu.checker.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[8]
[system.cpu.checker.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.checker.itb.walker
@ -265,9 +341,10 @@ walker=system.cpu.checker.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
port=system.cpu.toL2Bus.slave[6]
[system.cpu.checker.tracer]
type=ExeTracer
@ -308,10 +385,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -319,6 +421,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -673,24 +776,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -698,6 +837,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -746,7 +886,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

37
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
View file

@ -10,25 +10,20 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: 6165886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
warn: 6172734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
warn: 6181171500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 6216960500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 6232347500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: 6775306000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: 6176053500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
warn: 6184767500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 6220839500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 6236327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: 6779610500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
warn: 51869237500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: 2475417694000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
warn: 2489281853500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2490491047500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
warn: 2511643992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2512158375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2516381302500: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0
warn: 2516399186500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10
warn: 2517881609000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
warn: 2518389750000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
warn: 2518949430500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
warn: 2518950618000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
warn: 2519498238000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
warn: 51874115000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: 2476169247000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
warn: 2490093200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2491309014500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
warn: 2512521404000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2513043156000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2517323856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10
warn: 2518814467000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
warn: 2519896624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
warn: 2519897721500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
warn: 2520452967000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0

9
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,12 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:07:43
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:47:40
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
0: system.cpu.checker.isa: ISA system set to: 0x645a800 0x645a800
0: system.cpu.isa: ISA system set to: 0x645a800 0x645a800
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2525131633500 because m5_exit instruction encountered
Exiting @ tick 2526146947500 because m5_exit instruction encountered

3032
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

File diff suppressed because it is too large Load diff

170
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -112,6 +122,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
fetchBufferSize=64
@ -130,6 +141,7 @@ interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu0.istage2_mmu
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -224,10 +236,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.dtb.walker
@ -235,6 +272,7 @@ walker=system.cpu0.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -589,24 +627,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.itb.walker
@ -614,6 +688,7 @@ walker=system.cpu0.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -624,7 +699,7 @@ eventq_index=0
[system.cpu1]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -650,6 +725,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
fetchBufferSize=64
@ -668,6 +744,7 @@ interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -750,7 +827,7 @@ tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[5]
mem_side=system.toL2Bus.slave[7]
[system.cpu1.dcache.tags]
type=LRU
@ -762,10 +839,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[11]
[system.cpu1.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.dtb.walker
@ -773,9 +875,10 @@ walker=system.cpu1.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
port=system.toL2Bus.slave[9]
[system.cpu1.fuPool]
type=FUPool
@ -1107,7 +1210,7 @@ tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[4]
mem_side=system.toL2Bus.slave[6]
[system.cpu1.icache.tags]
type=LRU
@ -1127,24 +1230,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[10]
[system.cpu1.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.itb.walker
@ -1152,9 +1291,10 @@ walker=system.cpu1.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
port=system.toL2Bus.slave[8]
[system.cpu1.tracer]
type=ExeTracer
@ -1791,7 +1931,7 @@ system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
[system.vncserver]
type=VncServer

3
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
View file

@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented

9
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,12 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:17:38
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:56:34
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
0: system.cpu0.isa: ISA system set to: 0x6856800 0x6856800
0: system.cpu1.isa: ISA system set to: 0x6856800 0x6856800
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1104766159000 because m5_exit instruction encountered
Exiting @ tick 2605645191500 because m5_exit instruction encountered

4554
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

87
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -112,6 +122,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -130,6 +141,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -224,10 +236,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -235,6 +272,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -589,24 +627,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -614,6 +688,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -662,7 +737,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
View file

@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,12 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:04:18
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:42:01
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
0: system.cpu.isa: ISA system set to: 0x6dd8800 0x6dd8800
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2525131633500 because m5_exit instruction encountered
Exiting @ tick 2526146947500 because m5_exit instruction encountered

2962
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

233
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus ioca
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
fastmem=false
@ -100,6 +111,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
istage2_mmu=system.cpu0.istage2_mmu
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -157,10 +169,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.dtb.walker
@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -215,24 +253,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.itb.walker
@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -250,19 +325,21 @@ eventq_index=0
[system.cpu1]
type=TimingSimpleCPU
children=dtb isa itb tracer
children=dstage2_mmu dtb isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=Null
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -277,10 +354,34 @@ system=system
tracer=system.cpu1.tracer
workload=
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu1.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.dtb.walker
@ -288,6 +389,7 @@ walker=system.cpu1.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -295,24 +397,59 @@ sys=system
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu1.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.itb.walker
@ -320,6 +457,7 @@ walker=system.cpu1.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -329,7 +467,7 @@ eventq_index=0
[system.cpu2]
type=DerivO3CPU
children=branchPred dtb fuPool isa itb tracer
children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -355,6 +493,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu2.dstage2_mmu
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
@ -373,6 +512,7 @@ interrupts=Null
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu2.istage2_mmu
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -430,10 +570,34 @@ localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu2.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb
tlb=system.cpu2.dtb
[system.cpu2.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu2.dstage2_mmu.stage2_tlb.walker
[system.cpu2.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu2.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu2.dtb.walker
@ -441,6 +605,7 @@ walker=system.cpu2.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -755,24 +920,59 @@ opLat=3
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu2.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb
tlb=system.cpu2.itb
[system.cpu2.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu2.istage2_mmu.stage2_tlb.walker
[system.cpu2.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu2.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu2.itb.walker
@ -780,6 +980,7 @@ walker=system.cpu2.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -1418,7 +1619,7 @@ system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
[system.vncserver]
type=VncServer

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
View file

@ -11,8 +11,16 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

7
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
View file

@ -1,8 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:23:40
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 19:05:28
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400
0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400
0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400

3347
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
View file

File diff suppressed because it is too large Load diff

160
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -112,6 +122,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
fetchBufferSize=64
@ -130,6 +141,7 @@ interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu0.istage2_mmu
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -224,10 +236,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.dtb.walker
@ -235,6 +272,7 @@ walker=system.cpu0.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -589,24 +627,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.itb.walker
@ -614,6 +688,7 @@ walker=system.cpu0.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -624,7 +699,7 @@ eventq_index=0
[system.cpu1]
type=DerivO3CPU
children=branchPred dtb fuPool isa itb tracer
children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -650,6 +725,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
fetchBufferSize=64
@ -668,6 +744,7 @@ interrupts=Null
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -725,10 +802,34 @@ localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu1.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.dtb.walker
@ -736,6 +837,7 @@ walker=system.cpu1.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -1050,24 +1152,59 @@ opLat=3
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu1.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.itb.walker
@ -1075,6 +1212,7 @@ walker=system.cpu1.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -1713,7 +1851,7 @@ system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
[system.vncserver]
type=VncServer

20
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
View file

@ -11,7 +11,23 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
View file

@ -1,8 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:28:14
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 19:10:32
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
0: system.cpu0.isa: ISA system set to: 0x6aaf400 0x6aaf400
0: system.cpu1.isa: ISA system set to: 0x6aaf400 0x6aaf400

3779
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

160
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
istage2_mmu=system.cpu0.istage2_mmu
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -150,10 +162,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.dtb.walker
@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -208,24 +246,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.itb.walker
@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -243,19 +318,21 @@ eventq_index=0
[system.cpu1]
type=TimingSimpleCPU
children=dtb isa itb tracer
children=dstage2_mmu dtb isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=Null
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -270,10 +347,34 @@ system=system
tracer=system.cpu1.tracer
workload=
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu1.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.dtb.walker
@ -281,6 +382,7 @@ walker=system.cpu1.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -288,24 +390,59 @@ sys=system
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu1.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.itb.walker
@ -313,6 +450,7 @@ walker=system.cpu1.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
@ -951,7 +1089,7 @@ system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
[system.vncserver]
type=VncServer

38
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
View file

@ -11,8 +11,42 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
View file

@ -1,8 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:31:08
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 19:11:44
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu0.isa: ISA system set to: 0x6f57400 0x6f57400
0: system.cpu1.isa: ISA system set to: 0x6f57400 0x6f57400

2240
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

78
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -67,6 +68,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -179,10 +182,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -544,24 +573,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -569,6 +634,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -617,7 +683,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

7
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:37:28
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:10:45
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x50d0380
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
@ -23,4 +24,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 26911413000 because target called exit()
Exiting @ tick 26911921000 because target called exit()

1344
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

78
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -55,6 +57,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -77,10 +80,35 @@ workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@ -100,24 +129,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -125,6 +190,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@ -168,7 +234,7 @@ system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.physmem]
type=SimpleMemory

5
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:39:34
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:11:38
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x63b66c0
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I

54
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu
sim_ticks 54240661000 # Number of ticks simulated
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2327254 # Simulator instruction rate (inst/s)
host_op_rate 2343964 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1393249116 # Simulator tick rate (ticks/s)
host_mem_usage 371180 # Number of bytes of host memory used
host_seconds 38.93 # Real time elapsed on the host
host_inst_rate 2151308 # Simulator instruction rate (inst/s)
host_op_rate 2166754 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1287915883 # Simulator tick rate (ticks/s)
host_mem_usage 391064 # Number of bytes of host memory used
host_seconds 42.12 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated
sim_ops 91252960 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -39,6 +39,27 @@ system.membus.throughput 9960199711 # Th
system.membus.data_through_bus 540247816 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -93,7 +135,7 @@ system.cpu.num_func_calls 112245 # nu
system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525674 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read
system.cpu.num_int_register_reads 396967282 # number of times the integer registers were read
system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written

78
tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

5
tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:40:24
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:12:31
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5565040
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I

54
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
sim_ticks 147135976000 # Number of ticks simulated
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1334589 # Simulator instruction rate (inst/s)
host_op_rate 1344158 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2167949307 # Simulator tick rate (ticks/s)
host_mem_usage 379884 # Number of bytes of host memory used
host_seconds 67.87 # Real time elapsed on the host
host_inst_rate 1098833 # Simulator instruction rate (inst/s)
host_op_rate 1106711 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1784978875 # Simulator tick rate (ticks/s)
host_mem_usage 400800 # Number of bytes of host memory used
host_seconds 82.43 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La
system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -99,7 +141,7 @@ system.cpu.num_func_calls 112245 # nu
system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525674 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read
system.cpu.num_int_register_reads 464618159 # number of times the integer registers were read
system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written

78
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -67,6 +68,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -179,10 +182,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -544,24 +573,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -569,6 +634,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -617,7 +683,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

7
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:41:42
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:14:04
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x4cfd380
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@ -67,4 +68,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 202741893000 because target called exit()
Exiting @ tick 202696649500 because target called exit()

1553
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

78
tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -55,6 +57,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -77,10 +80,35 @@ workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@ -100,24 +129,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -125,6 +190,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@ -168,7 +234,7 @@ system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.physmem]
type=SimpleMemory

5
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:44:24
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:19:30
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5d016c0
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************

54
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu
sim_ticks 290498967000 # Number of ticks simulated
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2346027 # Simulator instruction rate (inst/s)
host_op_rate 2644207 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1345327991 # Simulator tick rate (ticks/s)
host_mem_usage 241300 # Number of bytes of host memory used
host_seconds 215.93 # Real time elapsed on the host
host_inst_rate 2103217 # Simulator instruction rate (inst/s)
host_op_rate 2370536 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1206088561 # Simulator tick rate (ticks/s)
host_mem_usage 262216 # Number of bytes of host memory used
host_seconds 240.86 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated
sim_ops 570968167 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -39,6 +39,27 @@ system.membus.throughput 9312824252 # Th
system.membus.data_through_bus 2705365825 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -93,7 +135,7 @@ system.cpu.num_func_calls 19311615 # nu
system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727695 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read
system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read
system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written

78
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

5
tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:45:59
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:21:27
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x6322040
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************

54
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu
sim_ticks 717366012000 # Number of ticks simulated
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1243497 # Simulator instruction rate (inst/s)
host_op_rate 1401211 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1766466230 # Simulator tick rate (ticks/s)
host_mem_usage 251064 # Number of bytes of host memory used
host_seconds 406.10 # Real time elapsed on the host
host_inst_rate 1131056 # Simulator instruction rate (inst/s)
host_op_rate 1274509 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1606737202 # Simulator tick rate (ticks/s)
host_mem_usage 271980 # Number of bytes of host memory used
host_seconds 446.47 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated
sim_ops 569034839 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.1 # La
system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -107,7 +149,7 @@ system.cpu.num_func_calls 19311615 # nu
system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727695 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read
system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read
system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written

78
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -67,6 +68,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -179,10 +182,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -544,24 +573,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -569,6 +634,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -617,7 +683,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

7
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:48:11
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:23:42
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x4718040
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
@ -13,4 +14,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.060000
Exiting @ tick 68509635500 because target called exit()
Exiting @ tick 68503867000 because target called exit()

1323
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

78
tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -55,6 +57,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -77,10 +80,35 @@ workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@ -100,24 +129,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -125,6 +190,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@ -168,7 +234,7 @@ system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.physmem]
type=SimpleMemory

5
tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:52:31
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:27:26
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x56d96c0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1

54
tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu
sim_ticks 212344043000 # Number of ticks simulated
final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1679583 # Simulator instruction rate (inst/s)
host_op_rate 2147266 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1306228104 # Simulator tick rate (ticks/s)
host_mem_usage 246496 # Number of bytes of host memory used
host_seconds 162.56 # Real time elapsed on the host
host_inst_rate 1312619 # Simulator instruction rate (inst/s)
host_op_rate 1678120 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1020836459 # Simulator tick rate (ticks/s)
host_mem_usage 266392 # Number of bytes of host memory used
host_seconds 208.01 # Real time elapsed on the host
sim_insts 273037663 # Number of instructions simulated
sim_ops 349065399 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -39,6 +39,27 @@ system.membus.throughput 10715621794 # Th
system.membus.data_through_bus 2275398455 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -93,7 +135,7 @@ system.cpu.num_func_calls 12448615 # nu
system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584918 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read
system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read
system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written

78
tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

5
tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:52:55
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:29:04
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x4c37d00
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1

54
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu
sim_ticks 525834342000 # Number of ticks simulated
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 870200 # Simulator instruction rate (inst/s)
host_op_rate 1112519 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1677723175 # Simulator tick rate (ticks/s)
host_mem_usage 255236 # Number of bytes of host memory used
host_seconds 313.42 # Real time elapsed on the host
host_inst_rate 719381 # Simulator instruction rate (inst/s)
host_op_rate 919702 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1386947293 # Simulator tick rate (ticks/s)
host_mem_usage 276148 # Number of bytes of host memory used
host_seconds 379.13 # Real time elapsed on the host
sim_insts 272739283 # Number of instructions simulated
sim_ops 348687122 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La
system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -99,7 +141,7 @@ system.cpu.num_func_calls 12448615 # nu
system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584917 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read
system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read
system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written

78
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -67,6 +68,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -179,10 +182,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -544,24 +573,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -569,6 +634,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -617,7 +683,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

5
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:55:24
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:31:04
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x4c3a340
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.

382
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.629535 # Nu
sim_ticks 629535413500 # Number of ticks simulated
final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 111054 # Simulator instruction rate (inst/s)
host_op_rate 151240 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 50501117 # Simulator tick rate (ticks/s)
host_mem_usage 257896 # Number of bytes of host memory used
host_seconds 12465.77 # Real time elapsed on the host
host_inst_rate 106173 # Simulator instruction rate (inst/s)
host_op_rate 144593 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48281629 # Simulator tick rate (ticks/s)
host_mem_usage 278772 # Number of bytes of host memory used
host_seconds 13038.82 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -264,14 +264,14 @@ system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # By
system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation
system.physmem.totQLat 3804882250 # Total ticks spent queuing
system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 3804806750 # Total ticks spent queuing
system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers
system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks
system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst
system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s
@ -303,20 +303,41 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 34627840 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 438247561 # Number of BP lookups
system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted
system.cpu.branchPred.lookups 438247722 # Number of BP lookups
system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups
system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits
system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups
system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage
system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -338,6 +359,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -363,94 +405,94 @@ system.cpu.workload.num_syscalls 1411 # Nu
system.cpu.numCycles 1259070828 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed
system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked
system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed
system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch
system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode
system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename
system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups
system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer
system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued
system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
@ -486,7 +528,7 @@ system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued
@ -519,17 +561,17 @@ system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Ty
system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued
system.cpu.iq.rate 1.934087 # Inst issue rate
system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued
system.cpu.iq.rate 1.934086 # Inst issue rate
system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
@ -540,13 +582,13 @@ system.cpu.iew.lsq.thread0.squashedStores 208692629 # N
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions
@ -556,43 +598,43 @@ system.cpu.iew.memOrderViolationEvents 1430281 # Nu
system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 12446 # number of nop insts executed
system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed
system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed
system.cpu.iew.exec_branches 319532182 # Number of branches executed
system.cpu.iew.exec_stores 423276586 # Number of stores executed
system.cpu.iew.exec_rate 1.874346 # Inst execution rate
system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1349155886 # num instructions producing a value
system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value
system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1349155649 # num instructions producing a value
system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle
system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -605,10 +647,10 @@ system.cpu.commit.int_insts 1653698867 # Nu
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3791959297 # The number of ROB reads
system.cpu.rob.rob_writes 5711929091 # The number of ROB writes
system.cpu.rob.rob_reads 3791959363 # The number of ROB reads
system.cpu.rob.rob_writes 5711929117 # The number of ROB writes
system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
@ -616,11 +658,11 @@ system.cpu.cpi 0.909490 # CP
system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads
system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads
system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes
system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads
system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes
system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads
system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes
system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads
system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution
@ -743,7 +785,7 @@ system.cpu.l2cache.tags.total_refs 1110777 # To
system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy
@ -788,16 +830,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2426 #
system.cpu.l2cache.overall_misses::cpu.data 472563 # number of overall misses
system.cpu.l2cache.overall_misses::total 474989 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746506500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 30922725250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4757394750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 35503901250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 35680120000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 35503901250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 35680120000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1464549 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses)
@ -827,16 +869,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970
system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -870,18 +912,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424
system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses
@ -896,24 +938,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 1532970 # number of replacements
system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy
@ -925,20 +967,20 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 977
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits
system.cpu.dcache.overall_hits::total 971375738 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits
system.cpu.dcache.overall_hits::total 971375795 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses
@ -949,28 +991,28 @@ system.cpu.dcache.demand_misses::cpu.data 2796744 # n
system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses
system.cpu.dcache.overall_misses::total 2796744 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses
@ -981,16 +1023,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002871
system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
@ -1019,14 +1061,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1541332
system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
@ -1035,14 +1077,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582
system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

78
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -55,6 +57,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -77,10 +80,35 @@ workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@ -100,24 +129,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -125,6 +190,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@ -168,7 +234,7 @@ system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.physmem]
type=SimpleMemory

5
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 22:58:19
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:35:34
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x49db380
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.

54
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu
sim_ticks 945613126000 # Number of ticks simulated
final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1817390 # Simulator instruction rate (inst/s)
host_op_rate 2475033 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1241382789 # Simulator tick rate (ticks/s)
host_mem_usage 247108 # Number of bytes of host memory used
host_seconds 761.74 # Real time elapsed on the host
host_inst_rate 1603190 # Simulator instruction rate (inst/s)
host_op_rate 2183323 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1095071931 # Simulator tick rate (ticks/s)
host_mem_usage 266996 # Number of bytes of host memory used
host_seconds 863.52 # Real time elapsed on the host
sim_insts 1384381606 # Number of instructions simulated
sim_ops 1885336358 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -39,6 +39,27 @@ system.membus.throughput 9675679644 # Th
system.membus.data_through_bus 9149449674 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -93,7 +135,7 @@ system.cpu.num_func_calls 80372855 # nu
system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698868 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 8601515912 # number of times the integer registers were read
system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read
system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written

78
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

5
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:11:12
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:50:08
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x56b7d00
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.

54
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 968971 # Simulator instruction rate (inst/s)
host_op_rate 1314478 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1631393565 # Simulator tick rate (ticks/s)
host_mem_usage 255816 # Number of bytes of host memory used
host_seconds 1425.85 # Real time elapsed on the host
host_inst_rate 908275 # Simulator instruction rate (inst/s)
host_op_rate 1232140 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1529204664 # Simulator tick rate (ticks/s)
host_mem_usage 276728 # Number of bytes of host memory used
host_seconds 1521.13 # Real time elapsed on the host
sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.0 # La
system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -107,7 +149,7 @@ system.cpu.num_func_calls 80372855 # nu
system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698868 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read
system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read
system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written

78
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -67,6 +68,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -179,10 +182,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -544,24 +573,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -569,6 +634,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -617,7 +683,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

1
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
View file

@ -1 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4]

7
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:17:11
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:54:40
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5a6c340
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 26810051000 because target called exit()
Exiting @ tick 26790388000 because target called exit()

1739
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

78
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -55,6 +57,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -77,10 +80,35 @@ workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@ -100,24 +129,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -125,6 +190,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@ -168,7 +234,7 @@ system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.physmem]
type=SimpleMemory

5
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:25:48
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:03:38
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x49b6380
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 53932157000 because target called exit()

54
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu
sim_ticks 53932157000 # Number of ticks simulated
final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1940189 # Simulator instruction rate (inst/s)
host_op_rate 2753308 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1475586020 # Simulator tick rate (ticks/s)
host_mem_usage 245844 # Number of bytes of host memory used
host_seconds 36.55 # Real time elapsed on the host
host_inst_rate 1720542 # Simulator instruction rate (inst/s)
host_op_rate 2441608 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1308536096 # Simulator tick rate (ticks/s)
host_mem_usage 265732 # Number of bytes of host memory used
host_seconds 41.22 # Real time elapsed on the host
sim_insts 70913181 # Number of instructions simulated
sim_ops 100632428 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -39,6 +39,27 @@ system.membus.throughput 9230371187 # Th
system.membus.data_through_bus 497813828 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -93,7 +135,7 @@ system.cpu.num_func_calls 3311620 # nu
system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls
system.cpu.num_int_insts 91472780 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 452177195 # number of times the integer registers were read
system.cpu.num_int_register_reads 452305352 # number of times the integer registers were read
system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written

78
tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

5
tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:26:35
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:04:30
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5604d00
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 132689045000 because target called exit()

54
tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu
sim_ticks 132689045000 # Number of ticks simulated
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1019812 # Simulator instruction rate (inst/s)
host_op_rate 1446120 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1922848599 # Simulator tick rate (ticks/s)
host_mem_usage 254584 # Number of bytes of host memory used
host_seconds 69.01 # Real time elapsed on the host
host_inst_rate 945773 # Simulator instruction rate (inst/s)
host_op_rate 1341131 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1783248877 # Simulator tick rate (ticks/s)
host_mem_usage 275500 # Number of bytes of host memory used
host_seconds 74.41 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 99791654 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.7 # La
system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -107,7 +149,7 @@ system.cpu.num_func_calls 3311620 # nu
system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls
system.cpu.num_int_insts 91472780 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read
system.cpu.num_int_register_reads 533671029 # number of times the integer registers were read
system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written

78
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -67,6 +68,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -179,10 +182,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -544,24 +573,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -569,6 +634,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -617,7 +683,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

7
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:27:54
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:05:55
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5017340
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
@ -24,4 +25,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 533797009000 because target called exit()
Exiting @ tick 533761922000 because target called exit()

1641
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

78
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -55,6 +57,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -77,10 +80,35 @@ workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@ -100,24 +129,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -125,6 +190,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@ -168,7 +234,7 @@ system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.physmem]
type=SimpleMemory

5
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:35:09
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:13:20
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x571a380
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data

54
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu
sim_ticks 861538200000 # Number of ticks simulated
final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2414882 # Simulator instruction rate (inst/s)
host_op_rate 2693979 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1346991470 # Simulator tick rate (ticks/s)
host_mem_usage 238968 # Number of bytes of host memory used
host_seconds 639.60 # Real time elapsed on the host
host_inst_rate 2200753 # Simulator instruction rate (inst/s)
host_op_rate 2455102 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1227552560 # Simulator tick rate (ticks/s)
host_mem_usage 258852 # Number of bytes of host memory used
host_seconds 701.83 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated
sim_ops 1723073853 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -39,6 +39,27 @@ system.membus.throughput 9731209155 # Th
system.membus.data_through_bus 8383808419 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -93,7 +135,7 @@ system.cpu.num_func_calls 27330256 # nu
system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941842 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read
system.cpu.num_int_register_reads 7861285293 # number of times the integer registers were read
system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written

78
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

5
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:38:44
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:15:41
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5333d00
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data

54
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu
sim_ticks 2391205115000 # Number of ticks simulated
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1202285 # Simulator instruction rate (inst/s)
host_op_rate 1341761 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1868329144 # Simulator tick rate (ticks/s)
host_mem_usage 247832 # Number of bytes of host memory used
host_seconds 1279.86 # Real time elapsed on the host
host_inst_rate 1176543 # Simulator instruction rate (inst/s)
host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1828326739 # Simulator tick rate (ticks/s)
host_mem_usage 268744 # Number of bytes of host memory used
host_seconds 1307.87 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.5 # La
system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -107,7 +149,7 @@ system.cpu.num_func_calls 27330256 # nu
system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941842 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read
system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read
system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written

78
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
@ -67,6 +68,7 @@ dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -179,10 +182,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -544,24 +573,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -569,6 +634,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -617,7 +683,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

9
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
View file

@ -1,13 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 23:45:59
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:25:13
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5949040
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
@ -23,4 +22,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 74219948500 because target called exit()
122 123 124 Exiting @ tick 74219931000 because target called exit()

762
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

78
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -55,6 +57,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -77,10 +80,35 @@ workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@ -100,24 +129,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -125,6 +190,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@ -168,7 +234,7 @@ system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.physmem]
type=SimpleMemory

7
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
View file

@ -1,13 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:00:14
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:37:39
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5fbc6c0
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988

54
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu
sim_ticks 103106766000 # Number of ticks simulated
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2018881 # Simulator instruction rate (inst/s)
host_op_rate 2210479 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1208004529 # Simulator tick rate (ticks/s)
host_mem_usage 241364 # Number of bytes of host memory used
host_seconds 85.35 # Real time elapsed on the host
host_inst_rate 1878588 # Simulator instruction rate (inst/s)
host_op_rate 2056872 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1124059947 # Simulator tick rate (ticks/s)
host_mem_usage 262308 # Number of bytes of host memory used
host_seconds 91.73 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated
sim_ops 188670891 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -39,6 +39,27 @@ system.membus.throughput 8876496088 # Th
system.membus.data_through_bus 915226805 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -93,7 +135,7 @@ system.cpu.num_func_calls 3545028 # nu
system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106218 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read
system.cpu.num_int_register_reads 815315678 # number of times the integer registers were read
system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written

78
tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
View file

@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

7
tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
View file

@ -1,13 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 23 2014 00:01:50
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 18:39:21
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5d0ed00
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988

54
tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu
sim_ticks 232072304000 # Number of ticks simulated
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1248624 # Simulator instruction rate (inst/s)
host_op_rate 1367377 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1686259354 # Simulator tick rate (ticks/s)
host_mem_usage 250108 # Number of bytes of host memory used
host_seconds 137.63 # Real time elapsed on the host
host_inst_rate 1152638 # Simulator instruction rate (inst/s)
host_op_rate 1262262 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1556630640 # Simulator tick rate (ticks/s)
host_mem_usage 271024 # Number of bytes of host memory used
host_seconds 149.09 # Real time elapsed on the host
sim_insts 171842483 # Number of instructions simulated
sim_ops 188185920 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La
system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -99,7 +141,7 @@ system.cpu.num_func_calls 3545028 # nu
system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106218 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read
system.cpu.num_int_register_reads 904571312 # number of times the integer registers were read
system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written

170
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
fastmem=false
@ -100,6 +111,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
istage2_mmu=system.cpu0.istage2_mmu
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -157,10 +169,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.dtb.walker
@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -215,24 +253,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.itb.walker
@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -250,13 +325,14 @@ eventq_index=0
[system.cpu1]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
fastmem=false
@ -264,6 +340,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -309,7 +386,7 @@ tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[5]
mem_side=system.toL2Bus.slave[7]
[system.cpu1.dcache.tags]
type=LRU
@ -321,10 +398,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[11]
[system.cpu1.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.dtb.walker
@ -332,9 +434,10 @@ walker=system.cpu1.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
port=system.toL2Bus.slave[9]
[system.cpu1.icache]
type=BaseCache
@ -359,7 +462,7 @@ tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[4]
mem_side=system.toL2Bus.slave[6]
[system.cpu1.icache.tags]
type=LRU
@ -379,24 +482,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[10]
[system.cpu1.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.itb.walker
@ -404,9 +543,10 @@ walker=system.cpu1.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
port=system.toL2Bus.slave[8]
[system.cpu1.tracer]
type=ExeTracer
@ -1019,7 +1159,7 @@ system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
[system.vncserver]
type=VncServer

3
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
View file

@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented

9
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
View file

@ -1,12 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 17:30:53
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:07:33
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
0: system.cpu0.isa: ISA system set to: 0x6a97800 0x6a97800
0: system.cpu1.isa: ISA system set to: 0x6a97800 0x6a97800
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 912096763500 because m5_exit instruction encountered
Exiting @ tick 912096767500 because m5_exit instruction encountered

576
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
View file

@ -1,30 +1,30 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.912097 # Number of seconds simulated
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 912096767500 # Number of ticks simulated
final_tick 912096767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1859152 # Simulator instruction rate (inst/s)
host_op_rate 2393654 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27516397451 # Simulator tick rate (ticks/s)
host_mem_usage 399324 # Number of bytes of host memory used
host_seconds 33.15 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
host_inst_rate 1391627 # Simulator instruction rate (inst/s)
host_op_rate 1791703 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20594093924 # Simulator tick rate (ticks/s)
host_mem_usage 421260 # Number of bytes of host memory used
host_seconds 44.29 # Real time elapsed on the host
sim_insts 61634065 # Number of instructions simulated
sim_ops 79353129 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6235196 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory
system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3364536 # Number of bytes read from this memory
system.physmem.bytes_read::total 49638596 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
@ -32,12 +32,12 @@ system.physmem.bytes_written::total 7222864 # Nu
system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 97499 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 52599 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5082824 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
@ -45,29 +45,29 @@ system.physmem.num_writes::total 822331 # Nu
system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 550621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 6836112 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 235278 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3688793 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 54422511 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 550621 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 235278 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 785899 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4600143 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::writebacks 4600143 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 550621 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 6854751 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 235278 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988978 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341477 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
@ -86,24 +86,24 @@ system.realview.nvmem.bw_inst_read::total 75 # I
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 64986577 # Throughput (bytes/s)
system.membus.data_through_bus 59274047 # Total data (bytes)
system.membus.throughput 64986682 # Throughput (bytes/s)
system.membus.data_through_bus 59274143 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 70658 # number of replacements
system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use
system.l2c.tags.tagsinuse 51560.149479 # Cycle average of tags in use
system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::writebacks 39278.694836 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4358.955623 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2482.444990 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2126.451280 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3310.922652 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
@ -124,8 +124,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 12549 #
system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 16906854 # Number of tag accesses
system.l2c.tags.data_accesses 16906854 # Number of data accesses
system.l2c.tags.tag_accesses 16908094 # Number of tag accesses
system.l2c.tags.data_accesses 16908094 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
@ -172,9 +172,9 @@ system.l2c.ReadReq_misses::cpu1.dtb.walker 3 #
system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses
system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
@ -208,9 +208,9 @@ system.l2c.ReadReq_accesses::cpu1.data 174787 # nu
system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses)
@ -243,9 +243,9 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562
system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
@ -285,33 +285,75 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 154009014 # Throughput (bytes/s)
system.toL2Bus.data_through_bus 140471123 # Total data (bytes)
system.toL2Bus.throughput 154019994 # Throughput (bytes/s)
system.toL2Bus.data_through_bus 140481139 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iobus.throughput 45730949 # Throughput (bytes/s)
system.iobus.data_through_bus 41711051 # Total data (bytes)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7975768 # DTB read hits
system.cpu0.dtb.read_hits 7977216 # DTB read hits
system.cpu0.dtb.read_misses 3611 # DTB read misses
system.cpu0.dtb.write_hits 5966574 # DTB write hits
system.cpu0.dtb.write_hits 5966960 # DTB write hits
system.cpu0.dtb.write_misses 672 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7979379 # DTB read accesses
system.cpu0.dtb.write_accesses 5967246 # DTB write accesses
system.cpu0.dtb.read_accesses 7980827 # DTB read accesses
system.cpu0.dtb.write_accesses 5967632 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 13942342 # DTB hits
system.cpu0.dtb.hits 13944176 # DTB hits
system.cpu0.dtb.misses 4283 # DTB misses
system.cpu0.dtb.accesses 13946625 # DTB accesses
system.cpu0.itb.inst_hits 30238804 # ITB inst hits
system.cpu0.dtb.accesses 13948459 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 30245736 # ITB inst hits
system.cpu0.itb.inst_misses 2175 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@ -321,80 +363,80 @@ system.cpu0.itb.flush_tlb 4 # Nu
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB
system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses
system.cpu0.itb.hits 30238804 # DTB hits
system.cpu0.itb.inst_accesses 30247911 # ITB inst accesses
system.cpu0.itb.hits 30245736 # DTB hits
system.cpu0.itb.misses 2175 # DTB misses
system.cpu0.itb.accesses 30240979 # DTB accesses
system.cpu0.numCycles 1823671407 # number of cpu cycles simulated
system.cpu0.itb.accesses 30247911 # DTB accesses
system.cpu0.numCycles 1823671415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 29750005 # Number of instructions committed
system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses
system.cpu0.committedInsts 29756754 # Number of instructions committed
system.cpu0.committedOps 39137733 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34752271 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
system.cpu0.num_func_calls 1241903 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34471201 # number of integer instructions
system.cpu0.num_func_calls 1242676 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4045310 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34752271 # number of integer instructions
system.cpu0.num_fp_insts 5449 # number of float instructions
system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written
system.cpu0.num_int_register_reads 179899233 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36833612 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
system.cpu0.num_mem_refs 14626951 # number of memory refs
system.cpu0.num_load_insts 8357226 # Number of load instructions
system.cpu0.num_store_insts 6269725 # Number of store instructions
system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles
system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles
system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
system.cpu0.num_mem_refs 14629077 # number of memory refs
system.cpu0.num_load_insts 8358676 # Number of load instructions
system.cpu0.num_store_insts 6270401 # Number of store instructions
system.cpu0.num_idle_cycles 1783997907.577739 # Number of idle cycles
system.cpu0.num_busy_cycles 39673507.422261 # Number of busy cycles
system.cpu0.not_idle_fraction 0.021755 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.978245 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed
system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 428546 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks.
system.cpu0.icache.tags.tagsinuse 511.015213 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 29818047 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor
system.cpu0.icache.tags.avg_refs 69.496541 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 64537144000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015213 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 30669233 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 30669233 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits
system.cpu0.icache.overall_hits::total 29811115 # number of overall hits
system.cpu0.icache.tags.tag_accesses 30676165 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 30676165 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 29818047 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29818047 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29818047 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 29818047 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29818047 # number of overall hits
system.cpu0.icache.overall_hits::total 29818047 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses
system.cpu0.icache.overall_misses::total 429059 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30247106 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 30247106 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30247106 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 30247106 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30247106 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 30247106 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014185 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014185 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014185 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014185 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014185 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014185 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -405,67 +447,67 @@ system.cpu0.icache.fast_writes 0 # nu
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 323609 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks.
system.cpu0.dcache.tags.tagsinuse 494.763093 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 12469292 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor
system.cpu0.dcache.tags.avg_refs 38.487726 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763093 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 51675155 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51675155 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits
system.cpu0.dcache.tags.tag_accesses 51682637 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51682637 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6513463 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6513463 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5631258 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5631258 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits
system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits
system.cpu0.dcache.demand_hits::cpu0.data 12144721 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12144721 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12144721 # number of overall hits
system.cpu0.dcache.overall_hits::total 12144721 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 167351 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 167351 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses
system.cpu0.dcache.overall_misses::total 364509 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.demand_misses::cpu0.data 364518 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 364518 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 364518 # number of overall misses
system.cpu0.dcache.overall_misses::total 364518 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6710630 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6710630 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798609 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5798609 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses
system.cpu0.dcache.demand_accesses::cpu0.data 12509239 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12509239 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12509239 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12509239 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029381 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.029381 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029140 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.029140 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029140 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029140 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -477,28 +519,70 @@ system.cpu0.dcache.cache_copies 0 # nu
system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks
system.cpu0.dcache.writebacks::total 300958 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 7364781 # DTB read hits
system.cpu1.dtb.read_hits 7365100 # DTB read hits
system.cpu1.dtb.read_misses 3705 # DTB read misses
system.cpu1.dtb.write_hits 5489656 # DTB write hits
system.cpu1.dtb.write_hits 5489754 # DTB write hits
system.cpu1.dtb.write_misses 1595 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB
system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7368486 # DTB read accesses
system.cpu1.dtb.write_accesses 5491251 # DTB write accesses
system.cpu1.dtb.read_accesses 7368805 # DTB read accesses
system.cpu1.dtb.write_accesses 5491349 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 12854437 # DTB hits
system.cpu1.dtb.hits 12854854 # DTB hits
system.cpu1.dtb.misses 5300 # DTB misses
system.cpu1.dtb.accesses 12859737 # DTB accesses
system.cpu1.itb.inst_hits 32412306 # ITB inst hits
system.cpu1.dtb.accesses 12860154 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 32413691 # ITB inst hits
system.cpu1.itb.inst_misses 2200 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
@ -508,48 +592,48 @@ system.cpu1.itb.flush_tlb 4 # Nu
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB
system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses
system.cpu1.itb.hits 32412306 # DTB hits
system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses
system.cpu1.itb.hits 32413691 # DTB hits
system.cpu1.itb.misses 2200 # DTB misses
system.cpu1.itb.accesses 32414506 # DTB accesses
system.cpu1.numCycles 1824193528 # number of cpu cycles simulated
system.cpu1.itb.accesses 32415891 # DTB accesses
system.cpu1.numCycles 1824193536 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 31875965 # Number of instructions committed
system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses
system.cpu1.committedInsts 31877311 # Number of instructions committed
system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
system.cpu1.num_func_calls 955227 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls
system.cpu1.num_int_insts 35797832 # number of integer instructions
system.cpu1.num_func_calls 955425 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls
system.cpu1.num_int_insts 35862250 # number of integer instructions
system.cpu1.num_fp_insts 4436 # number of float instructions
system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read
system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written
system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read
system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
system.cpu1.num_mem_refs 13370713 # number of memory refs
system.cpu1.num_load_insts 7642673 # Number of load instructions
system.cpu1.num_store_insts 5728040 # Number of store instructions
system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles
system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles
system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles
system.cpu1.num_mem_refs 13371151 # number of memory refs
system.cpu1.num_load_insts 7642991 # Number of load instructions
system.cpu1.num_store_insts 5728160 # Number of store instructions
system.cpu1.num_idle_cycles 1783399616.755682 # Number of idle cycles
system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles
system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed
system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed
system.cpu1.icache.tags.replacements 433942 # number of replacements
system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks.
system.cpu1.icache.tags.tagsinuse 475.447911 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor
system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 69967761000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447911 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
@ -558,26 +642,26 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::1 63
system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 32848033 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 32848033 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits
system.cpu1.icache.overall_hits::total 31979125 # number of overall hits
system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits
system.cpu1.icache.overall_hits::total 31980510 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses
system.cpu1.icache.overall_misses::total 434454 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses
@ -595,10 +679,10 @@ system.cpu1.icache.cache_copies 0 # nu
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 294289 # number of replacements
system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks.
system.cpu1.dcache.tags.total_refs 11708150 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.avg_refs 39.715435 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 67293491000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy
@ -608,56 +692,56 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 48417680 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 48417680 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits
system.cpu1.dcache.tags.tag_accesses 48419345 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 48419345 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 7002503 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 7002503 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4520265 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4520265 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits
system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits
system.cpu1.dcache.demand_hits::cpu1.data 11522768 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11522768 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 11522768 # number of overall hits
system.cpu1.dcache.overall_hits::total 11522768 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 126066 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 126066 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses
system.cpu1.dcache.overall_misses::total 324195 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.demand_misses::cpu1.data 324341 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 324341 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 324341 # number of overall misses
system.cpu1.dcache.overall_misses::total 324341 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027132 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.027132 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked

87
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
@ -100,6 +111,7 @@ function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -157,10 +169,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
@ -168,6 +205,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@ -215,24 +253,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
@ -240,6 +314,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@ -288,7 +363,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer

2
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
View file

@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
View file

@ -1,12 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 17:30:43
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:06:34
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
0: system.cpu.isa: ISA system set to: 0x55f5800 0x55f5800
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2332810264000 because m5_exit instruction encountered
Exiting @ tick 2332810269000 because m5_exit instruction encountered

158
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
View file

@ -1,46 +1,46 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.332810 # Number of seconds simulated
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2332810269000 # Number of ticks simulated
final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1656319 # Simulator instruction rate (inst/s)
host_op_rate 2129924 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 63962280307 # Simulator tick rate (ticks/s)
host_mem_usage 398176 # Number of bytes of host memory used
host_seconds 36.47 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
host_inst_rate 1274625 # Simulator instruction rate (inst/s)
host_op_rate 1639090 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49222371545 # Simulator tick rate (ticks/s)
host_mem_usage 420236 # Number of bytes of host memory used
host_seconds 47.39 # Real time elapsed on the host
sim_insts 60408649 # Number of instructions simulated
sim_ops 77681829 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
@ -48,9 +48,9 @@ system.physmem.bw_total::writebacks 1587455 # To
system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
@ -63,8 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 55969585 # Throughput (bytes/s)
system.membus.data_through_bus 130566422 # Total data (bytes)
system.membus.throughput 55969605 # Throughput (bytes/s)
system.membus.data_through_bus 130566470 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -75,9 +75,30 @@ system.cf0.dma_write_txs 0 # Nu
system.iobus.throughput 48895252 # Throughput (bytes/s)
system.iobus.data_through_bus 114063346 # Total data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14971214 # DTB read hits
system.cpu.dtb.read_hits 14971217 # DTB read hits
system.cpu.dtb.read_misses 7294 # DTB read misses
system.cpu.dtb.write_hits 11217004 # DTB write hits
system.cpu.dtb.write_misses 2181 # DTB write misses
@ -85,17 +106,38 @@ system.cpu.dtb.flush_tlb 2 # Nu
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 14978508 # DTB read accesses
system.cpu.dtb.read_accesses 14978511 # DTB read accesses
system.cpu.dtb.write_accesses 11219185 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26188218 # DTB hits
system.cpu.dtb.hits 26188221 # DTB hits
system.cpu.dtb.misses 9475 # DTB misses
system.cpu.dtb.accesses 26197693 # DTB accesses
system.cpu.dtb.accesses 26197696 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 61431840 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@ -106,7 +148,7 @@ system.cpu.itb.flush_tlb 2 # Nu
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -117,37 +159,37 @@ system.cpu.itb.inst_accesses 61436311 # IT
system.cpu.itb.hits 61431840 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61436311 # DTB accesses
system.cpu.numCycles 4665620529 # number of cpu cycles simulated
system.cpu.numCycles 4665620539 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60408639 # Number of instructions committed
system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses
system.cpu.committedInsts 60408649 # Number of instructions committed
system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2136008 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls
system.cpu.num_int_insts 68795605 # number of integer instructions
system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls
system.cpu.num_int_insts 69130761 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read
system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written
system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read
system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27361637 # number of memory refs
system.cpu.num_load_insts 15639527 # Number of load instructions
system.cpu.num_mem_refs 27361639 # number of memory refs
system.cpu.num_load_insts 15639529 # Number of load instructions
system.cpu.num_store_insts 11722110 # Number of store instructions
system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles
system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles
system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles
system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles
system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
system.cpu.icache.tags.replacements 850590 # number of replacements
system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor
system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
@ -192,16 +234,16 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 62243 # number of replacements
system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
@ -312,12 +354,12 @@ system.cpu.l2cache.writebacks::writebacks 57863 # n
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 623337 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use
system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
@ -382,8 +424,8 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
system.cpu.dcache.writebacks::total 592643 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes)
system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use

170
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
View file

@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l
atags_addr=256
boot_loader=/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=
@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=268435504
gic_cpu_addr=520093952
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
@ -33,7 +41,9 @@ multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
istage2_mmu=system.cpu0.istage2_mmu
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -150,10 +162,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.dtb.walker
@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -208,24 +246,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.itb.walker
@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -243,19 +318,21 @@ eventq_index=0
[system.cpu1]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -295,7 +372,7 @@ tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[5]
mem_side=system.toL2Bus.slave[7]
[system.cpu1.dcache.tags]
type=LRU
@ -307,10 +384,35 @@ hit_latency=2
sequential_access=false
size=32768
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[11]
[system.cpu1.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.dtb.walker
@ -318,9 +420,10 @@ walker=system.cpu1.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
port=system.toL2Bus.slave[9]
[system.cpu1.icache]
type=BaseCache
@ -345,7 +448,7 @@ tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[4]
mem_side=system.toL2Bus.slave[6]
[system.cpu1.icache.tags]
type=LRU
@ -365,24 +468,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_mmfr3=34611729
id_pfr0=49
id_pfr1=1
midr=890224640
id_pfr1=4113
midr=1091551472
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[10]
[system.cpu1.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.itb.walker
@ -390,9 +529,10 @@ walker=system.cpu1.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
port=system.toL2Bus.slave[8]
[system.cpu1.tracer]
type=ExeTracer
@ -1029,7 +1169,7 @@ system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
[system.vncserver]
type=VncServer

3
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
View file

@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented

9
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
View file

@ -1,12 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:24:06
gem5 started Jan 22 2014 17:31:37
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:08:43
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
0: system.cpu0.isa: ISA system set to: 0x6319800 0x6319800
0: system.cpu1.isa: ISA system set to: 0x6319800 0x6319800
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1196134388000 because m5_exit instruction encountered
Exiting @ tick 1196139241000 because m5_exit instruction encountered

3016
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View file

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