stats: Bump stats for the fixes, and mostly DRAM controller changes
This commit is contained in:
Andreas Hansson
parent
aa329f4757
commit
57e5401d95
127 changed files with 41636 additions and 36617 deletions
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@ -4,11 +4,11 @@ sim_seconds 5.304497 # Nu
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sim_ticks 5304496750000 # Number of ticks simulated
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final_tick 5304496750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 156851 # Simulator instruction rate (inst/s)
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host_op_rate 300747 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7785889362 # Simulator tick rate (ticks/s)
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host_mem_usage 816820 # Number of bytes of host memory used
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host_seconds 681.30 # Real time elapsed on the host
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host_inst_rate 145026 # Simulator instruction rate (inst/s)
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host_op_rate 278074 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7198918941 # Simulator tick rate (ticks/s)
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host_mem_usage 818088 # Number of bytes of host memory used
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host_seconds 736.85 # Real time elapsed on the host
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sim_insts 106862058 # Number of instructions simulated
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sim_ops 204897478 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -234,9 +234,7 @@ system.physmem.wrQLenPdf::63 0 # Wh
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system.physmem.totQLat 0 # Total ticks spent queuing
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system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 0 # Total ticks spent in databus transfers
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system.physmem.totBankLat 0 # Total ticks spent accessing banks
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system.physmem.avgQLat nan # Average queueing delay per DRAM burst
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system.physmem.avgBankLat nan # Average bank access latency per DRAM burst
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system.physmem.avgBusLat nan # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s
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@ -255,137 +253,11 @@ system.physmem.readRowHitRate nan # Ro
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap nan # Average gap between requests
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system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state
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system.iobus.throughput 383259 # Throughput (bytes/s)
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system.iobus.trans_dist::ReadReq 858443 # Transaction distribution
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system.iobus.trans_dist::ReadResp 858443 # Transaction distribution
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system.iobus.trans_dist::WriteReq 37726 # Transaction distribution
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system.iobus.trans_dist::WriteResp 37726 # Transaction distribution
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system.iobus.trans_dist::MessageReq 1924 # Transaction distribution
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system.iobus.trans_dist::MessageResp 1924 # Transaction distribution
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system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 242 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703384 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5244 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89454 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::total 1796186 # Packet count per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 484 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972069 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10485 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54229 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::total 2032994 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.data_through_bus 2032994 # Total data (bytes)
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system.iobus.reqLayer0.occupancy 45000 # Layer occupancy (ticks)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks)
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system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer2.occupancy 10111500 # Layer occupancy (ticks)
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system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks)
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system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer4.occupancy 1076000 # Layer occupancy (ticks)
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system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer5.occupancy 95000 # Layer occupancy (ticks)
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system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks)
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system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks)
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system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks)
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system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer9.occupancy 1240500 # Layer occupancy (ticks)
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system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer10.occupancy 41494500 # Layer occupancy (ticks)
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system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks)
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system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer12.occupancy 23487000 # Layer occupancy (ticks)
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system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
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system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
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system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
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system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
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system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer17.occupancy 469626032 # Layer occupancy (ticks)
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system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer18.occupancy 7795368 # Layer occupancy (ticks)
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system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks)
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system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer0.occupancy 2413900 # Layer occupancy (ticks)
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system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer2.occupancy 1790216000 # Layer occupancy (ticks)
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system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer4.occupancy 80190500 # Layer occupancy (ticks)
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system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
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system.physmem.memoryStateTime::IDLE 5127363440000 # Time in different power states
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system.physmem.memoryStateTime::REF 177128640000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 0 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.ruby.clk_domain.clock 500 # Clock period in ticks
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system.ruby.delayHist::bucket_size 2 # delay histogram for all message
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system.ruby.delayHist::max_bucket 19 # delay histogram for all message
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@ -590,6 +462,136 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
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system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
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system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
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system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
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system.iobus.throughput 383259 # Throughput (bytes/s)
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system.iobus.trans_dist::ReadReq 858443 # Transaction distribution
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system.iobus.trans_dist::ReadResp 858443 # Transaction distribution
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system.iobus.trans_dist::WriteReq 37726 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 37726 # Transaction distribution
|
||||
system.iobus.trans_dist::MessageReq 1924 # Transaction distribution
|
||||
system.iobus.trans_dist::MessageResp 1924 # Transaction distribution
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 242 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703384 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5244 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89454 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 1796186 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 484 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972069 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54229 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 2032994 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 2032994 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 45000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer2.occupancy 10111500 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer4.occupancy 1076000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer5.occupancy 95000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer9.occupancy 1240500 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer10.occupancy 41494500 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer12.occupancy 23487000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer17.occupancy 469626032 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer18.occupancy 7795368 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks)
|
||||
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer0.occupancy 2413900 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer2.occupancy 1790216000 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.iobus.respLayer4.occupancy 80190500 # Layer occupancy (ticks)
|
||||
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu0.numCycles 10608993500 # number of cpu cycles simulated
|
||||
|
|
@ -617,6 +619,41 @@ system.cpu0.num_busy_cycles 526834059.049901
|
|||
system.cpu0.not_idle_fraction 0.049659 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.950341 # Percentage of idle cycles
|
||||
system.cpu0.Branches 11678784 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 146088 0.13% 0.13% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 102315691 88.54% 88.66% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 88423 0.08% 88.74% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 60803 0.05% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCmp 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCvt 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatMult 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatDiv 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatSqrt 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAdd 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAddAcc 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAlu 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCmp 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCvt 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMisc 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMult 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMultAcc 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShift 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShiftAcc 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdSqrt 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAdd 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAlu 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCmp 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCvt 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatDiv 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMisc 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 88.79% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 7847946 6.79% 95.58% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 5106253 4.42% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 115565204 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
|
|
@ -645,6 +682,41 @@ system.cpu1.num_busy_cycles 320373991.077311
|
|||
system.cpu1.not_idle_fraction 0.030207 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.969793 # Percentage of idle cycles
|
||||
system.cpu1.Branches 10261767 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 160875 0.18% 0.18% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 75501866 84.52% 84.70% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 96299 0.11% 84.80% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 67676 0.08% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.88% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 8734970 9.78% 94.66% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 4772103 5.34% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 89333789 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.ruby.network.routers0.throttle0.link_utilization 0.041639
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu
|
|||
sim_ticks 54240661000 # Number of ticks simulated
|
||||
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2151308 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2166754 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1287915883 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 391064 # Number of bytes of host memory used
|
||||
host_seconds 42.12 # Real time elapsed on the host
|
||||
host_inst_rate 1753346 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1765935 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1049669772 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 433744 # Number of bytes of host memory used
|
||||
host_seconds 51.67 # Real time elapsed on the host
|
||||
sim_insts 90602407 # Number of instructions simulated
|
||||
sim_ops 91252960 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 108481323 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 18732304 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91253402 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
|
|||
sim_ticks 147135976000 # Number of ticks simulated
|
||||
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1098833 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1106711 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1784978875 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 400800 # Number of bytes of host memory used
|
||||
host_seconds 82.43 # Real time elapsed on the host
|
||||
host_inst_rate 805246 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 811020 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1308067541 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 443480 # Number of bytes of host memory used
|
||||
host_seconds 112.48 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91226312 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -153,6 +153,41 @@ system.cpu.num_busy_cycles 294271952 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 18732304 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91253402 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 2 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu
|
|||
sim_ticks 122215823500 # Number of ticks simulated
|
||||
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3086610 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3086737 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1547143112 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 361240 # Number of bytes of host memory used
|
||||
host_seconds 78.99 # Real time elapsed on the host
|
||||
host_inst_rate 2362566 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2362664 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1184221154 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 397240 # Number of bytes of host memory used
|
||||
host_seconds 103.20 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -65,5 +65,40 @@ system.cpu.num_busy_cycles 244431648 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 29302884 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 244431613 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu
|
|||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1454320 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1454380 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2156135283 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 371132 # Number of bytes of host memory used
|
||||
host_seconds 167.66 # Real time elapsed on the host
|
||||
host_inst_rate 1070091 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1586487053 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 406976 # Number of bytes of host memory used
|
||||
host_seconds 227.85 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -69,6 +69,41 @@ system.cpu.num_busy_cycles 722977060 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 29302884 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 244431613 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
|
|||
sim_ticks 168950040000 # Number of ticks simulated
|
||||
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1603557 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2823605 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1714813271 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 379092 # Number of bytes of host memory used
|
||||
host_seconds 98.52 # Real time elapsed on the host
|
||||
host_inst_rate 1054637 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1857047 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1127809594 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 414920 # Number of bytes of host memory used
|
||||
host_seconds 149.80 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 337900081 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 29309705 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 278192465 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
|
|||
sim_ticks 365989065000 # Number of ticks simulated
|
||||
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 696180 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1225861 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1612738645 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388852 # Number of bytes of host memory used
|
||||
host_seconds 226.94 # Real time elapsed on the host
|
||||
host_inst_rate 596728 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1382352440 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 424660 # Number of bytes of host memory used
|
||||
host_seconds 264.76 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -82,6 +82,41 @@ system.cpu.num_busy_cycles 731978130 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 29309705 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 278192465 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu
|
|||
sim_ticks 290498967000 # Number of ticks simulated
|
||||
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2103217 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2370536 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1206088561 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262216 # Number of bytes of host memory used
|
||||
host_seconds 240.86 # Real time elapsed on the host
|
||||
host_inst_rate 1775828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2001536 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1018347697 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304924 # Number of bytes of host memory used
|
||||
host_seconds 285.27 # Real time elapsed on the host
|
||||
sim_insts 506581607 # Number of instructions simulated
|
||||
sim_ops 570968167 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 580997935 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 121548301 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 570968717 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu
|
|||
sim_ticks 717366012000 # Number of ticks simulated
|
||||
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1131056 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1274509 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1606737202 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271980 # Number of bytes of host memory used
|
||||
host_seconds 446.47 # Real time elapsed on the host
|
||||
host_inst_rate 879063 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 990556 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1248765490 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313636 # Number of bytes of host memory used
|
||||
host_seconds 574.46 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -161,6 +161,41 @@ system.cpu.num_busy_cycles 1434732024 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 121548301 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 570968717 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu
|
|||
sim_ticks 885229328000 # Number of ticks simulated
|
||||
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1633857 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3021184 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1749156833 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252248 # Number of bytes of host memory used
|
||||
host_seconds 506.09 # Real time elapsed on the host
|
||||
host_inst_rate 1112999 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2058060 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1191542406 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288080 # Number of bytes of host memory used
|
||||
host_seconds 742.93 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 1770458657 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 149758583 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1528988702 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
|
|||
sim_ticks 1647872849000 # Number of ticks simulated
|
||||
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 782951 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1447764 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1560332529 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260992 # Number of bytes of host memory used
|
||||
host_seconds 1056.10 # Real time elapsed on the host
|
||||
host_inst_rate 654522 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1210285 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1304389188 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297832 # Number of bytes of host memory used
|
||||
host_seconds 1263.33 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -82,6 +82,41 @@ system.cpu.num_busy_cycles 3295745698 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 149758583 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1528988702 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.139926 # Number of seconds simulated
|
||||
sim_ticks 139926186500 # Number of ticks simulated
|
||||
final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.139925 # Number of seconds simulated
|
||||
sim_ticks 139925460500 # Number of ticks simulated
|
||||
final_tick 139925460500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 124689 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 124689 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43764124 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271420 # Number of bytes of host memory used
|
||||
host_seconds 3197.28 # Real time elapsed on the host
|
||||
host_inst_rate 120046 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 120046 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42134532 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271408 # Number of bytes of host memory used
|
||||
host_seconds 3320.92 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1536353 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1815357 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3351710 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1536353 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1536353 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1536353 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1815357 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3351710 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1536361 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1815367 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3351727 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1536361 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1536361 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1536361 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1815367 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3351727 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7328 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 139926113000 # Total gap between requests
|
||||
system.physmem.totGap 139925387000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 4589 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1831 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 611 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4503 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1916 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 242 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 558 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 480.917563 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 280.270360 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 415.877438 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 147 26.34% 26.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 107 19.18% 45.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 50 8.96% 54.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 28 5.02% 59.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 15 2.69% 62.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 15 2.69% 64.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 7 1.25% 66.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 5 0.90% 67.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 184 32.97% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 558 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 59527000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 199924500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1345 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 345.790335 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 209.990258 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 340.082178 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 408 30.33% 30.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 331 24.61% 54.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 167 12.42% 67.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 84 6.25% 73.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 65 4.83% 78.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 45 3.35% 81.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 30 2.23% 84.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 29 2.16% 86.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 186 13.83% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1345 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 64590750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 201990750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 103757500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 8123.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 14159.05 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgQLat 8814.24 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27282.27 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27564.24 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -218,14 +216,18 @@ system.physmem.busUtilRead 0.03 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 5962 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 5972 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 81.50 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 19094720.66 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.43 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 3351710 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 19094621.59 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.50 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 133853003250 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 4672200000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1393983000 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 3351727 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
|
||||
|
|
@ -236,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 468992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 8819000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 68133000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 68224500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 53489673 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 53489674 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 32882350 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 94754639 # DTB read hits
|
||||
system.cpu.dtb.read_hits 94754638 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 94754660 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521131 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 94754659 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73521127 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73521166 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275770 # DTB hits
|
||||
system.cpu.dtb.write_accesses 73521162 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168275765 # DTB hits
|
||||
system.cpu.dtb.data_misses 56 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168275826 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611322 # ITB hits
|
||||
system.cpu.dtb.data_accesses 168275821 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 48611320 # ITB hits
|
||||
system.cpu.itb.fetch_misses 44520 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 48655842 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 48655840 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -283,18 +285,18 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 279852374 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 279850922 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386572 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedNotTaken 24259169 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722431 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 100484576 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 100484573 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -305,12 +307,12 @@ system.cpu.execution_unit.executions 205475782 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 279400810 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 279400656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7266 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13545705 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306669 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.159696 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7212 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13544259 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 266306663 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.160188 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -322,81 +324,81 @@ system.cpu.committedInsts 398664595 # Nu
|
|||
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.701974 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.701971 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.701974 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.424553 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.701971 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.424561 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.424553 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107200637 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651737 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.693862 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 181107747 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744627 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.284541 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90384400 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467974 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.702829 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.424561 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78103252 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 201747670 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.091122 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 107199191 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 172651731 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.694180 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 102635700 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177215222 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.324866 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 181106302 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98744620 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 35.284722 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 90382943 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189467979 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.703182 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 1975 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1830.934233 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 48606787 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1830.939956 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 48606789 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12453.698950 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12453.699462 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.934233 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894011 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894011 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939956 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894014 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894014 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 97226547 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 97226547 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606787 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606787 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606787 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606787 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606787 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606787 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4535 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4535 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4535 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4535 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4535 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4535 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 279787250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 279787250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 279787250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 279787250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 279787250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 279787250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611322 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611322 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611322 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611322 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 97226543 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 97226543 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 48606789 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 48606789 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 48606789 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 48606789 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 48606789 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 48606789 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4531 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 279235250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 279235250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 279235250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 279235250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 279235250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 279235250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 48611320 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 48611320 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 48611320 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 48611320 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 48611320 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 48611320 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61695.093716 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61627.731185 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61627.731185 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61627.731185 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61627.731185 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61627.731185 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61627.731185 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -405,38 +407,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 632 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 632 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 632 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 632 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 628 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 628 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243851250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243851250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243851250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243851250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243851250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243851250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62477.901614 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62477.901614 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62477.901614 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 62477.901614 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62477.901614 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 62477.901614 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 3981091 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
|
|
@ -452,26 +454,26 @@ system.cpu.toL2Bus.data_through_bus 557056 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6445500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6455750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6649999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6676249 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3906.832917 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 3906.848534 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 370.533355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.730052 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.569510 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 370.535307 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.741321 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571906 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088767 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.119228 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 564 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.143951 # Percentage of cache occupancy per task id
|
||||
|
|
@ -501,17 +503,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234486500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61133000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 295619500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 230289500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 230289500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 234486500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 291422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 525909000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 234486500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 291422500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 525909000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234462250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 60397500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 294859750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231906750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 231906750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 234462250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 292304250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 526766500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 234462250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 292304250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 526766500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -536,17 +538,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69801.205716 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73297.936893 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70490.019125 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73738.235294 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73738.235294 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69801.205716 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.825397 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71884.074782 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69801.205716 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.825397 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71884.074782 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -566,17 +568,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192420000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50867000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 243287000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191492500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191492500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192420000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 242359500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 434779500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192420000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 242359500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 434779500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192372250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50131500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 242503750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193005250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193005250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192372250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 243136750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 435509000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192372250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 243136750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 435509000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -588,27 +590,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57270.690682 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60839.199029 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57973.643318 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61368.918919 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61368.918919 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57270.690682 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61258.944318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59430.813319 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57270.690682 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61258.944318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59430.813319 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3284.879976 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3284.892778 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168254239 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40523.660645 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.879976 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.801973 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.801973 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.892778 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.801976 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.801976 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
|
||||
|
|
@ -618,30 +620,30 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3109
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 336554588 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753183 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753183 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73501056 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73501056 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168254239 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168254239 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168254239 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168254239 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1306 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1306 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19673 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 19673 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20979 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20979 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 20979 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 20979 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 87087749 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 87087749 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1166784250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1166784250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1253871999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1253871999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1253871999 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1253871999 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 86414249 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 86414249 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1153377000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1153377000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1239791249 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1239791249 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1239791249 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1239791249 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -658,28 +660,28 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59767.958387 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 33117 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66167.112557 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66167.112557 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58627.408123 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 58627.408123 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59096.775299 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59096.775299 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59096.775299 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59096.775299 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 33700 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 591 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 588 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.035533 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.312925 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16469 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16469 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 356 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 356 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16471 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 16471 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 16827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 16827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 16827 # number of overall MSHR hits
|
||||
|
|
@ -692,14 +694,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63587751 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 63587751 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 234030250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 234030250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 297618001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 297618001 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 297618001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 297618001 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 62852251 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 62852251 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235649500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 235649500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298501751 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 298501751 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298501751 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 298501751 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -708,14 +710,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66160.264211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66160.264211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73594.472205 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73594.472205 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71893.485308 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71893.485308 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71893.485308 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71893.485308 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu
|
|||
sim_ticks 199332411500 # Number of ticks simulated
|
||||
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3310187 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3310187 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1655094150 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226700 # Number of bytes of host memory used
|
||||
host_seconds 120.44 # Real time elapsed on the host
|
||||
host_inst_rate 2589605 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2589605 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1294803220 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262692 # Number of bytes of host memory used
|
||||
host_seconds 153.95 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 398664824 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587532 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 145805196 36.57% 42.37% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 398664651 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
|
|||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1478735 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1478735 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2104370306 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 235572 # Number of bytes of host memory used
|
||||
host_seconds 269.60 # Real time elapsed on the host
|
||||
host_inst_rate 1080224 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1080224 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1537254294 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271408 # Number of bytes of host memory used
|
||||
host_seconds 369.06 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 1134670186 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587535 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 145805208 36.57% 42.37% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 94754511 23.77% 81.56% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 398664665 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu
|
|||
sim_ticks 212344043000 # Number of ticks simulated
|
||||
final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1312619 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1678120 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1020836459 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266392 # Number of bytes of host memory used
|
||||
host_seconds 208.01 # Real time elapsed on the host
|
||||
host_inst_rate 1152169 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1472992 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 896053064 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309060 # Number of bytes of host memory used
|
||||
host_seconds 236.98 # Real time elapsed on the host
|
||||
sim_insts 273037663 # Number of instructions simulated
|
||||
sim_ops 349065399 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 424688087 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563502 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 116649415 33.42% 33.42% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 349065594 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu
|
|||
sim_ticks 525834342000 # Number of ticks simulated
|
||||
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 485432 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 620607 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 935900071 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332908 # Number of bytes of host memory used
|
||||
host_seconds 561.85 # Real time elapsed on the host
|
||||
host_inst_rate 605985 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 774729 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1168322503 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318808 # Number of bytes of host memory used
|
||||
host_seconds 450.08 # Real time elapsed on the host
|
||||
sim_insts 272739283 # Number of instructions simulated
|
||||
sim_ops 348687122 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -153,6 +153,41 @@ system.cpu.num_busy_cycles 1051668684 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563501 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 349065592 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 1.004711 # Nu
|
|||
sim_ticks 1004710587000 # Number of ticks simulated
|
||||
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1945820 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1945820 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 973120006 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280320 # Number of bytes of host memory used
|
||||
host_seconds 1032.46 # Real time elapsed on the host
|
||||
host_inst_rate 2670371 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2670371 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1335473702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265688 # Number of bytes of host memory used
|
||||
host_seconds 752.33 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 2009421175 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 266706457 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2009421070 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.769740 # Nu
|
|||
sim_ticks 2769739533000 # Number of ticks simulated
|
||||
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1066482 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1066482 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1470331870 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289152 # Number of bytes of host memory used
|
||||
host_seconds 1883.75 # Real time elapsed on the host
|
||||
host_inst_rate 1094265 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1094265 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1508635104 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274392 # Number of bytes of host memory used
|
||||
host_seconds 1835.92 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -109,6 +109,41 @@ system.cpu.num_busy_cycles 5539479066 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 266706457 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2009421070 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 9046 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu
|
|||
sim_ticks 945613126000 # Number of ticks simulated
|
||||
final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1077492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1467395 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 735989505 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323780 # Number of bytes of host memory used
|
||||
host_seconds 1284.82 # Real time elapsed on the host
|
||||
host_inst_rate 1407956 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1917442 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 961716087 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309672 # Number of bytes of host memory used
|
||||
host_seconds 983.26 # Real time elapsed on the host
|
||||
sim_insts 1384381606 # Number of instructions simulated
|
||||
sim_ops 1885336358 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 1891226253 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 298259106 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1885337770 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu
|
|||
sim_ticks 2326118592000 # Number of ticks simulated
|
||||
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 546207 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 740969 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 919614125 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332488 # Number of bytes of host memory used
|
||||
host_seconds 2529.45 # Real time elapsed on the host
|
||||
host_inst_rate 706219 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 958037 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1189016431 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318376 # Number of bytes of host memory used
|
||||
host_seconds 1956.34 # Real time elapsed on the host
|
||||
sim_insts 1381604339 # Number of instructions simulated
|
||||
sim_ops 1874244941 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -161,6 +161,41 @@ system.cpu.num_busy_cycles 4652237184 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 298259106 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1885337770 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 18364 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.043459 # Number of seconds simulated
|
||||
sim_ticks 43458818000 # Number of ticks simulated
|
||||
final_tick 43458818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.043473 # Number of seconds simulated
|
||||
sim_ticks 43472869000 # Number of ticks simulated
|
||||
final_tick 43472869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 114678 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 114678 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56415550 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273516 # Number of bytes of host memory used
|
||||
host_seconds 770.33 # Real time elapsed on the host
|
||||
host_inst_rate 112027 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 112027 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55129043 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274568 # Number of bytes of host memory used
|
||||
host_seconds 788.57 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,31 +25,31 @@ system.physmem.num_reads::cpu.data 158412 # Nu
|
|||
system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10460294 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 233286787 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 243747080 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10460294 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10460294 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 167878657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 167878657 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 167878657 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10460294 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 233286787 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 411625737 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 10456913 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 233211385 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 243668298 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10456913 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10456913 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 167824396 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 167824396 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 167824396 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10456913 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 233211385 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 411492694 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165515 # Number of read requests accepted
|
||||
system.physmem.writeReqs 113997 # Number of write requests accepted
|
||||
system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 10592576 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 7294400 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadDRAM 10592320 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 7293824 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 10379 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 10437 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 10436 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 10256 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 10015 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 10350 # Per bank write bursts
|
||||
|
|
@ -58,9 +58,9 @@ system.physmem.perBankRdBursts::6 9796 # Pe
|
|||
system.physmem.perBankRdBursts::7 10273 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 10509 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 10590 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 10477 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 10475 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 10188 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 10236 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 10235 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 10580 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 10468 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 10593 # Per bank write bursts
|
||||
|
|
@ -71,18 +71,18 @@ system.physmem.perBankWrBursts::3 6998 # Pe
|
|||
system.physmem.perBankWrBursts::4 7125 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 7170 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 6769 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 7092 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 7216 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 7083 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 7217 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 6938 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 7083 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 7081 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 6989 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 6963 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 7284 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 7281 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 7282 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 43458797000 # Total gap between requests
|
||||
system.physmem.totGap 43472848000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 113997 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 69517 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 66164 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 19662 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 10165 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 70302 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 51581 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 34122 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 9498 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 866 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 1934 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 2737 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4571 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 5772 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 6159 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 6456 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 6714 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 7156 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 7301 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 7672 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 8033 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 8104 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 8481 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 8313 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 5342 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 3822 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 910 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 567 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 333 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 82 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 69 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 48 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 47 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 38 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 37 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 29 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 954 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 2155 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 2833 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4913 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 6026 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 6448 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 6697 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 6974 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 7338 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 7765 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 8182 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 8823 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 9350 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 8420 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 8642 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 8524 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 8027 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 402 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 219 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 140 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
|
|
@ -193,83 +193,71 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 41807 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 385.014950 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 230.118388 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 358.708548 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12628 30.21% 30.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8632 20.65% 50.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4415 10.56% 61.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2749 6.58% 67.99% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2263 5.41% 73.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1680 4.02% 77.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1442 3.45% 80.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1629 3.90% 84.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6369 15.23% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 41807 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 6909 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 23.954842 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 351.043824 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 6907 99.97% 99.97% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.bytesPerActivate::samples 52007 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 343.898321 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 202.122220 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 343.471226 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 18183 34.96% 34.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 10752 20.67% 55.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5531 10.64% 66.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3167 6.09% 72.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2729 5.25% 77.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1801 3.46% 81.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1676 3.22% 84.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1325 2.55% 86.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6843 13.16% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 52007 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 6952 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 23.806818 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 349.983272 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 6951 99.99% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 6909 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 6909 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.496599 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.404036 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 2.150839 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 6289 91.03% 91.03% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 13 0.19% 91.21% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 61 0.88% 92.10% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 166 2.40% 94.50% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 127 1.84% 96.34% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 73 1.06% 97.39% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 63 0.91% 98.31% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 29 0.42% 98.73% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::24 18 0.26% 98.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::25 12 0.17% 99.16% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::26 7 0.10% 99.26% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::27 3 0.04% 99.31% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::28 3 0.04% 99.35% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::29 1 0.01% 99.36% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::30 2 0.03% 99.39% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::31 3 0.04% 99.44% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::32 2 0.03% 99.46% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::34 3 0.04% 99.51% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::35 2 0.03% 99.54% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::37 3 0.04% 99.58% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::39 19 0.28% 99.88% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::40 5 0.07% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::42 2 0.03% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 6909 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 5306478250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7800537000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 827545000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 1666513750 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 32061.57 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 10069.02 # Average bank access latency per DRAM burst
|
||||
system.physmem.rdPerTurnAround::total 6952 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 6951 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.395339 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.363988 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 1.079809 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 5950 85.60% 85.60% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 35 0.50% 86.10% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 555 7.98% 94.09% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 213 3.06% 97.15% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 101 1.45% 98.60% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 56 0.81% 99.41% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 23 0.33% 99.74% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 12 0.17% 99.91% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::24 2 0.03% 99.94% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::25 2 0.03% 99.97% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 6951 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 4829573500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7932792250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 827525000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 29180.83 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 47130.59 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 243.74 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 167.85 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 243.75 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 167.88 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 47930.83 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 243.65 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 167.78 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 243.67 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 167.82 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 3.22 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 3.21 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 1.90 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 1.31 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 144461 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 82889 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.28 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 72.71 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 155480.97 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 10.25 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 411625737 # Throughput (bytes/s)
|
||||
system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 145183 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 82273 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 72.17 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 155531.24 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 26086323250 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1451580000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 15933004250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 411492694 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 34625 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 34625 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 113997 # Transaction distribution
|
||||
|
|
@ -281,40 +269,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17888768 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1219845000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1219071000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1520840750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1523545750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 18742760 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 12318400 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 18742718 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 12318358 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 15507492 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 15507357 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 4664025 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 30.075947 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 30.076208 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20277780 # DTB read hits
|
||||
system.cpu.dtb.read_hits 20277728 # DTB read hits
|
||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20367928 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14729056 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 20367876 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14728971 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14736308 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006836 # DTB hits
|
||||
system.cpu.dtb.write_accesses 14736223 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006699 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35104236 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12367757 # ITB hits
|
||||
system.cpu.dtb.data_accesses 35104099 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12367762 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11021 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 12378778 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 12378783 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -328,34 +316,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 86917637 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 86945739 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 8074236 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10668524 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74162131 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedNotTaken 10668482 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74162124 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126481381 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126481374 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14174243 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 14174248 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35060070 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44777932 # Number of Instructions Executed.
|
||||
system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 77191042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 77212885 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 229429 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 17341864 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69575773 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 80.047934 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 241035 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 17370075 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69575664 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 80.021936 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 20276638 # Number of Load instructions committed
|
||||
system.cpu.comStores 14613377 # Number of Store instructions committed
|
||||
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
||||
|
|
@ -367,120 +355,120 @@ system.cpu.committedInsts 88340673 # Nu
|
|||
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.983891 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.984210 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.983891 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.016372 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.984210 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.016044 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.016372 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 34262012 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 52655625 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.581059 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 44462439 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42455198 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 48.845320 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 43887105 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43030532 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.507250 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 64797015 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22120622 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.450096 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 40875399 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46042238 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 52.972262 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.016044 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 34290146 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 52655593 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 60.561442 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 44490597 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42455142 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 48.829468 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 43915285 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43030454 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 49.491159 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 64825125 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22120614 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.441861 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 40903528 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46042211 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 52.955109 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 84371 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1905.831723 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 12250503 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1906.099937 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 12250492 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 141.760337 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 141.760209 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1905.831723 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.930582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.930582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1906.099937 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.930713 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.930713 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 24821911 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 24821911 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12250503 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12250503 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12250503 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12250503 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12250503 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12250503 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 117244 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 117244 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 117244 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 117244 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117244 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117244 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1999895234 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1999895234 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1999895234 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1999895234 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1999895234 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1999895234 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12367747 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12367747 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12367747 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009480 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 17057.548651 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 17057.548651 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 343 # number of cycles access was blocked
|
||||
system.cpu.icache.tags.tag_accesses 24821923 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 24821923 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12250492 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12250492 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12250492 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12250492 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12250492 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12250492 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 117261 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 117261 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 117261 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 117261 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117261 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117261 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1989588981 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1989588981 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1989588981 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1989588981 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1989588981 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1989588981 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12367753 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12367753 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12367753 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12367753 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12367753 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12367753 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009481 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009481 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009481 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009481 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009481 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009481 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16967.184153 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16967.184153 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16967.184153 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16967.184153 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 22.866667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.133333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30827 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30827 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30827 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30827 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30844 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30844 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30844 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30844 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30844 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30844 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1419611513 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1419611513 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1419611513 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1419611513 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1419611513 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1419611513 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1409598264 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1409598264 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1409598264 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1409598264 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1409598264 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1409598264 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16311.585267 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16311.585267 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 676121104 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 675902573 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution
|
||||
|
|
@ -496,28 +484,28 @@ system.cpu.toL2Bus.data_through_bus 29383424 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 130829487 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 130854736 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 323146469 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 326587968 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 131591 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30877.243576 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 30879.620467 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.905024 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1776.684074 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.826802 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061276 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.054220 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.942299 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27087.517417 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.809532 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1783.293518 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.826645 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061304 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.054422 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.942371 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17173 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13478 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17062 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13579 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3980348 # Number of tag accesses
|
||||
|
|
@ -546,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 165515 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165515 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 537407000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1972226500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2509633500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12899781250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12899781250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 537407000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 14872007750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15409414750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 537407000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 14872007750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15409414750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 527407000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2000529000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2527936000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12857601250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12857601250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 527407000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 14858130250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15385537250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 527407000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 14858130250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15385537250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -581,17 +569,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.569242 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74251.302267 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72688.358404 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73008.981949 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98232.112843 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98232.112843 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 92955.546325 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 92955.546325 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -613,17 +601,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165515
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 448296500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1624855000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2073151500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11301062250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11301062250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448296500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12925917250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 13374213750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448296500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12925917250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 13374213750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 438280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1653149000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2091429000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11252735250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11252735250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12905884250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 13344164250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12905884250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 13344164250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -635,58 +623,58 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61703.505561 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60066.455926 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60402.281588 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85970.931698 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85970.931698 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 200251 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.081511 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 33755026 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4076.191917 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 33755204 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 165.184838 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 302612000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.081511 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995137 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995137 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 165.185709 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 301118000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.191917 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995164 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995164 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 922 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3108 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3099 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 69984377 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 69984377 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180293 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180293 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574733 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574733 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33755026 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33755026 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33755026 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33755026 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96345 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96345 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038644 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038644 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1134989 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1134989 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1134989 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1134989 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4945314984 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4945314984 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 82211352380 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 82211352380 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 87156667364 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 87156667364 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 87156667364 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 87156667364 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180307 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180307 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574897 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574897 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33755204 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33755204 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33755204 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33755204 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96331 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96331 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038480 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038480 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1134811 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1134811 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1134811 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1134811 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5018382484 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5018382484 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 82442485122 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 82442485122 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 87460867606 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 87460867606 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 87460867606 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 87460867606 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -695,40 +683,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 #
|
|||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032530 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032530 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032530 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032530 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 76790.759526 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 76790.759526 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5467849 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071064 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.071064 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032525 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032525 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032525 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032525 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52095.197641 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 52095.197641 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79387.648411 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 79387.648411 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 77070.866960 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 77070.866960 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5473044 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116872 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.784936 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.883943 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168352 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35578 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35578 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895064 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 895064 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930642 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930642 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930642 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930642 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35564 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35564 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 894900 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 894900 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930464 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930464 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930464 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930464 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
||||
|
|
@ -737,14 +725,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347
|
|||
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2366861266 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2366861266 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13170287765 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13170287765 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15537149031 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 15537149031 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15537149031 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 15537149031 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395231766 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395231766 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13128048266 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13128048266 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15523280032 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 15523280032 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15523280032 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 15523280032 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -753,14 +741,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39416.653216 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39416.653216 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91433.683424 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91433.683424 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu
|
|||
sim_ticks 44221003000 # Number of ticks simulated
|
||||
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1834941 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1834940 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 918522034 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 279452 # Number of bytes of host memory used
|
||||
host_seconds 48.14 # Real time elapsed on the host
|
||||
host_inst_rate 2624099 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2624098 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1313553455 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264796 # Number of bytes of host memory used
|
||||
host_seconds 33.67 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 88442007 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13754477 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 88438073 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu
|
|||
sim_ticks 133634727000 # Number of ticks simulated
|
||||
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 990858 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 990858 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1498890062 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288280 # Number of bytes of host memory used
|
||||
host_seconds 89.16 # Real time elapsed on the host
|
||||
host_inst_rate 1051168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1051168 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1590122468 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273520 # Number of bytes of host memory used
|
||||
host_seconds 84.04 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -109,6 +109,41 @@ system.cpu.num_busy_cycles 267269454 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13754477 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 88438073 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu
|
|||
sim_ticks 53932157000 # Number of ticks simulated
|
||||
final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1050888 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1491308 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 799239680 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 322556 # Number of bytes of host memory used
|
||||
host_seconds 67.48 # Real time elapsed on the host
|
||||
host_inst_rate 1371353 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1946078 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1042965622 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308436 # Number of bytes of host memory used
|
||||
host_seconds 51.71 # Real time elapsed on the host
|
||||
sim_insts 70913181 # Number of instructions simulated
|
||||
sim_ops 100632428 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 107864315 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13741485 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 100634375 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu
|
|||
sim_ticks 132689045000 # Number of ticks simulated
|
||||
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 552138 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 782946 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1041052140 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332284 # Number of bytes of host memory used
|
||||
host_seconds 127.46 # Real time elapsed on the host
|
||||
host_inst_rate 682193 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 967367 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1286269606 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318200 # Number of bytes of host memory used
|
||||
host_seconds 103.16 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 99791654 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -161,6 +161,41 @@ system.cpu.num_busy_cycles 265378090 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13741485 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 100634375 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu
|
|||
sim_ticks 68148672000 # Number of ticks simulated
|
||||
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1921737 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1946620 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 974440461 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287756 # Number of bytes of host memory used
|
||||
host_seconds 69.94 # Real time elapsed on the host
|
||||
host_inst_rate 2339703 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2369997 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1186374997 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273296 # Number of bytes of host memory used
|
||||
host_seconds 57.44 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -65,5 +65,40 @@ system.cpu.num_busy_cycles 136297345 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 12719095 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 136293798 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu
|
|||
sim_ticks 202242260000 # Number of ticks simulated
|
||||
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 840358 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 851239 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1264562009 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296592 # Number of bytes of host memory used
|
||||
host_seconds 159.93 # Real time elapsed on the host
|
||||
host_inst_rate 1069571 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1083420 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1609480248 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282012 # Number of bytes of host memory used
|
||||
host_seconds 125.66 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -77,6 +77,41 @@ system.cpu.num_busy_cycles 404484520 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 12719095 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 136293798 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
|
|||
sim_ticks 913189263000 # Number of ticks simulated
|
||||
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1966439 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1966439 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 986784511 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271364 # Number of bytes of host memory used
|
||||
host_seconds 925.42 # Real time elapsed on the host
|
||||
host_inst_rate 2693565 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2693565 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1351665756 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 256712 # Number of bytes of host memory used
|
||||
host_seconds 675.60 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 1826378527 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
|
|||
sim_ticks 2623386226000 # Number of ticks simulated
|
||||
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1078959 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1078959 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1555422646 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280076 # Number of bytes of host memory used
|
||||
host_seconds 1686.61 # Real time elapsed on the host
|
||||
host_inst_rate 1099630 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1099630 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1585220760 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265440 # Number of bytes of host memory used
|
||||
host_seconds 1654.90 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -109,6 +109,41 @@ system.cpu.num_busy_cycles 5246772452 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu
|
|||
sim_ticks 861538200000 # Number of ticks simulated
|
||||
final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2200753 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2455102 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1227552560 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258852 # Number of bytes of host memory used
|
||||
host_seconds 701.83 # Real time elapsed on the host
|
||||
host_inst_rate 1785934 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1992340 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 996171702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301680 # Number of bytes of host memory used
|
||||
host_seconds 864.85 # Real time elapsed on the host
|
||||
sim_insts 1544563041 # Number of instructions simulated
|
||||
sim_ops 1723073853 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 1723076401 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462426 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1723073900 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu
|
|||
sim_ticks 2391205115000 # Number of ticks simulated
|
||||
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1176543 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1828326739 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268744 # Number of bytes of host memory used
|
||||
host_seconds 1307.87 # Real time elapsed on the host
|
||||
host_inst_rate 867002 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 967582 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1347305237 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 310408 # Number of bytes of host memory used
|
||||
host_seconds 1774.81 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1717270334 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -161,6 +161,41 @@ system.cpu.num_busy_cycles 4782410230 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462426 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1723073900 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu
|
|||
sim_ticks 2846007227500 # Number of ticks simulated
|
||||
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1097459 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1709940 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1038328376 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292828 # Number of bytes of host memory used
|
||||
host_seconds 2740.95 # Real time elapsed on the host
|
||||
host_inst_rate 1186122 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1848085 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1122213991 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278740 # Number of bytes of host memory used
|
||||
host_seconds 2536.06 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 5692014456 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 248500691 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
|
|||
sim_ticks 5882580526000 # Number of ticks simulated
|
||||
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 532297 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 829367 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1040955661 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 302560 # Number of bytes of host memory used
|
||||
host_seconds 5651.13 # Real time elapsed on the host
|
||||
host_inst_rate 693030 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1079804 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1355284560 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288492 # Number of bytes of host memory used
|
||||
host_seconds 4340.48 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -82,6 +82,41 @@ system.cpu.num_busy_cycles 11765161052 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 248500691 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.041684 # Number of seconds simulated
|
||||
sim_ticks 41683573000 # Number of ticks simulated
|
||||
final_tick 41683573000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.041682 # Number of seconds simulated
|
||||
sim_ticks 41681685000 # Number of ticks simulated
|
||||
final_tick 41681685000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 119929 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 119929 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 54395175 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269084 # Number of bytes of host memory used
|
||||
host_seconds 766.31 # Real time elapsed on the host
|
||||
host_inst_rate 117228 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 117228 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53167547 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270132 # Number of bytes of host memory used
|
||||
host_seconds 783.97 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 4289843 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3291848 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7581692 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4289843 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4289843 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4289843 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3291848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7581692 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 4290038 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3291997 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7582035 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 4290038 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 4290038 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 4290038 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3291997 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7582035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 41683192000 # Total gap between requests
|
||||
system.physmem.totGap 41681611000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr
|
|||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1157 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 435 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1049 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 74 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 284 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 541.521127 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 335.427822 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 417.351632 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 58 20.42% 20.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 54 19.01% 39.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 24 8.45% 47.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 12 4.23% 52.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 10 3.52% 55.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 9 3.17% 58.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 5 1.76% 60.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 5 1.76% 62.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 107 37.68% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 284 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 37971250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 131493750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 856 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 367.551402 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 223.659981 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 343.121338 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 258 30.14% 30.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 183 21.38% 51.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 95 11.10% 62.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 63 7.36% 69.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 46 5.37% 75.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 30 3.50% 78.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 51 5.96% 84.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 22 2.57% 87.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 108 12.62% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 856 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 35422000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 128009500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 68832500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 7689.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13939.35 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgQLat 7173.35 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26628.95 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25923.35 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -218,14 +216,18 @@ system.physmem.busUtilRead 0.06 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 4086 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4077 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 8441310.65 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.75 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 7581692 # Throughput (bytes/s)
|
||||
system.physmem.avgGap 8440990.48 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 39211333500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1391780000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1076956500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 7582035 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
|
|
@ -236,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 316032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 5782000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 45941000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 45945000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 13412627 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 13412628 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 3768498 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 50.757737 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 19996264 # DTB read hits
|
||||
system.cpu.dtb.read_hits 19996260 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 19996274 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501866 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 19996270 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6501862 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6501889 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498130 # DTB hits
|
||||
system.cpu.dtb.write_accesses 6501885 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26498122 # DTB hits
|
||||
system.cpu.dtb.data_misses 33 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 26498163 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956950 # ITB hits
|
||||
system.cpu.dtb.data_accesses 26498155 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 9956951 # ITB hits
|
||||
system.cpu.itb.fetch_misses 49 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 9956999 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 9957000 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -283,10 +285,10 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 83367147 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 83363371 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedTaken 5905663 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
|
|
@ -305,12 +307,12 @@ system.cpu.execution_unit.executions 57404027 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 82970332 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 82970271 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10410 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7759392 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607755 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.692506 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 10393 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7755613 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607758 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.696618 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -322,36 +324,36 @@ system.cpu.committedInsts 91903056 # Nu
|
|||
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.907121 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.907079 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.907121 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102389 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.907079 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102439 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.102389 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27686803 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680344 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.789312 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34115467 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251680 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.078044 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33515800 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 1.102439 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 27683021 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 55680350 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 66.792345 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 34111687 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 59.080725 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 33512024 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 59.797353 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65340657 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026490 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.623014 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29507392 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 59.800061 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 65336871 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026500 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.624006 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29503616 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.605491 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.utilization 64.608418 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1492.188372 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1492.194030 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.188372 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.728608 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.728608 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.194030 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.728610 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.728610 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
|
|
@ -359,44 +361,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 613
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 959 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 19923420 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 19923420 # Number of data accesses
|
||||
system.cpu.icache.tags.tag_accesses 19923422 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 19923422 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 9945551 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11399 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 329283500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 329283500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 329283500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 329283500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 329283500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 329283500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11400 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11400 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11400 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11400 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11400 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11400 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327908250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 327908250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 327908250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 327908250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 327908250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 327908250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956951 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956951 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956951 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9956951 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9956951 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9956951 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28887.051496 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28763.881579 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28763.881579 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28763.881579 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28763.881579 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -405,38 +407,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1880 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1880 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1880 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1880 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1880 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1880 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268822750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 268822750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268822750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 268822750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268822750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 268822750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 268503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 268503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 268503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28204.096639 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28204.096639 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 18194218 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 18195042 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
|
|
@ -452,21 +454,21 @@ system.cpu.toL2Bus.data_through_bus 758400 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 14800250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 14805000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3515750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3522500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2189.597840 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2189.603987 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.844631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.766792 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.844250 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.772066 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 350.987671 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3282 # Occupied blocks per task id
|
||||
|
|
@ -502,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191765250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32319750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 224085000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 125611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 191765250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 157931250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 349696500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 191765250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 157931250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 349696500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191445500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31242750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 222688250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 121662250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 121662250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 191445500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 152905000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 344350500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 191445500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 152905000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 344350500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -537,17 +539,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68520.221904 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74034.952607 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69243.858831 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70651.713124 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70651.713124 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69734.811665 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69734.811665 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -567,17 +569,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156642750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27057250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 183700000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104540000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104540000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156642750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131597250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 288240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156642750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131597250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 288240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156316500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25982750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 182299250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100579250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100579250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156316500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 126562000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 282878500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156316500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 126562000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 282878500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -589,25 +591,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55947.208304 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61570.497630 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56685.090174 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58408.391405 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58408.391405 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1441.382253 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488456 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1441.383569 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26488452 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.634728 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.632928 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.382253 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.383569 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
|
||||
|
|
@ -619,30 +621,30 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492835 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492835 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488456 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488456 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488456 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488456 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8268 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8268 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8845 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8845 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8845 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8845 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40979500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 40979500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 507652000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 507652000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 548631500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 548631500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 548631500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 548631500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995619 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 19995619 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492833 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492833 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26488452 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26488452 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26488452 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26488452 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 579 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 579 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8270 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8270 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8849 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8849 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8849 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8849 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39903000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 39903000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 493053000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 493053000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 532956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 532956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 532956000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 532956000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -659,32 +661,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000334
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62027.303561 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 25755 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68917.098446 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68917.098446 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59619.467956 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59619.467956 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60227.822353 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60227.822353 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 844 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 836 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.515403 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.770335 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6520 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6520 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6622 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6622 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6622 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6622 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6522 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6522 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 6626 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 6626 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 6626 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 6626 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
||||
|
|
@ -693,14 +695,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33343250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33343250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127629000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 127629000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160972250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 160972250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160972250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 160972250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32266250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32266250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 123679750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 123679750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155946000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 155946000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155946000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 155946000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -709,14 +711,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67928.947368 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67928.947368 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70755.005721 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70755.005721 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu
|
|||
sim_ticks 45951567500 # Number of ticks simulated
|
||||
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1649677 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1649676 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 824838449 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275016 # Number of bytes of host memory used
|
||||
host_seconds 55.71 # Real time elapsed on the host
|
||||
host_inst_rate 2663178 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2663177 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1331588953 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260384 # Number of bytes of host memory used
|
||||
host_seconds 34.51 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 91903136 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 10240685 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91903089 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu
|
|||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1382014 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1382013 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1785419086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233256 # Number of bytes of host memory used
|
||||
host_seconds 66.50 # Real time elapsed on the host
|
||||
host_inst_rate 1199929 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1199929 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1550185026 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269088 # Number of bytes of host memory used
|
||||
host_seconds 76.59 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 237458632 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 10240685 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91903089 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu
|
|||
sim_ticks 103106766000 # Number of ticks simulated
|
||||
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1878588 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2056872 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1124059947 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262308 # Number of bytes of host memory used
|
||||
host_seconds 91.73 # Real time elapsed on the host
|
||||
host_inst_rate 1728223 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1892237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1034088491 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304984 # Number of bytes of host memory used
|
||||
host_seconds 99.71 # Real time elapsed on the host
|
||||
sim_insts 172317409 # Number of instructions simulated
|
||||
sim_ops 188670891 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 206213533 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 40300311 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 188671292 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu
|
|||
sim_ticks 232072304000 # Number of ticks simulated
|
||||
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1152638 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1262262 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1556630640 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271024 # Number of bytes of host memory used
|
||||
host_seconds 149.09 # Real time elapsed on the host
|
||||
host_inst_rate 924224 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1012125 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1248159761 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313696 # Number of bytes of host memory used
|
||||
host_seconds 185.93 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 188185920 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -153,6 +153,41 @@ system.cpu.num_busy_cycles 464144608 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 40300311 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 188671292 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu
|
|||
sim_ticks 96722945000 # Number of ticks simulated
|
||||
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2588672 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2588674 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1294344494 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233760 # Number of bytes of host memory used
|
||||
host_seconds 74.73 # Real time elapsed on the host
|
||||
host_inst_rate 2358558 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2358560 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1179286883 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269756 # Number of bytes of host memory used
|
||||
host_seconds 82.02 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -65,5 +65,40 @@ system.cpu.num_busy_cycles 193445891 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 15132745 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 193445773 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu
|
|||
sim_ticks 270563082000 # Number of ticks simulated
|
||||
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1313314 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1313315 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1836878526 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242660 # Number of bytes of host memory used
|
||||
host_seconds 147.30 # Real time elapsed on the host
|
||||
host_inst_rate 1069922 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1069924 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1496457293 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278484 # Number of bytes of host memory used
|
||||
host_seconds 180.80 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -69,6 +69,41 @@ system.cpu.num_busy_cycles 541126164 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 15132745 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 193445773 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
|
|||
sim_ticks 131393279000 # Number of ticks simulated
|
||||
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1414135 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2370219 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1406875667 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267896 # Number of bytes of host memory used
|
||||
host_seconds 93.39 # Real time elapsed on the host
|
||||
host_inst_rate 1131336 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1896222 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1125528252 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303676 # Number of bytes of host memory used
|
||||
host_seconds 116.74 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 262786559 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 12326938 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 133863963 60.47% 61.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 772953 0.35% 61.35% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 7031501 3.18% 64.53% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 1352943 0.61% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 221363385 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
|
|||
sim_ticks 250953957000 # Number of ticks simulated
|
||||
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 770398 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1291257 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1463865173 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276604 # Number of bytes of host memory used
|
||||
host_seconds 171.43 # Real time elapsed on the host
|
||||
host_inst_rate 652190 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1093130 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1239252699 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313428 # Number of bytes of host memory used
|
||||
host_seconds 202.50 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -74,6 +74,41 @@ system.cpu.num_busy_cycles 501907914 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 12326938 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 133863963 60.47% 61.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 772953 0.35% 61.35% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 7031501 3.18% 64.53% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 1352943 0.61% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 221363385 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu
|
|||
sim_ticks 1870335522500 # Number of ticks simulated
|
||||
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3158607 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3158605 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 93543458564 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309852 # Number of bytes of host memory used
|
||||
host_seconds 19.99 # Real time elapsed on the host
|
||||
host_inst_rate 2258331 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2258329 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66881420828 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346748 # Number of bytes of host memory used
|
||||
host_seconds 27.97 # Real time elapsed on the host
|
||||
sim_insts 63154034 # Number of instructions simulated
|
||||
sim_ops 63154034 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -307,6 +307,41 @@ system.cpu0.num_busy_cycles 57233845.415270 #
|
|||
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
|
||||
system.cpu0.Branches 8650704 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 3102513 5.42% 5.42% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 37823162 66.09% 71.51% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 59490 0.10% 71.61% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 18488 0.03% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 9401052 16.43% 88.08% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 5956984 10.41% 98.49% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 866222 1.51% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 57230132 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
|
||||
system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed
|
||||
|
|
@ -612,6 +647,41 @@ system.cpu1.num_busy_cycles 5936690.922345 #
|
|||
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
|
||||
system.cpu1.Branches 836747 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 3533366 59.53% 63.57% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 7265 0.12% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 5935766 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
|
|||
sim_ticks 1829332258000 # Number of ticks simulated
|
||||
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3003513 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3003511 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 91515177007 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306744 # Number of bytes of host memory used
|
||||
host_seconds 19.99 # Real time elapsed on the host
|
||||
host_inst_rate 2367650 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2367648 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72140813877 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 343680 # Number of bytes of host memory used
|
||||
host_seconds 25.36 # Real time elapsed on the host
|
||||
sim_insts 60038305 # Number of instructions simulated
|
||||
sim_ops 60038305 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -160,6 +160,41 @@ system.cpu.num_busy_cycles 60055430.608382 #
|
|||
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064385 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199104 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39460699 65.71% 71.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60680 0.10% 71.14% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 25609 0.04% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975081 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050143 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,33 +4,15 @@ sim_seconds 0.912098 # Nu
|
|||
sim_ticks 912098398000 # Number of ticks simulated
|
||||
final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1169212 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1505339 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 17301899059 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 421332 # Number of bytes of host memory used
|
||||
host_seconds 52.72 # Real time elapsed on the host
|
||||
host_inst_rate 1024713 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1319299 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15163617701 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 465872 # Number of bytes of host memory used
|
||||
host_seconds 60.15 # Real time elapsed on the host
|
||||
sim_insts 61636937 # Number of instructions simulated
|
||||
sim_ops 79356422 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
|
||||
|
|
@ -86,6 +68,24 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To
|
|||
system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 64987015 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 59274552 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -397,6 +397,41 @@ system.cpu0.num_busy_cycles 39676799.500046 #
|
|||
system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles
|
||||
system.cpu0.Branches 5492144 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 16326 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 24520115 62.53% 62.57% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 45259 0.12% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCmp 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCvt 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatMult 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatDiv 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatSqrt 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAdd 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAddAcc 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAlu 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCmp 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCvt 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMisc 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMult 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMultAcc 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShift 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShiftAcc 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdSqrt 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAdd 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAlu 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCmp 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCvt 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatDiv 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMisc 1421 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 62.69% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 8359235 21.32% 84.01% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 6270624 15.99% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 39212980 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed
|
||||
system.cpu0.icache.tags.replacements 428546 # number of replacements
|
||||
|
|
@ -627,6 +662,41 @@ system.cpu1.num_busy_cycles 40793919.244318 #
|
|||
system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles
|
||||
system.cpu1.Branches 5037975 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 12508 0.03% 0.03% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 26844895 66.65% 66.68% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 49628 0.12% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 737 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.80% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 7642991 18.98% 85.78% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 5728160 14.22% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 40278919 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed
|
||||
system.cpu1.icache.tags.replacements 433942 # number of replacements
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.332812 # Nu
|
|||
sim_ticks 2332811899500 # Number of ticks simulated
|
||||
final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1065837 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1370594 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41157671581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 420236 # Number of bytes of host memory used
|
||||
host_seconds 56.68 # Real time elapsed on the host
|
||||
host_inst_rate 975328 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1254205 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 37662621026 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 462792 # Number of bytes of host memory used
|
||||
host_seconds 61.94 # Real time elapsed on the host
|
||||
sim_insts 60411489 # Number of instructions simulated
|
||||
sim_ops 77685090 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -182,6 +182,41 @@ system.cpu.num_busy_cycles 78801726.992856 #
|
|||
system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983110 # Percentage of idle cycles
|
||||
system.cpu.Branches 10299261 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 50337551 64.69% 64.72% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 87780 0.11% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 2117 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 15640088 20.10% 84.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 11722333 15.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 77818387 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 850590 # number of replacements
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,66 +4,15 @@ sim_seconds 2.332812 # Nu
|
|||
sim_ticks 2332811899500 # Number of ticks simulated
|
||||
final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1003640 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1290613 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38755909714 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 421296 # Number of bytes of host memory used
|
||||
host_seconds 60.19 # Real time elapsed on the host
|
||||
host_inst_rate 860450 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1106481 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33226597982 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 465868 # Number of bytes of host memory used
|
||||
host_seconds 70.21 # Real time elapsed on the host
|
||||
sim_insts 60411489 # Number of instructions simulated
|
||||
sim_ops 77685090 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 6490328 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 2581740 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 121450892 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 1610064 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6719076 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 13912 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 101447 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 3318 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 40350 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14118200 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 351445 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 402516 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 811824 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 211251 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 2782191 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 91028 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 1106707 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52062017 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 211251 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 91028 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1587454 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 602612 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 690182 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2880248 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1587454 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 211251 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 3384803 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 1796889 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
|
|
@ -76,31 +25,82 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9
|
|||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55969745 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566887 # Total data (bytes)
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 6490264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 2581696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3703360 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 1610036 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6719176 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 13912 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 101446 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 3318 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 40339 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 57865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 351445 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 402509 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 811819 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 211251 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 2782163 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 91028 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 1106688 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 211251 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 91028 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1587509 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 602612 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 690170 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2880291 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1587509 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 211251 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 3384775 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 1796858 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55969742 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566879 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 62244 # number of replacements
|
||||
system.l2c.tags.tagsinuse 50006.487761 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1678458 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 127629 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 13.151071 # Average number of references to valid blocks.
|
||||
system.l2c.tags.replacements 62245 # number of replacements
|
||||
system.l2c.tags.tagsinuse 50006.493098 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1678467 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 127630 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 13.151038 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 36900.766383 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 36901.760029 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993822 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4918.263908 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 3149.549186 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 3148.560878 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2096.452041 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 2939.468488 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.563061 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::writebacks 0.563076 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075047 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.048058 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.048043 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.031989 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.044853 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.763038 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.763039 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
|
||||
|
|
@ -111,19 +111,19 @@ system.l2c.tags.age_task_id_blocks_1024::3 9187 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::4 52391 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 17104555 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 17104555 # Number of data accesses
|
||||
system.l2c.tags.tag_accesses 17104618 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 17104618 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 9008 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 3279 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.inst 473060 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 196973 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 196974 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 4855 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 2031 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 365811 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 169795 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1224812 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 592687 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 592687 # number of Writeback hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 169798 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1224816 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 592692 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 592692 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
|
|
@ -133,28 +133,28 @@ system.l2c.ReadExReq_hits::total 113738 # nu
|
|||
system.l2c.demand_hits::cpu0.dtb.walker 9008 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 3279 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 473060 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 260317 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 260318 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 4855 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 2031 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 365811 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 220189 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1338550 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 220192 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1338554 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 9008 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 3279 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 473060 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 260317 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 260318 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 4855 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 2031 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 365811 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 220189 # number of overall hits
|
||||
system.l2c.overall_hits::total 1338550 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 220192 # number of overall hits
|
||||
system.l2c.overall_hits::total 1338554 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.inst 7286 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 5804 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 5803 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 3318 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 4068 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 20481 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 1525 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 1394 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
|
||||
|
|
@ -164,17 +164,17 @@ system.l2c.ReadExReq_misses::total 133474 # nu
|
|||
system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 7286 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 102226 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 102225 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 3318 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 41120 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 153955 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 153954 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 7286 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 102226 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 102225 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 3318 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 41120 # number of overall misses
|
||||
system.l2c.overall_misses::total 153955 # number of overall misses
|
||||
system.l2c.overall_misses::total 153954 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9010 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 3282 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 480346 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -182,10 +182,10 @@ system.l2c.ReadReq_accesses::cpu0.data 202777 # nu
|
|||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4855 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 2031 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 369129 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 173863 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1245293 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 592687 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 592687 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 173866 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1245296 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 592692 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 592692 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 1537 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 1408 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -199,8 +199,8 @@ system.l2c.demand_accesses::cpu0.data 362543 # nu
|
|||
system.l2c.demand_accesses::cpu1.dtb.walker 4855 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 2031 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 369129 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 261309 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1492505 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 261312 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1492508 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 9010 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 3282 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 480346 # number of overall (read+write) accesses
|
||||
|
|
@ -208,15 +208,15 @@ system.l2c.overall_accesses::cpu0.data 362543 # nu
|
|||
system.l2c.overall_accesses::cpu1.dtb.walker 4855 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 2031 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 369129 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 261309 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1492505 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 261312 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1492508 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000914 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015168 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.028623 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.028618 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.inst 0.008989 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.023398 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.016447 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.023397 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992193 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990057 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
|
||||
|
|
@ -226,17 +226,17 @@ system.l2c.ReadExReq_miss_rate::total 0.539917 # mi
|
|||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000914 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.015168 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.281969 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.281967 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.008989 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.157362 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.103152 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.157360 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.103151 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000914 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.015168 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.281969 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.281967 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.008989 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.157362 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.103152 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.157360 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.103151 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
|||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 57863 # number of writebacks
|
||||
system.l2c.writebacks::total 57863 # number of writebacks
|
||||
system.l2c.writebacks::writebacks 57865 # number of writebacks
|
||||
system.l2c.writebacks::total 57865 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
|
|
@ -254,8 +254,8 @@ system.cf0.dma_read_txs 0 # Nu
|
|||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.toL2Bus.throughput 59119535 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 137914755 # Total data (bytes)
|
||||
system.toL2Bus.throughput 59119724 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 137915195 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iobus.throughput 48895283 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 114063499 # Total data (bytes)
|
||||
|
|
@ -366,6 +366,41 @@ system.cpu0.num_busy_cycles 75843061.764530 #
|
|||
system.cpu0.not_idle_fraction 0.016397 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.983603 # Percentage of idle cycles
|
||||
system.cpu0.Branches 5613326 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 16463 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 26898614 64.08% 64.12% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 45874 0.11% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCmp 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCvt 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatMult 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatDiv 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatSqrt 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAdd 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAddAcc 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAlu 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCmp 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCvt 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMisc 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMult 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMultAcc 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShift 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdSqrt 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.23% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMisc 1340 0.00% 64.24% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 64.24% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.24% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.24% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 8305325 19.79% 84.02% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 6706507 15.98% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 41974123 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu0.icache.tags.replacements 850590 # number of replacements
|
||||
|
|
@ -432,14 +467,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.tags.replacements 623340 # number of replacements
|
||||
system.cpu0.dcache.tags.replacements 623343 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 23628946 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 623852 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 37.875884 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.total_refs 23628961 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 37.875726 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291431 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705599 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291422 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705608 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881429 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118566 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -448,59 +483,59 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278
|
|||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 97635044 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 97635044 # Number of data accesses
|
||||
system.cpu0.dcache.tags.tag_accesses 97635119 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 97635119 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6996051 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 6184470 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 13180521 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::cpu1.data 6184476 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 13180527 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 5775160 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu1.data 4187066 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 9962226 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu1.data 4187070 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 9962230 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139339 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96697 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96699 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 236038 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145986 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101232 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 247218 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101235 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 12771211 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 10371536 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 23142747 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 10371546 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 23142757 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 12771211 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 10371536 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 23142747 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 10371546 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 23142757 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 196129 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::cpu1.data 169328 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 365457 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::cpu1.data 169330 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 161303 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu1.data 88854 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 250157 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6648 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4535 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 11184 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 357432 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 258182 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 615614 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 258184 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 615616 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 357432 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 258182 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 615614 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 258184 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 615616 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7192180 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353798 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 13545978 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353806 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 13545986 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5936463 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275920 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 10212383 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275924 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145987 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101232 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101235 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145986 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101232 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101235 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 13128643 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu1.data 10629718 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 23758361 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu1.data 10629730 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 23758373 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 13128643 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu1.data 10629718 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 23758361 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu1.data 10629730 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 23758373 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027270 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses
|
||||
|
|
@ -508,14 +543,14 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172
|
|||
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020780 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045538 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044798 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044807 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045239 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027225 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024289 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.025911 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027225 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024289 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.025911 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -524,8 +559,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 592687 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 592687 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 592692 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 592692 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
@ -634,6 +669,41 @@ system.cpu1.num_busy_cycles 69683264.930565 #
|
|||
system.cpu1.not_idle_fraction 0.016273 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.983727 # Percentage of idle cycles
|
||||
system.cpu1.Branches 4685935 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 12055 0.03% 0.03% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 23438937 65.39% 65.42% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 41906 0.12% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 777 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.54% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 7334763 20.46% 86.01% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 5015826 13.99% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 35844264 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112126 # Nu
|
|||
sim_ticks 5112126264500 # Number of ticks simulated
|
||||
final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1019778 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2087932 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26075321841 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 640200 # Number of bytes of host memory used
|
||||
host_seconds 196.05 # Real time elapsed on the host
|
||||
host_inst_rate 1285356 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2631685 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32866027497 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 626676 # Number of bytes of host memory used
|
||||
host_seconds 155.54 # Real time elapsed on the host
|
||||
sim_insts 199929810 # Number of instructions simulated
|
||||
sim_ops 409343850 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -141,6 +141,41 @@ system.cpu.num_busy_cycles 453735690.308166
|
|||
system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
|
||||
system.cpu.Branches 43125514 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 175310 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373241321 91.18% 91.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144368 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27238816 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8422097 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 409344880 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 790558 # number of replacements
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu
|
|||
sim_ticks 200409284500 # Number of ticks simulated
|
||||
final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22333008 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22332995 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8544906534 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 473604 # Number of bytes of host memory used
|
||||
host_seconds 23.45 # Real time elapsed on the host
|
||||
host_inst_rate 14275836 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 14275831 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5462126987 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 513712 # Number of bytes of host memory used
|
||||
host_seconds 36.69 # Real time elapsed on the host
|
||||
sim_insts 523790075 # Number of instructions simulated
|
||||
sim_ops 523790075 # Number of ops (including micro ops) simulated
|
||||
testsys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -113,6 +113,41 @@ testsys.cpu.num_busy_cycles 20262547.637842 #
|
|||
testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles
|
||||
testsys.cpu.Branches 2929848 # Number of branches fetched
|
||||
testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntAlu 12147340 59.95% 63.47% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatAdd 4653 0.02% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemRead 4230637 20.88% 84.48% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemWrite 2319552 11.45% 95.93% # Class of executed instruction
|
||||
testsys.cpu.op_class::IprAccess 824102 4.07% 100.00% # Class of executed instruction
|
||||
testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
testsys.cpu.op_class::total 20261680 # Class of executed instruction
|
||||
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed
|
||||
|
|
@ -336,6 +371,41 @@ drivesys.cpu.num_busy_cycles 19051473.772069 #
|
|||
drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles
|
||||
drivesys.cpu.Branches 2793313 # Number of branches fetched
|
||||
drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntAlu 11538630 60.57% 63.84% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatAdd 138 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatDiv 23 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdAdd 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdAlu 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdCmp 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdCvt 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdMisc 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdMult 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdShift 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::MemRead 4026028 21.13% 85.08% # Class of executed instruction
|
||||
drivesys.cpu.op_class::MemWrite 2085021 10.94% 96.02% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IprAccess 757336 3.98% 100.00% # Class of executed instruction
|
||||
drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
drivesys.cpu.op_class::total 19051393 # Class of executed instruction
|
||||
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
drivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed
|
||||
drivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed
|
||||
|
|
@ -455,11 +525,11 @@ sim_seconds 0.000407 # Nu
|
|||
sim_ticks 407341500 # Number of ticks simulated
|
||||
final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 6913599452 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 6911980937 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5373353780 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 524140 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 7312019890 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 7310591323 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5683411932 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 513712 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 523862353 # Number of instructions simulated
|
||||
sim_ops 523862353 # Number of ops (including micro ops) simulated
|
||||
testsys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -561,6 +631,41 @@ testsys.cpu.num_busy_cycles 36406.828108 # Nu
|
|||
testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles
|
||||
testsys.cpu.Branches 5238 # Number of branches fetched
|
||||
testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction
|
||||
testsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction
|
||||
testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
testsys.cpu.op_class::total 36126 # Class of executed instruction
|
||||
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
|
||||
|
|
@ -735,6 +840,41 @@ drivesys.cpu.num_busy_cycles 36082.640939 # Nu
|
|||
drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles
|
||||
drivesys.cpu.Branches 5243 # Number of branches fetched
|
||||
drivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntMult 44 0.12% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntDiv 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatAdd 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatCmp 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatDiv 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
|
||||
drivesys.cpu.op_class::MemRead 7678 21.24% 84.84% # Class of executed instruction
|
||||
drivesys.cpu.op_class::MemWrite 3936 10.89% 95.73% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IprAccess 1545 4.27% 100.00% # Class of executed instruction
|
||||
drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
drivesys.cpu.op_class::total 36152 # Class of executed instruction
|
||||
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
|
||||
drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu
|
|||
sim_ticks 25552000 # Number of ticks simulated
|
||||
final_tick 25552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 78801 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 78787 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 314994021 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262608 # Number of bytes of host memory used
|
||||
host_inst_rate 78387 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 78372 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 313333088 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263656 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr
|
|||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 313 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,27 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 54 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 317.629630 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 196.201768 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 327.982069 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 16 29.63% 29.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 16 29.63% 59.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 7 12.96% 72.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 4 7.41% 79.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 1 1.85% 81.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1 1.85% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 3.70% 87.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7 12.96% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 54 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2560250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 12605250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 86 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 330.418605 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 204.922237 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 319.300576 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 27 31.40% 31.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 21 24.42% 55.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 10 11.63% 67.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 8 9.30% 76.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 1 1.16% 77.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 3.49% 81.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 7 8.14% 89.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 2.33% 91.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7 8.14% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 86 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3845750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 12639500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 7700000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 5458.96 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 16417.91 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgQLat 8199.89 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26876.87 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26949.89 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1174.70 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1174.70 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -223,7 +222,11 @@ system.physmem.readRowHitRate 80.60 # Ro
|
|||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 54450.96 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.60 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.physmem.memoryStateTime::IDLE 13500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 780000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 22839000 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1172197871 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
|
|
@ -237,7 +240,7 @@ system.membus.data_through_bus 29952 # To
|
|||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4371250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 4371000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 1632 # Number of BP lookups
|
||||
|
|
@ -304,9 +307,9 @@ system.cpu.execution_unit.executions 4448 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 11596 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 11594 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 469 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 43730 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 7375 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 14.431073 # Percentage of cycles cpu is active
|
||||
|
|
@ -343,14 +346,14 @@ system.cpu.stage4.idleCycles 46641 # Nu
|
|||
system.cpu.stage4.runCycles 4464 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 8.734957 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 142.169993 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 142.073249 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.169993 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069419 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069419 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 142.073249 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.069372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.069372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id
|
||||
|
|
@ -369,12 +372,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n
|
|||
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 355 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25349750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25349750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25349750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25349750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25349750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25349750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24875750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24875750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24875750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24875750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24875750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24875750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
|
||||
|
|
@ -387,12 +390,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978
|
|||
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71407.746479 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 71407.746479 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 71407.746479 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70072.535211 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70072.535211 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70072.535211 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70072.535211 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -413,24 +416,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302
|
|||
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21532500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 21532500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21532500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 21532500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21532500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 21532500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21058500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 21058500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21058500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 21058500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21058500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 21058500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71299.668874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71299.668874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69730.132450 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69730.132450 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1174702567 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
|
||||
|
|
@ -449,19 +452,19 @@ system.cpu.toL2Bus.reqLayer0.occupancy 235000 # La
|
|||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 508000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 274750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 198.925679 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 198.803908 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.205920 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.719759 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004340 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001731 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006071 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.109548 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.694360 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001730 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006067 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
|
||||
|
|
@ -485,17 +488,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21214000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6927250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 28141250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4931500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4931500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21214000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11858750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 33072750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21214000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11858750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 33072750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20740000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7180750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 27920750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5181250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5181250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20740000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12362000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 33102000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20740000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12362000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 33102000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -518,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70478.405316 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72918.421053 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71063.762626 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67554.794521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67554.794521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70517.590618 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70517.590618 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68903.654485 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75586.842105 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70506.944444 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70976.027397 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70976.027397 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70579.957356 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70579.957356 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -548,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17443000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5745750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23188750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4029500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4029500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17443000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9775250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27218250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17443000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9775250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27218250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16969500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5998750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22968250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4278250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4278250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16969500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10277000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27246500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16969500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10277000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27246500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -570,27 +573,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57950.166113 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58557.449495 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55198.630137 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55198.630137 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56377.076412 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63144.736842 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58000.631313 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58606.164384 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58606.164384 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.450623 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.396801 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.450623 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025256 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025256 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.396801 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025243 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025243 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
|
||||
|
|
@ -613,14 +616,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n
|
|||
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 447 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7371250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7371250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21672250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21672250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29043500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29043500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29043500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29043500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7625750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7625750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22645250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22645250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30271000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30271000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30271000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30271000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -637,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75992.268041 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75992.268041 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61920.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61920.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64974.272931 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78615.979381 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 78615.979381 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64700.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64700.714286 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67720.357942 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67720.357942 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.730769 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.307692 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -669,14 +672,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7028750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7028750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5009000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5009000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12037750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12037750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12037750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12037750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7282250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7282250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5258750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5258750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12541000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12541000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12541000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12541000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -685,14 +688,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73986.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73986.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68616.438356 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68616.438356 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76655.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76655.263158 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72037.671233 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72037.671233 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000021 # Number of seconds simulated
|
||||
sim_ticks 21078000 # Number of ticks simulated
|
||||
final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 21025000 # Number of ticks simulated
|
||||
final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72140 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 72127 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 238549554 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265696 # Number of bytes of host memory used
|
||||
host_inst_rate 72274 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 72262 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 238397605 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265716 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu
|
|||
system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 487 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 488 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 21045000 # Total gap between requests
|
||||
system.physmem.totGap 20992000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3243750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 4394750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 7645000 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.58 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.61 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 394 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43125.00 # Average gap between requests
|
||||
system.physmem.avgGap 43016.39 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1478698169 # Throughput (bytes/s)
|
||||
system.physmem.memoryStateTime::IDLE 22000 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 15304250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1482425684 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 415 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 414 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -234,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 31168 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.7 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 2894 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted
|
||||
|
|
@ -252,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 2078 # DTB read hits
|
||||
system.cpu.dtb.read_hits 2077 # DTB read hits
|
||||
system.cpu.dtb.read_misses 47 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 2125 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 2124 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 1062 # DTB write hits
|
||||
system.cpu.dtb.write_misses 31 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 1093 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 3140 # DTB hits
|
||||
system.cpu.dtb.data_hits 3139 # DTB hits
|
||||
system.cpu.dtb.data_misses 78 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 3218 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2388 # ITB hits
|
||||
system.cpu.dtb.data_accesses 3217 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2387 # ITB hits
|
||||
system.cpu.itb.fetch_misses 39 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 2427 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 2426 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -281,95 +285,95 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 42157 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 42051 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2770 # Number of cycles decode is running
|
||||
system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2769 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2628 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename
|
||||
system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2627 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups
|
||||
system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available
|
||||
|
|
@ -405,7 +409,7 @@ system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued
|
||||
|
|
@ -434,39 +438,39 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 10780 # Type of FU issued
|
||||
system.cpu.iq.rate 0.255711 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 10779 # Type of FU issued
|
||||
system.cpu.iq.rate 0.256332 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 112 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes
|
||||
system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
||||
|
|
@ -475,43 +479,43 @@ system.cpu.iew.memOrderViolationEvents 16 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 89 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3231 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs 3230 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1589 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1095 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.238916 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.239495 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 9612 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 5080 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6838 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 5069 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6811 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 6389 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -522,26 +526,61 @@ system.cpu.commit.branches 1050 # Nu
|
|||
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 127 # Number of function calls committed.
|
||||
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 26334 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 27415 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 26369 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 27413 # The number of ROB writes
|
||||
system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 6372 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 12785 # number of integer regfile reads
|
||||
system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 12784 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7268 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -556,61 +595,61 @@ system.cpu.toL2Bus.data_through_bus 31232 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5090 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1899 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5088 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1898 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 489 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31431750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31431750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31431750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2388 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2388 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2388 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2388 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2388 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2388 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204774 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.204774 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.204774 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.204774 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.204774 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.204774 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 64277.607362 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 64277.607362 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -631,34 +670,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315
|
|||
system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22098000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22098000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22098000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22098000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22098000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22098000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131910 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.131910 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.131910 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 219.244506 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.494883 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 59.749622 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004867 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id
|
||||
|
|
@ -684,17 +723,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 488 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21772000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7725500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29497500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5467500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5467500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21772000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13193000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34965000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21772000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13193000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34965000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -717,17 +756,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -747,17 +786,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17823000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6485500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4573000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4573000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17823000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11058500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 28881500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17823000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11058500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 28881500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -769,41 +808,41 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 107.267771 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 107.267771 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.026188 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.026188 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 5694 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5694 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2230 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2229 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
|
||||
|
|
@ -812,43 +851,43 @@ system.cpu.dcache.demand_misses::cpu.data 530 # n
|
|||
system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 530 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11467500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 34691233 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -868,30 +907,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174
|
|||
system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5462500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5462500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13377500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 3208000 # Number of ticks simulated
|
||||
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 105446 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 105415 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52907298 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268408 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 172950 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 172880 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 86758979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253924 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 6417 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu
|
|||
sim_ticks 138616 # Number of ticks simulated
|
||||
final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 14698 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 14697 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 318804 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 174728 # Number of bytes of host memory used
|
||||
host_seconds 0.43 # Real time elapsed on the host
|
||||
host_inst_rate 36011 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36008 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 781041 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 161164 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -210,6 +210,41 @@ system.cpu.num_busy_cycles 138616 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.369871
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 1041
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000118 # Nu
|
|||
sim_ticks 117611 # Number of ticks simulated
|
||||
final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 21881 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 21879 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 402676 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 177980 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
host_inst_rate 31716 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31714 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 583663 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 164416 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 117611 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.786874
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 253
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu
|
|||
sim_ticks 113627 # Number of ticks simulated
|
||||
final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 28822 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 28819 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 512426 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 175880 # Number of bytes of host memory used
|
||||
host_seconds 0.22 # Real time elapsed on the host
|
||||
host_inst_rate 50343 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50337 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 894983 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 161272 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 113627 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.473611
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1178
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu
|
|||
sim_ticks 93341 # Number of ticks simulated
|
||||
final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31508 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31505 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 460155 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 175808 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_inst_rate 52665 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52659 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 769125 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 161200 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -185,6 +185,41 @@ system.cpu.num_busy_cycles 93341 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.199848
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000144 # Nu
|
|||
sim_ticks 143853 # Number of ticks simulated
|
||||
final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 14935 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 14935 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 336198 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 174340 # Number of bytes of host memory used
|
||||
host_seconds 0.43 # Real time elapsed on the host
|
||||
host_inst_rate 53676 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 53669 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1208067 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 160752 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -160,6 +160,41 @@ system.cpu.num_busy_cycles 143853 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.011692
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu
|
|||
sim_ticks 32544000 # Number of ticks simulated
|
||||
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 163681 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 163603 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 832819326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277116 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 550056 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 549394 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2794675827 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262632 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 65088 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
sim_ticks 12006500 # Number of ticks simulated
|
||||
final_tick 12006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 11975500 # Number of ticks simulated
|
||||
final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 60243 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 60220 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 302796832 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264400 # Number of bytes of host memory used
|
||||
host_inst_rate 56599 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56579 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 283759448 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265424 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 12032 # Nu
|
|||
system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1002123850 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 453087911 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1455211760 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1002123850 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1002123850 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1002123850 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 453087911 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1455211760 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1004717966 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 454260782 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1458978748 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1004717966 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1004717966 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1004717966 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 454260782 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1458978748 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 273 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 11917000 # Total gap between requests
|
||||
system.physmem.totGap 11886000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,33 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 24 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 464 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 290.487911 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 387.347726 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 6 25.00% 25.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 4 16.67% 41.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 3 12.50% 54.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1 4.17% 58.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 8.33% 66.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 8.33% 75.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6 25.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 24 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1638000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7265500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 38 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 387.368421 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 224.223359 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 366.580725 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 14 36.84% 36.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 5 13.16% 50.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4 10.53% 60.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2 5.26% 65.79% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 5.26% 71.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 5.26% 76.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 5.26% 81.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1 2.63% 84.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6 15.79% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 38 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2067500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7186250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 4262500 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 6000.00 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 15613.55 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgQLat 7573.26 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26613.55 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1455.21 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26323.26 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1458.98 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1455.21 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1458.98 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.37 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.40 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.40 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
|
|
@ -220,10 +220,14 @@ system.physmem.readRowHits 225 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43652.01 # Average gap between requests
|
||||
system.physmem.avgGap 43538.46 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1455211760 # Throughput (bytes/s)
|
||||
system.physmem.memoryStateTime::IDLE 22000 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 260000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 7796750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1458978748 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 249 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
|
|
@ -234,9 +238,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
|||
system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17472 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2552500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.3 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 1176 # Number of BP lookups
|
||||
|
|
@ -281,42 +285,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 24014 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 23952 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 7722 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.907925 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.314691 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 6513 84.34% 84.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 7722 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.048971 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.291955 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5487 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 1153 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing
|
||||
|
|
@ -325,9 +329,9 @@ system.cpu.decode.BranchMispred 81 # Nu
|
|||
system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 5585 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1063 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename
|
||||
|
|
@ -354,23 +358,23 @@ system.cpu.iq.iqSquashedInstsIssued 54 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 7722 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.523828 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.238657 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 6098 78.97% 78.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 565 7.32% 86.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 401 5.19% 91.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 263 3.41% 94.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 200 2.59% 97.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 120 1.55% 99.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7722 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available
|
||||
|
|
@ -440,10 +444,10 @@ system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 4045 # Type of FU issued
|
||||
system.cpu.iq.rate 0.168443 # Inst issue rate
|
||||
system.cpu.iq.rate 0.168879 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 15897 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
||||
|
|
@ -484,26 +488,26 @@ system.cpu.iew.exec_nop 336 # nu
|
|||
system.cpu.iew.exec_refs 1130 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 644 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 388 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.160531 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.160947 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3658 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1710 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2211 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.152328 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 7228 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.356392 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.198445 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 6359 87.98% 87.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle
|
||||
|
|
@ -512,7 +516,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 7228 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -523,25 +527,60 @@ system.cpu.commit.branches 396 # Nu
|
|||
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 71 # Number of function calls committed.
|
||||
system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 12220 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 12203 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 11111 # The number of ROB writes
|
||||
system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 16292 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 10.060327 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 10.060327 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.099400 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.099400 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4672 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2825 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1455211760 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1458978748 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
|
|
@ -556,19 +595,19 @@ system.cpu.toL2Bus.data_through_bus 17472 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 315500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 316750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 93.163170 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 93.163170 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.045490 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.045490 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
|
||||
|
|
@ -587,12 +626,12 @@ system.cpu.icache.demand_misses::cpu.inst 250 # n
|
|||
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 250 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17591499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17591499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17591499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17591499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17591499 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17591499 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses
|
||||
|
|
@ -605,12 +644,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.234742
|
|||
system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70365.996000 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -631,36 +670,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188
|
|||
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13162249 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13162249 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13162249 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 122.028433 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.360563 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.667870 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002849 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
|
|
@ -678,17 +717,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12973500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4680750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17654250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1693750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1693750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12973500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6374500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12973500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6374500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19348000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -711,17 +750,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -741,17 +780,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10603500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3934250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14537750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1399750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1399750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10603500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5334000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15937500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10603500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5334000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15937500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14452750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1393500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1393500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5298500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15846250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5298500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15846250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -763,30 +802,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 45.630537 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 45.630537 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011140 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011140 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011129 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses
|
||||
|
|
@ -806,14 +845,14 @@ system.cpu.dcache.demand_misses::cpu.data 196 # n
|
|||
system.cpu.dcache.demand_misses::total 196 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 196 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 196 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7964000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7964000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5323250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5323250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13287250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13287250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13287250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13287250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7876750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7876750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5302250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5302250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13179000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -830,14 +869,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.205236
|
|||
system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67792.091837 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65459.876543 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67239.795918 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67239.795918 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
||||
|
|
@ -862,14 +901,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6461000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6461000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6461000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6461000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -878,14 +917,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu
|
|||
sim_ticks 1297500 # Number of ticks simulated
|
||||
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 59390 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 59366 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29878318 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267100 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 741583 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 738395 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 370291096 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253628 # Number of bytes of host memory used
|
||||
host_seconds 0.00 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 2596 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu
|
|||
sim_ticks 52548 # Number of ticks simulated
|
||||
final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 15623 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 15622 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 318507 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 173288 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_inst_rate 36298 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36291 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 739863 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 159844 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -209,6 +209,41 @@ system.cpu.num_busy_cycles 52548 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.426467
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 431
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu
|
|||
sim_ticks 44968 # Number of ticks simulated
|
||||
final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 18935 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 18932 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 330302 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 175652 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 32543 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 32537 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 567670 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 162088 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 44968 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.661804
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 87
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu
|
|||
sim_ticks 43073 # Number of ticks simulated
|
||||
final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22164 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22160 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 370326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 173416 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 51660 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51645 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 862979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 159984 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 43073 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.412904
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu
|
|||
sim_ticks 35432 # Number of ticks simulated
|
||||
final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22204 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22201 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 305145 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 174496 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 51262 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 704386 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 159904 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -184,6 +184,41 @@ system.cpu.num_busy_cycles 35432 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.200610
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu
|
|||
sim_ticks 52498 # Number of ticks simulated
|
||||
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 10658 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 10657 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 217095 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 172908 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_inst_rate 55191 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 55175 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1123673 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 158428 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -159,6 +159,41 @@ system.cpu.num_busy_cycles 52498 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.958322
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 16524000 # Number of ticks simulated
|
||||
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 56666 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56644 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 363064230 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275808 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 366311 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 365532 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2339184598 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262348 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 33048 # Nu
|
|||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 17056000 # Number of ticks simulated
|
||||
final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 16955000 # Number of ticks simulated
|
||||
final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 29277 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36530 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 108745688 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308972 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 43189 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 53887 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 159459409 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309444 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu
|
|||
system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 392 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 16998500 # Total gap between requests
|
||||
system.physmem.totGap 16897500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
|
|
@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 4223500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3795000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 5431250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.49 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.56 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 326 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43363.52 # Average gap between requests
|
||||
system.physmem.avgGap 43105.87 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1467166979 # Throughput (bytes/s)
|
||||
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 15324750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1475906812 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total 25024 # Cu
|
|||
system.membus.data_through_bus 25024 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 2481 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
|
||||
|
|
@ -420,39 +424,39 @@ system.cpu.itb.inst_accesses 0 # IT
|
|||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 34113 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 33911 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
|
||||
|
|
@ -461,9 +465,9 @@ system.cpu.decode.BranchMispred 159 # Nu
|
|||
system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename
|
||||
|
|
@ -490,23 +494,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
|
||||
|
|
@ -576,10 +580,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
||||
system.cpu.iq.rate 0.261513 # Inst issue rate
|
||||
system.cpu.iq.rate 0.263071 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
|
|
@ -612,43 +616,43 @@ system.cpu.iew.memOrderViolationEvents 21 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.249846 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.251364 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3883 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers 7789 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -659,25 +663,60 @@ system.cpu.commit.branches 1007 # Nu
|
|||
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5729 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23225 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 23248 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23415 # The number of ROB writes
|
||||
system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39210 # number of integer regfile reads
|
||||
system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39214 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -692,22 +731,22 @@ system.cpu.toL2Bus.data_through_bus 27904 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4184 # Number of data accesses
|
||||
|
|
@ -723,12 +762,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n
|
|||
system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 363 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
||||
|
|
@ -741,12 +780,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441
|
|||
system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -767,39 +806,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290
|
|||
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses
|
||||
|
|
@ -823,17 +862,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -856,17 +895,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -892,17 +931,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -914,39 +953,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses
|
||||
system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
|
||||
|
|
@ -963,22 +1002,22 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n
|
|||
system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 496 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
|
||||
|
|
@ -989,22 +1028,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626
|
|||
system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -1031,14 +1070,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1047,14 +1086,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 17056000 # Number of ticks simulated
|
||||
final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 16955000 # Number of ticks simulated
|
||||
final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 53685 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 66982 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 199380443 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308976 # Number of bytes of host memory used
|
||||
host_inst_rate 52426 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 65410 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 193552438 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308400 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu
|
|||
system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 392 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 16998500 # Total gap between requests
|
||||
system.physmem.totGap 16897500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
||||
|
|
@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 4223500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3795000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
|
||||
system.physmem.totBankLat 5431250 # Total ticks spent accessing banks
|
||||
system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst
|
||||
system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.49 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.56 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 326 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43363.52 # Average gap between requests
|
||||
system.physmem.avgGap 43105.87 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined
|
||||
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
||||
system.membus.throughput 1467166979 # Throughput (bytes/s)
|
||||
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 15324750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1475906812 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total 25024 # Cu
|
|||
system.membus.data_through_bus 25024 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 2481 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
|
||||
|
|
@ -333,39 +337,39 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 34113 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 33911 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
|
||||
|
|
@ -374,9 +378,9 @@ system.cpu.decode.BranchMispred 159 # Nu
|
|||
system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename
|
||||
|
|
@ -403,23 +407,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
|
||||
|
|
@ -489,10 +493,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
||||
system.cpu.iq.rate 0.261513 # Inst issue rate
|
||||
system.cpu.iq.rate 0.263071 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
|
|
@ -525,43 +529,43 @@ system.cpu.iew.memOrderViolationEvents 21 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.249846 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.251364 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3883 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers 7789 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -572,25 +576,60 @@ system.cpu.commit.branches 1007 # Nu
|
|||
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
||||
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5729 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23225 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 23248 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 23415 # The number of ROB writes
|
||||
system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
||||
system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39210 # number of integer regfile reads
|
||||
system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 39214 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
|
|
@ -605,22 +644,22 @@ system.cpu.toL2Bus.data_through_bus 27904 # To
|
|||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4184 # Number of data accesses
|
||||
|
|
@ -636,12 +675,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n
|
|||
system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 363 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
||||
|
|
@ -654,12 +693,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441
|
|||
system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -680,39 +719,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290
|
|||
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses
|
||||
|
|
@ -736,17 +775,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -769,17 +808,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -805,17 +844,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -827,39 +866,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses
|
||||
system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
|
||||
|
|
@ -876,22 +915,22 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n
|
|||
system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 496 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
|
||||
|
|
@ -902,22 +941,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626
|
|||
system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -944,14 +983,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -960,14 +999,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
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