506 lines
57 KiB
Plaintext
506 lines
57 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.623386 # Number of seconds simulated
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sim_ticks 2623386226000 # Number of ticks simulated
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final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1099630 # Simulator instruction rate (inst/s)
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host_op_rate 1099630 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1585220760 # Simulator tick rate (ticks/s)
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host_mem_usage 265440 # Number of bytes of host memory used
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host_seconds 1654.90 # Real time elapsed on the host
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sim_insts 1819780127 # Number of instructions simulated
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sim_ops 1819780127 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory
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system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 65156928 # Number of bytes written to this memory
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system.physmem.bytes_written::total 65156928 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1958861 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1959663 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 72644797 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
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system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
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system.membus.trans_dist::Writeback 1018077 # Transaction distribution
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system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
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system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 190575360 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
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system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 444595663 # DTB read hits
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system.cpu.dtb.read_misses 4897078 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 449492741 # DTB read accesses
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system.cpu.dtb.write_hits 160728502 # DTB write hits
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system.cpu.dtb.write_misses 1701304 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 162429806 # DTB write accesses
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system.cpu.dtb.data_hits 605324165 # DTB hits
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system.cpu.dtb.data_misses 6598382 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 611922547 # DTB accesses
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system.cpu.itb.fetch_hits 1826378510 # ITB hits
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system.cpu.itb.fetch_misses 18 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 29 # Number of system calls
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system.cpu.numCycles 5246772452 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 1819780127 # Number of instructions committed
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system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
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system.cpu.num_func_calls 33534877 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1725565901 # number of integer instructions
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system.cpu.num_fp_insts 805526 # number of float instructions
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system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
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system.cpu.num_mem_refs 611922547 # number of memory refs
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system.cpu.num_load_insts 449492741 # Number of load instructions
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system.cpu.num_store_insts 162429806 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 5246772452 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 214632552 # Number of branches fetched
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system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
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system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction
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system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
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system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
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system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 1826378509 # Class of executed instruction
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system.cpu.icache.tags.replacements 1 # number of replacements
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system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits
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system.cpu.icache.overall_hits::total 1826377708 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
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system.cpu.icache.overall_misses::total 802 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 1926937 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1059 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 106294313 # Number of data accesses
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system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 3693497 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108019 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1108019 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7152873 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7152873 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7152873 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7152873 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1177560 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1178362 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 781301 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 781301 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1958861 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1959663 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3693497 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3693497 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163042 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.163135 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413536 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413536 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214982 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.215051 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1018077 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1018077 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177560 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1178362 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781301 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 781301 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958861 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1959663 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413536 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413536 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1238 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3693497 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
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|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
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|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s)
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|
system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution
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|
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
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|
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
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|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes)
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|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
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|
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---------- End Simulation Statistics ----------
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