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This commit is contained in:
Ali Saidi 2013-01-07 13:05:54 -05:00
parent 009970f59b
commit 9f15510c2c
103 changed files with 13779 additions and 13811 deletions
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57
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -12,14 +12,15 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
console=/projects/pd/randd/dist/binaries/console
console=/gem5/dist/binaries/console
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux
kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
pal=/projects/pd/randd/dist/binaries/ts_osfpal
pal=/gem5/dist/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@ -71,7 +72,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -131,6 +131,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
@ -147,21 +148,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@ -441,21 +437,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@ -502,7 +493,6 @@ cpu_id=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -562,6 +552,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
@ -578,21 +569,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@ -872,21 +858,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@ -922,7 +903,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -942,7 +923,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -962,30 +943,25 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
type=BaseCache
addr_ranges=0:8589934591
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
mem_side=system.membus.slave[1]
mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
@ -994,25 +970,20 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@ -1024,7 +995,7 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@ -1077,7 +1048,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -1164,7 +1135,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
clock=0
clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false

8
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:02:14
gem5 started Oct 30 2012 13:40:49
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:09:21
gem5 started Jan 4 2013 21:41:13
gem5 executing on u200540
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
info: kernel located at: /gem5/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 107840000

214
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.897858 # Nu
sim_ticks 1897857556000 # Number of ticks simulated
final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131170 # Simulator instruction rate (inst/s)
host_op_rate 131170 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4437782045 # Simulator tick rate (ticks/s)
host_mem_usage 332328 # Number of bytes of host memory used
host_seconds 427.66 # Real time elapsed on the host
host_inst_rate 54087 # Simulator instruction rate (inst/s)
host_op_rate 54087 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1829896991 # Simulator tick rate (ticks/s)
host_mem_usage 335972 # Number of bytes of host memory used
host_seconds 1037.14 # Real time elapsed on the host
sim_insts 56096024 # Number of instructions simulated
sim_ops 56096024 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory
@ -913,8 +913,8 @@ system.cpu0.int_regfile_reads 60234005 # nu
system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes
system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads
system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads
system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes
system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads
system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@ -1065,16 +1065,16 @@ system.cpu0.dcache.overall_misses::cpu0.data 3066244
system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses)
@ -1101,16 +1101,16 @@ system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872
system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked
@ -1145,16 +1145,16 @@ system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427
system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles
@ -1175,16 +1175,16 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707
system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@ -1236,27 +1236,27 @@ system.cpu1.BPredUnit.BTBCorrect 0 # Nu
system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed
system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked
system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total)
@ -1277,21 +1277,21 @@ system.cpu1.decode.BranchMispred 11788 # Nu
system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running
system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename
system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups
system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing
system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer
@ -1415,10 +1415,10 @@ system.cpu1.iew.lsq.thread0.rescheduledLoads 4939
system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking
system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions
@ -1493,23 +1493,23 @@ system.cpu1.int_regfile_reads 17892474 # nu
system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes
system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads
system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes
system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads
system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes
system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads
system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes
system.cpu1.icache.replacements 297472 # number of replacements
system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use
system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks.
system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks.
system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits
system.cpu1.icache.overall_hits::total 1814154 # number of overall hits
system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits
system.cpu1.icache.overall_hits::total 1814153 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses
@ -1522,12 +1522,12 @@ system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496
system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses
@ -1606,32 +1606,32 @@ system.cpu1.dcache.WriteReq_misses::cpu1.data 341345
system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses
system.cpu1.dcache.overall_misses::total 774607 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses
@ -1642,24 +1642,24 @@ system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055
system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked
@ -1692,18 +1692,18 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545
system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles
@ -1716,24 +1716,24 @@ system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency

45
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -12,14 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
console=/projects/pd/randd/dist/binaries/console
console=/gem5/dist/binaries/console
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux
kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
pal=/projects/pd/randd/dist/binaries/ts_osfpal
pal=/gem5/dist/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@ -71,7 +72,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -131,6 +131,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -147,21 +148,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -441,21 +437,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -478,25 +469,20 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
@ -528,7 +514,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -548,7 +534,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -568,30 +554,25 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
type=BaseCache
addr_ranges=0:8589934591
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
mem_side=system.membus.slave[1]
mem_side=system.membus.slave[2]
[system.membus]
type=CoherentBus
@ -603,7 +584,7 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@ -656,7 +637,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -733,7 +714,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
clock=0
clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false

8
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:02:14
gem5 started Oct 30 2012 13:34:06
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:09:21
gem5 started Jan 4 2013 21:39:46
gem5 executing on u200540
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
info: kernel located at: /gem5/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1854349611000 because m5_exit instruction encountered

12
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.854350 # Nu
sim_ticks 1854349611000 # Number of ticks simulated
final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 135035 # Simulator instruction rate (inst/s)
host_op_rate 135035 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4724741522 # Simulator tick rate (ticks/s)
host_mem_usage 327760 # Number of bytes of host memory used
host_seconds 392.48 # Real time elapsed on the host
host_inst_rate 55480 # Simulator instruction rate (inst/s)
host_op_rate 55480 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1941178876 # Simulator tick rate (ticks/s)
host_mem_usage 331452 # Number of bytes of host memory used
host_seconds 955.27 # Real time elapsed on the host
sim_insts 52998188 # Number of instructions simulated
sim_ops 52998188 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory
@ -601,7 +601,7 @@ system.cpu.int_regfile_reads 73962724 # nu
system.cpu.int_regfile_writes 40347354 # number of integer regfile writes
system.cpu.fp_regfile_reads 166024 # number of floating regfile reads
system.cpu.fp_regfile_writes 167429 # number of floating regfile writes
system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads
system.cpu.misc_regfile_reads 1994989 # number of misc regfile reads
system.cpu.misc_regfile_writes 947074 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

83
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@ -65,12 +65,12 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -96,7 +96,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -118,6 +117,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -155,6 +155,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -166,11 +167,10 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.checker]
type=O3Checker
children=dtb itb tracer
children=dtb isa itb tracer
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -179,6 +179,7 @@ exitOnError=false
function_trace=false
function_trace_start=0
interrupts=Null
isa=system.cpu.checker.isa
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -187,6 +188,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.checker.tracer
updateOnError=true
@ -206,6 +208,23 @@ num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.checker.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.checker.itb]
type=ArmTLB
children=walker
@ -229,21 +248,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -532,21 +546,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -555,6 +564,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -575,25 +601,20 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
@ -624,30 +645,25 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
addr_ranges=0:268435455
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[1]
mem_side=system.membus.slave[2]
[system.membus]
type=CoherentBus
@ -659,7 +675,7 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@ -789,11 +805,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]

36
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
View file

@ -10,27 +10,23 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: 5947838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
warn: 5955222500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
warn: 5964126500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 6000836500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 6016396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: LCD dual screen mode not supported
warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: 51807341500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
warn: 2473965329500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
warn: 2487749656500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2488961741500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
warn: 2510016165000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2510533208500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2516263747000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
warn: 2516773890500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
warn: 2517336143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
warn: 2517337246000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
warn: 2517887293500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
hack: be nice to actually delete the event here

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 1 2012 15:18:10
gem5 started Nov 2 2012 01:09:00
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 01:50:21
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2523500318000 because m5_exit instruction encountered
Exiting @ tick 2523517846500 because m5_exit instruction encountered

1700
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

File diff suppressed because it is too large Load diff

93
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@ -65,12 +65,12 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
children=dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -96,7 +96,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -118,6 +117,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
@ -155,6 +155,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
@ -171,21 +172,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@ -474,21 +470,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@ -497,6 +488,23 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=ArmInterrupts
[system.cpu0.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu0.itb]
type=ArmTLB
children=walker
@ -515,7 +523,7 @@ type=ExeTracer
[system.cpu1]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
children=dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -541,7 +549,6 @@ cpu_id=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -563,6 +570,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
@ -600,6 +608,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
@ -616,21 +625,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@ -919,21 +923,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@ -942,6 +941,23 @@ mem_side=system.toL2Bus.slave[4]
[system.cpu1.interrupts]
type=ArmInterrupts
[system.cpu1.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu1.itb]
type=ArmTLB
children=walker
@ -974,30 +990,25 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
addr_ranges=0:268435455
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[1]
mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
@ -1006,25 +1017,20 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@ -1036,7 +1042,7 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@ -1166,11 +1172,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
View file

@ -12,8 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 21:14:52
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 02:00:26
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2593146078000 because m5_exit instruction encountered
Exiting @ tick 2603185215000 because m5_exit instruction encountered

3118
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

61
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@ -65,12 +65,12 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -96,7 +96,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -118,6 +117,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -155,6 +155,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -171,21 +172,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -474,21 +470,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -497,6 +488,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -517,25 +525,20 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
@ -566,30 +569,25 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
addr_ranges=0:268435455
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[1]
mem_side=system.membus.slave[2]
[system.membus]
type=CoherentBus
@ -601,7 +599,7 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@ -731,11 +729,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
View file

@ -11,8 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 21:11:31
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 01:42:51
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2523500318000 because m5_exit instruction encountered
Exiting @ tick 2523517846500 because m5_exit instruction encountered

1674
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@ -19,16 +19,14 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
@ -67,7 +65,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 11 2012 16:28:23
gem5 started Dec 11 2012 16:28:35
gem5 executing on e103721-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 02:09:50
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...

36
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
View file

@ -4,13 +4,25 @@ sim_seconds 2.401421 # Nu
sim_ticks 2401421439000 # Number of ticks simulated
final_tick 2401421439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 170882 # Simulator instruction rate (inst/s)
host_op_rate 219406 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6786575645 # Simulator tick rate (ticks/s)
host_mem_usage 393972 # Number of bytes of host memory used
host_seconds 353.85 # Real time elapsed on the host
host_inst_rate 75201 # Simulator instruction rate (inst/s)
host_op_rate 96555 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2986582566 # Simulator tick rate (ticks/s)
host_mem_usage 393856 # Number of bytes of host memory used
host_seconds 804.07 # Real time elapsed on the host
sim_insts 60466509 # Number of instructions simulated
sim_ops 77636591 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
@ -245,18 +257,6 @@ system.physmem.writeRowHits 499132 # Nu
system.physmem.readRowHitRate 99.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.24 # Row buffer hit rate for writes
system.physmem.avgGap 182850.04 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 63371 # number of replacements
system.l2c.tagsinuse 50440.930838 # Cycle average of tags in use
system.l2c.total_refs 1764263 # Total number of references to valid blocks.
@ -1541,7 +1541,7 @@ system.cpu2.int_regfile_reads 159046643 # nu
system.cpu2.int_regfile_writes 30194860 # number of integer regfile writes
system.cpu2.fp_regfile_reads 22317 # number of floating regfile reads
system.cpu2.fp_regfile_writes 20822 # number of floating regfile writes
system.cpu2.misc_regfile_reads 41979427 # number of misc regfile reads
system.cpu2.misc_regfile_reads 9419199 # number of misc regfile reads
system.cpu2.misc_regfile_writes 278833 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@ -19,16 +19,14 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
@ -67,7 +65,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 11 2012 16:28:23
gem5 started Dec 11 2012 16:28:35
gem5 executing on e103721-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 02:15:48
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...

38
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
View file

@ -4,13 +4,25 @@ sim_seconds 2.540587 # Nu
sim_ticks 2540587123500 # Number of ticks simulated
final_tick 2540587123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 67374 # Simulator instruction rate (inst/s)
host_op_rate 86663 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2824409714 # Simulator tick rate (ticks/s)
host_mem_usage 407052 # Number of bytes of host memory used
host_seconds 899.51 # Real time elapsed on the host
host_inst_rate 28859 # Simulator instruction rate (inst/s)
host_op_rate 37121 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1209803028 # Simulator tick rate (ticks/s)
host_mem_usage 406188 # Number of bytes of host memory used
host_seconds 2100.00 # Real time elapsed on the host
sim_insts 60603607 # Number of instructions simulated
sim_ops 77954043 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
@ -224,18 +236,6 @@ system.physmem.writeRowHits 786076 # Nu
system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.67 # Row buffer hit rate for writes
system.physmem.avgGap 157735.86 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 64360 # number of replacements
system.l2c.tagsinuse 51403.610979 # Cycle average of tags in use
system.l2c.total_refs 1940230 # Total number of references to valid blocks.
@ -964,7 +964,7 @@ system.cpu0.int_regfile_reads 285784738 # nu
system.cpu0.int_regfile_writes 46365180 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22828 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19904 # number of floating regfile writes
system.cpu0.misc_regfile_reads 64493667 # number of misc regfile reads
system.cpu0.misc_regfile_reads 16064067 # number of misc regfile reads
system.cpu0.misc_regfile_writes 471303 # number of misc regfile writes
system.cpu0.icache.replacements 986601 # number of replacements
system.cpu0.icache.tagsinuse 511.585602 # Cycle average of tags in use
@ -1651,7 +1651,7 @@ system.cpu1.int_regfile_reads 264545362 # nu
system.cpu1.int_regfile_writes 41743183 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22037 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19620 # number of floating regfile writes
system.cpu1.misc_regfile_reads 56567930 # number of misc regfile reads
system.cpu1.misc_regfile_reads 14602821 # number of misc regfile reads
system.cpu1.misc_regfile_writes 442325 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use

47
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -16,9 +16,10 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
kernel=/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
readfile=tests/halt.sh
@ -98,7 +99,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -158,6 +158,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -174,21 +175,16 @@ assoc=4
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -213,21 +209,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dtb.walker.port
@ -503,21 +494,16 @@ assoc=1
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -530,7 +516,7 @@ int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
system=system
int_master=system.membus.slave[4]
int_master=system.membus.slave[3]
int_slave=system.membus.master[3]
pio=system.membus.master[2]
@ -556,21 +542,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.itb.walker.port
@ -583,25 +564,20 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[3]
mem_side=system.membus.slave[2]
[system.cpu.toL2Bus]
type=CoherentBus
@ -997,25 +973,20 @@ assoc=8
block_size=64
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[18]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[4]
[system.membus]
type=CoherentBus
@ -1027,7 +998,7 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@ -1297,7 +1268,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-x86.img
image_file=/gem5/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1317,7 +1288,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

10
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,13 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:14:29
gem5 started Oct 30 2012 18:26:17
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:20:54
gem5 started Jan 4 2013 23:13:25
gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5132789913000 because m5_exit instruction encountered
Exiting @ tick 5136797077000 because m5_exit instruction encountered

1942
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

42
tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/gem5/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

6
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 18:59:47
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:34:09
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

490
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.164568 # Nu
sim_ticks 164568389500 # Number of ticks simulated
final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 195675 # Simulator instruction rate (inst/s)
host_op_rate 206765 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56489453 # Simulator tick rate (ticks/s)
host_mem_usage 277972 # Number of bytes of host memory used
host_seconds 2913.26 # Real time elapsed on the host
host_inst_rate 61098 # Simulator instruction rate (inst/s)
host_op_rate 64561 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17638362 # Simulator tick rate (ticks/s)
host_mem_usage 233000 # Number of bytes of host memory used
host_seconds 9330.14 # Real time elapsed on the host
sim_insts 570052720 # Number of instructions simulated
sim_ops 602360926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 164 # Tr
system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 164568371500 # Total gap between requests
system.physmem.totGap 164568372500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 953340995 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1657962995 # Sum of mem lat for all requests
system.physmem.totQLat 953339495 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1657961495 # Sum of mem lat for all requests
system.physmem.totBusLat 109328000 # Total cycles spent in databus access
system.physmem.totBankLat 595294000 # Total cycles spent in bank access
system.physmem.avgQLat 34880.03 # Average queueing delay per request
system.physmem.avgQLat 34879.98 # Average queueing delay per request
system.physmem.avgBankLat 21780.11 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 60660.14 # Average memory access latency
system.physmem.avgMemAccLat 60660.09 # Average memory access latency
system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s
@ -191,7 +191,7 @@ system.physmem.readRowHits 17765 # Nu
system.physmem.writeRowHits 1091 # Number of row buffer hits during writes
system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes
system.physmem.avgGap 5509671.28 # Average gap between requests
system.physmem.avgGap 5509671.31 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 46871026 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 68501011 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 68501012 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 119329475 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 119329476 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 67084220 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 755001 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 328178874 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 67084221 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 755002 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 328178875 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 198558185 60.50% 60.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 198558186 60.50% 60.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total)
@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 328178874 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 328178875 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96199178 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 96199179 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing
@ -290,19 +290,19 @@ system.cpu.rename.SquashCycles 10725676 # Nu
system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 114043084 # Number of cycles rename is running
system.cpu.rename.RunCycles 114043085 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 694816427 # Number of instructions processed by rename
system.cpu.rename.RenamedInsts 694816428 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 721301804 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3230529001 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3230528873 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 721301805 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3230529005 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3230528877 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 93882615 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 93882616 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer
@ -317,11 +317,11 @@ system.cpu.iq.iqSquashedInstsIssued 1370428 # Nu
system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 328178874 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 328178875 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 68164683 20.77% 20.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 68164684 20.77% 20.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle
@ -333,7 +333,7 @@ system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 328178874 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 328178875 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available
@ -406,7 +406,7 @@ system.cpu.iq.FU_type_0::total 645601186 # Ty
system.cpu.iq.rate 1.961498 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1624523748 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 1624523749 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
@ -429,7 +429,7 @@ system.cpu.iew.iewSquashCycles 10725676 # Nu
system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 690727 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 690728 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions
@ -491,7 +491,7 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 977035801 # The number of ROB reads
system.cpu.rob.rob_writes 1370761733 # The number of ROB writes
system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 957906 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 957905 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 570052720 # Number of Instructions Simulated
system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated
@ -519,36 +519,36 @@ system.cpu.icache.demand_hits::cpu.inst 67083066 # nu
system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits
system.cpu.icache.overall_hits::total 67083066 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses
system.cpu.icache.overall_misses::total 1154 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 51351999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 51351999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 51351999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 51351999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 51351999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 51351999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 67084220 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 67084220 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 67084220 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 67084220 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 67084220 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 67084220 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 1155 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1155 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1155 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1155 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1155 # number of overall misses
system.cpu.icache.overall_misses::total 1155 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 51421999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 51421999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 51421999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 51421999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 51421999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 51421999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 67084221 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 67084221 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 67084221 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 67084221 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 67084221 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 67084221 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44499.132582 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44499.132582 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44499.132582 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44499.132582 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44521.211255 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44521.211255 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44521.211255 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44521.211255 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
@ -557,37 +557,184 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 335 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 335 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 335 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 335 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 335 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38657999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 38657999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38657999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 38657999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38657999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38657999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38656999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 38656999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38656999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 38656999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38656999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38656999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47143.901220 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47143.901220 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47142.681707 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47142.681707 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2559 # number of replacements
system.cpu.l2cache.tagsinuse 22365.188888 # Cycle average of tags in use
system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 646.825199 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.633652 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.019740 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.029140 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.682531 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 81 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 192805 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 192886 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 421636 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 421636 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 225369 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 225369 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 81 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 418174 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 418255 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 81 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 418174 # number of overall hits
system.cpu.l2cache.overall_hits::total 418255 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 739 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4814 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5553 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21790 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21790 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 739 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26604 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 27343 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 739 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26604 # number of overall misses
system.cpu.l2cache.overall_misses::total 27343 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37000500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728777500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 765778000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1545376500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 37000500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2274154000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2311154500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 37000500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2274154000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2311154500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 197619 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 198439 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 421636 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 421636 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247159 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247159 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 444778 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 445598 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 444778 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 445598 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.027983 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.088162 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.901220 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.059814 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.061362 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.100125 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.475599 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.363011 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.363011 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 84524.540102 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84524.540102 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.writebacks::total 2537 # number of writebacks
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system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
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system.cpu.l2cache.ReadExReq_mshr_misses::total 21790 # number of ReadExReq MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.data 26596 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27332 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668139562 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273791296 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941930858 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1969273031 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024320 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139021.964628 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.608811 # average ReadExReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency
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system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use
system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks.
@ -619,16 +766,16 @@ system.cpu.dcache.demand_misses::cpu.data 3714801 # n
system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses
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system.cpu.dcache.WriteReq_miss_latency::total 40250551202 # number of WriteReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 5159649500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 40250552202 # number of WriteReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 45410202202 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 45410201702 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 45410201702 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 45410201702 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
@ -651,16 +798,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.018456
system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses
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system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.924972 # average WriteReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 12224.127673 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12224.127673 # average overall miss latency
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system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked
@ -689,10 +836,10 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 444778
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles
@ -705,161 +852,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210
system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.143266 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.631998 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.631998 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2559 # number of replacements
system.cpu.l2cache.tagsinuse 22365.188889 # Cycle average of tags in use
system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 646.825200 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84524.576674 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2537 # number of writebacks
system.cpu.l2cache.writebacks::total 2537 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 736 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4806 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5542 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21790 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21790 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 736 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26596 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27332 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26596 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27332 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342673 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668140562 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695483235 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273790796 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273790796 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342673 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941931358 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1969274031 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342673 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941931358 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1969274031 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024320 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027928 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088162 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088162 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061338 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061338 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37150.370924 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139022.172701 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125493.185673 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.585865 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.585865 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

22
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -116,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -132,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -426,21 +422,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -463,21 +454,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -504,7 +490,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864

8
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:11:57
gem5 started Oct 30 2012 14:00:44
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:16:54
gem5 started Jan 4 2013 22:00:02
gem5 executing on u200540
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 387281648500 because target called exit()
Exiting @ tick 387279743500 because target called exit()

1056
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

28
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -433,21 +430,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -464,6 +456,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
@ -483,21 +478,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -524,7 +514,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864

8
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18
gem5 started Dec 30 2012 00:35:30
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jan 4 2013 21:20:54
gem5 started Jan 4 2013 22:11:32
gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

408
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.607446 # Nu
sim_ticks 607445544000 # Number of ticks simulated
final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 57635 # Simulator instruction rate (inst/s)
host_op_rate 106195 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 39782943 # Simulator tick rate (ticks/s)
host_mem_usage 279268 # Number of bytes of host memory used
host_seconds 15268.99 # Real time elapsed on the host
host_inst_rate 35384 # Simulator instruction rate (inst/s)
host_op_rate 65197 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 24424271 # Simulator tick rate (ticks/s)
host_mem_usage 239876 # Number of bytes of host memory used
host_seconds 24870.57 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 156 # Tr
system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 607445529000 # Total gap between requests
system.physmem.totGap 607445530000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 68456169 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 822256169 # Sum of mem lat for all requests
system.physmem.totQLat 68456669 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 822256669 # Sum of mem lat for all requests
system.physmem.totBusLat 109436000 # Total cycles spent in databus access
system.physmem.totBankLat 644364000 # Total cycles spent in bank access
system.physmem.avgQLat 2502.14 # Average queueing delay per request
system.physmem.avgQLat 2502.16 # Average queueing delay per request
system.physmem.avgBankLat 23552.18 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 30054.32 # Average memory access latency
system.physmem.avgMemAccLat 30054.34 # Average memory access latency
system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
@ -191,7 +191,7 @@ system.physmem.readRowHits 17697 # Nu
system.physmem.writeRowHits 1084 # Number of row buffer hits during writes
system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes
system.physmem.avgGap 20320661.33 # Average gap between requests
system.physmem.avgGap 20320661.36 # Average gap between requests
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1214891089 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -204,22 +204,22 @@ system.cpu.BPredUnit.BTBHits 84079165 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 179135724 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed
system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 574634439 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 574634441 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 187842502 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11743850 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1214538068 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 187842503 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11743851 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1214538070 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 822675210 67.74% 67.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 822675212 67.74% 67.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total)
@ -231,18 +231,18 @@ system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1214538068 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1214538070 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 497953946 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 497953948 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 124143934 # Number of cycles rename is blocking
system.cpu.rename.BlockCycles 124143936 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking
@ -270,11 +270,11 @@ system.cpu.iq.iqSquashedInstsIssued 243450 # Nu
system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 239 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1214538068 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 1214538070 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.468938 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.421549 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 360345167 29.67% 29.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 360345169 29.67% 29.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle
@ -286,7 +286,7 @@ system.cpu.iq.issued_per_cycle::8 597279 0.05% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1214538068 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1214538070 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 15.09% # attempts to use FU when none available
@ -359,7 +359,7 @@ system.cpu.iq.FU_type_0::total 1784080761 # Ty
system.cpu.iq.rate 1.468511 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4785843295 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 4785843297 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads
@ -379,7 +379,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 2481 #
system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1142263 # Number of cycles IEW is blocking
system.cpu.iew.iewBlockCycles 1142265 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch
@ -412,11 +412,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1152851075 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 1152851077 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 418199685 36.28% 36.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 418199687 36.28% 36.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle
@ -428,7 +428,7 @@ system.cpu.commit.committed_per_cycle::8 32432091 2.81% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1152851075 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1152851077 # Number of insts commited each cycle
system.cpu.commit.committedInsts 880025277 # Number of instructions committed
system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -441,10 +441,10 @@ system.cpu.commit.int_insts 1621354437 # Nu
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3114927127 # The number of ROB reads
system.cpu.rob.rob_reads 3114927129 # The number of ROB reads
system.cpu.rob.rob_writes 4050738571 # The number of ROB writes
system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 353021 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 353019 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
@ -471,36 +471,36 @@ system.cpu.icache.demand_hits::cpu.inst 187841119 # nu
system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 187841119 # number of overall hits
system.cpu.icache.overall_hits::total 187841119 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses
system.cpu.icache.overall_misses::total 1383 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64282500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 64282500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 64282500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 64282500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 64282500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 64282500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 187842502 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 187842502 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 187842502 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 187842502 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 187842502 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 187842502 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 1384 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1384 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1384 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1384 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1384 # number of overall misses
system.cpu.icache.overall_misses::total 1384 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64353500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 64353500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 64353500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 64353500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 64353500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 64353500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 187842503 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 187842503 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 187842503 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 187842503 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 187842503 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 187842503 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46480.477223 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 46480.477223 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 46480.477223 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 46480.477223 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46498.193642 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 46498.193642 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 46498.193642 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 46498.193642 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
@ -509,12 +509,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 40.600000
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 466 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 466 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 466 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 466 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 466 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 466 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 918 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 918 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 918 # number of demand (read+write) MSHR misses
@ -540,114 +540,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50259.259259
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 446019 # number of replacements
system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use
system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 452395597 # number of overall hits
system.cpu.dcache.overall_hits::total 452395597 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 211135 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 211135 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 246434 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 246434 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 457569 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 457569 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 457569 # number of overall misses
system.cpu.dcache.overall_misses::total 457569 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3016076500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3016076500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063848999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4063848999 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7079925499 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7079925499 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7079925499 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7079925499 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.061690 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.061690 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.618174 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.618174 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15472.913373 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15472.913373 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks
system.cpu.dcache.writebacks::total 428963 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523541000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523541000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570237499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570237499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6093778499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6093778499 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.018570 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.018570 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.541096 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.541096 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2556 # number of replacements
system.cpu.l2cache.tagsinuse 22259.528577 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531228 # Total number of references to valid blocks.
@ -655,7 +547,7 @@ system.cpu.l2cache.sampled_refs 24191 # Sa
system.cpu.l2cache.avg_refs 21.959737 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20782.488903 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 799.212801 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 799.212802 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 677.826873 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.634231 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.024390 # Average percentage of cache occupancy
@ -688,16 +580,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 902 #
system.cpu.l2cache.overall_misses::cpu.data 26457 # number of overall misses
system.cpu.l2cache.overall_misses::total 27359 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45120000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 370939500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079318500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1079318500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 370939000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079319500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1079319500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45120000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1405138000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1450258000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1405138500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1450258500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45120000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1405138000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1450258000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1405138500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1450258500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 203769 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 204679 # number of ReadReq accesses(hits+misses)
@ -725,16 +617,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991209
system.cpu.l2cache.overall_miss_rate::cpu.data 0.058778 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060659 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50022.172949 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.644737 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.760893 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.701923 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.701923 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.535088 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.669352 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.747591 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.747591 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 53008.443291 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 53008.461567 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 53008.443291 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 53008.461567 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -756,16 +648,16 @@ system.cpu.l2cache.demand_mshr_misses::total 27359
system.cpu.l2cache.overall_mshr_misses::cpu.inst 902 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26457 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33761933 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267685448 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301447381 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 796656102 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 796656102 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33761933 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064341550 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33761433 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267684948 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301446381 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 796657102 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 796657102 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33761433 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064342050 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1098103483 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761933 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064341550 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761433 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064342050 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1098103483 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022378 # mshr miss rate for ReadReq accesses
@ -778,17 +670,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.060659
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058778 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060659 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37430.080931 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.949123 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.926950 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36381.974791 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36381.974791 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37429.526608 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.839474 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.743867 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36382.020459 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36382.020459 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 446019 # number of replacements
system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use
system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 452395597 # number of overall hits
system.cpu.dcache.overall_hits::total 452395597 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 211135 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 211135 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 246434 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 246434 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 457569 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 457569 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 457569 # number of overall misses
system.cpu.dcache.overall_misses::total 457569 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3016076000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3016076000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063849999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4063849999 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7079925999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7079925999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7079925999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7079925999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.059322 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.059322 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.622232 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.622232 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15472.914465 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15472.914465 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks
system.cpu.dcache.writebacks::total 428963 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523540500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523540500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570238499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570238499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6093778999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6093778999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.016116 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.016116 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.545155 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.545155 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

44
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,9 +522,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
executable=/gem5/dist/cpu2000/binaries/arm/linux/mcf
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

6
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 19:23:29
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:47:37
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

424
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.026786 # Nu
sim_ticks 26786364500 # Number of ticks simulated
final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 184396 # Simulator instruction rate (inst/s)
host_op_rate 185720 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 54518089 # Simulator tick rate (ticks/s)
host_mem_usage 410024 # Number of bytes of host memory used
host_seconds 491.33 # Real time elapsed on the host
host_inst_rate 55091 # Simulator instruction rate (inst/s)
host_op_rate 55487 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16288150 # Simulator tick rate (ticks/s)
host_mem_usage 365372 # Number of bytes of host memory used
host_seconds 1644.53 # Real time elapsed on the host
sim_insts 90599358 # Number of instructions simulated
sim_ops 91249911 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 26786185500 # Total gap between requests
system.physmem.totGap 26786186500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 45050979 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests
system.physmem.totQLat 45051479 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests
system.physmem.totBusLat 62048000 # Total cycles spent in databus access
system.physmem.totBankLat 172004000 # Total cycles spent in bank access
system.physmem.avgQLat 2904.27 # Average queueing delay per request
system.physmem.avgQLat 2904.30 # Average queueing delay per request
system.physmem.avgBankLat 11088.45 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 17992.71 # Average memory access latency
system.physmem.avgMemAccLat 17992.75 # Average memory access latency
system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s
@ -184,7 +184,7 @@ system.physmem.readRowHits 15087 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 1726804.12 # Average gap between requests
system.physmem.avgGap 1726804.18 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -239,23 +239,23 @@ system.cpu.BPredUnit.BTBHits 11281654 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed
system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total)
@ -267,11 +267,11 @@ system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing
@ -283,19 +283,19 @@ system.cpu.rename.SquashCycles 3892391 # Nu
system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running
system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename
system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer
@ -310,11 +310,11 @@ system.cpu.iq.iqSquashedInstsIssued 79722 # Nu
system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle
@ -326,7 +326,7 @@ system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available
@ -399,7 +399,7 @@ system.cpu.iq.FU_type_0::total 105160593 # Ty
system.cpu.iq.rate 1.962950 # Inst issue rate
system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads
@ -422,7 +422,7 @@ system.cpu.iew.iewSquashCycles 3892391 # Nu
system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions
@ -484,7 +484,7 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 162359257 # The number of ROB reads
system.cpu.rob.rob_writes 240263976 # The number of ROB writes
system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90599358 # Number of Instructions Simulated
system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated
@ -513,36 +513,36 @@ system.cpu.icache.demand_hits::cpu.inst 13840965 # nu
system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits
system.cpu.icache.overall_hits::total 13840965 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
system.cpu.icache.overall_misses::total 983 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
system.cpu.icache.overall_misses::total 984 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
@ -551,12 +551,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses
@ -582,132 +582,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943495 # number of replacements
system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
system.cpu.dcache.writebacks::total 942892 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks.
@ -750,16 +624,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 708 #
system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses
system.cpu.l2cache.overall_misses::total 15523 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses)
@ -789,16 +663,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963265
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -829,19 +703,19 @@ system.cpu.l2cache.demand_mshr_misses::total 15512
system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses
@ -855,19 +729,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943495 # number of replacements
system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
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system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
system.cpu.dcache.writebacks::total 942892 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

30
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -433,21 +430,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -464,6 +456,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
@ -483,21 +478,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -524,9 +514,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
executable=/gem5/dist/cpu2000/binaries/x86/linux/mcf
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18
gem5 started Dec 30 2012 00:35:30
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jan 4 2013 21:20:54
gem5 started Jan 4 2013 22:18:55
gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

410
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.065983 # Nu
sim_ticks 65982862500 # Number of ticks simulated
final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 71115 # Simulator instruction rate (inst/s)
host_op_rate 125222 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29700736 # Simulator tick rate (ticks/s)
host_mem_usage 413360 # Number of bytes of host memory used
host_seconds 2221.59 # Real time elapsed on the host
host_inst_rate 39069 # Simulator instruction rate (inst/s)
host_op_rate 68794 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16316772 # Simulator tick rate (ticks/s)
host_mem_usage 376348 # Number of bytes of host memory used
host_seconds 4043.87 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 65982842000 # Total gap between requests
system.physmem.totGap 65982843000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 10444357 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests
system.physmem.totQLat 10445857 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests
system.physmem.totBusLat 121544000 # Total cycles spent in databus access
system.physmem.totBankLat 439614000 # Total cycles spent in bank access
system.physmem.avgQLat 343.72 # Average queueing delay per request
system.physmem.avgQLat 343.77 # Average queueing delay per request
system.physmem.avgBankLat 14467.65 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 18811.37 # Average memory access latency
system.physmem.avgMemAccLat 18811.42 # Average memory access latency
system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s
@ -191,7 +191,7 @@ system.physmem.readRowHits 29640 # Nu
system.physmem.writeRowHits 45 # Number of row buffer hits during writes
system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
system.physmem.avgGap 2155034.36 # Average gap between requests
system.physmem.avgGap 2155034.39 # Average gap between requests
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 131965726 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -204,18 +204,18 @@ system.cpu.BPredUnit.BTBHits 24642661 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed
system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total)
@ -460,12 +460,12 @@ system.cpu.fp_regfile_reads 138 # nu
system.cpu.fp_regfile_writes 78 # number of floating regfile writes
system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads
system.cpu.icache.replacements 68 # number of replacements
system.cpu.icache.tagsinuse 836.141366 # Cycle average of tags in use
system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use
system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits
@ -474,36 +474,36 @@ system.cpu.icache.demand_hits::cpu.inst 25950700 # nu
system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits
system.cpu.icache.overall_hits::total 25950700 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1350 # number of overall misses
system.cpu.icache.overall_misses::total 1350 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 65277000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 65277000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 65277000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 65277000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 65277000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 65277000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25952050 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25952050 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25952050 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25952050 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25952050 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses
system.cpu.icache.overall_misses::total 1351 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48353.333333 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48353.333333 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
@ -512,153 +512,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2072071 # number of replacements
system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use
system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits
system.cpu.dcache.overall_hits::total 71946748 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses
system.cpu.dcache.overall_misses::total 2723462 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321024000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 31321024000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 33409132498 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 33409132498 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 33409132498 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 33409132498 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks
system.cpu.dcache.writebacks::total 2066432 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

44
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,9 +522,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/gem5/dist/cpu2000/binaries/arm/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

1
tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
View file

@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
hack: be nice to actually delete the event here

8
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 19:35:49
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:51:04
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 206019870500 because target called exit()
Exiting @ tick 206006891000 because target called exit()

1338
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

30
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -433,21 +430,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -464,6 +456,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
@ -483,21 +478,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -524,9 +514,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
executable=/gem5/dist/cpu2000/binaries/x86/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18
gem5 started Dec 30 2012 01:06:22
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jan 4 2013 21:20:54
gem5 started Jan 4 2013 22:32:47
gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

482
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.434475 # Nu
sim_ticks 434474519000 # Number of ticks simulated
final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 64407 # Simulator instruction rate (inst/s)
host_op_rate 119096 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33842135 # Simulator tick rate (ticks/s)
host_mem_usage 385848 # Number of bytes of host memory used
host_seconds 12838.27 # Real time elapsed on the host
host_inst_rate 38128 # Simulator instruction rate (inst/s)
host_op_rate 70503 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20033995 # Simulator tick rate (ticks/s)
host_mem_usage 425632 # Number of bytes of host memory used
host_seconds 21686.86 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 18336 # Tr
system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 434474501000 # Total gap between requests
system.physmem.totGap 434474502000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 380876 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4272 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 53 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 380877 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4271 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 383 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 3519471180 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11592783180 # Sum of mem lat for all requests
system.physmem.totQLat 3519643685 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11592955685 # Sum of mem lat for all requests
system.physmem.totBusLat 1542368000 # Total cycles spent in databus access
system.physmem.totBankLat 6530944000 # Total cycles spent in bank access
system.physmem.avgQLat 9127.45 # Average queueing delay per request
system.physmem.avgQLat 9127.90 # Average queueing delay per request
system.physmem.avgBankLat 16937.45 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 30064.90 # Average memory access latency
system.physmem.avgMemAccLat 30065.34 # Average memory access latency
system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s
@ -204,23 +204,23 @@ system.cpu.BPredUnit.BTBHits 147901505 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 180614780 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed
system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 232782957 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33410 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 232782979 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 173495456 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3828583 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 855065189 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 173495457 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3828584 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 855065277 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.388123 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.388122 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 488192448 57.09% 57.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 488192536 57.09% 57.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total)
@ -232,19 +232,19 @@ system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 855065189 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 855065277 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 236982201 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 189423350 # Number of cycles decode is blocked
system.cpu.decode.IdleCycles 236982267 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 189423372 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 270449019 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 55242457 # Number of cycles rename is blocking
system.cpu.rename.IdleCycles 270449085 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 55242479 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking
@ -273,23 +273,23 @@ system.cpu.iq.iqSquashedInstsIssued 844321 # Nu
system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 855065189 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 855065277 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 234637640 27.44% 27.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 145403734 17.00% 44.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 138360213 16.18% 60.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 132907886 15.54% 76.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 234637728 27.44% 27.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 145403732 17.00% 44.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 138360216 16.18% 60.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 132907885 15.54% 76.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 58823756 6.88% 94.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 34984723 4.09% 98.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 58823757 6.88% 94.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 34984722 4.09% 98.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 855065189 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 855065277 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available
@ -362,7 +362,7 @@ system.cpu.iq.FU_type_0::total 1808313369 # Ty
system.cpu.iq.rate 2.081035 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4487818661 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 4487818749 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads
@ -407,7 +407,7 @@ system.cpu.iew.exec_rate 2.049103 # In
system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1341647639 # num instructions producing a value
system.cpu.iew.wb_consumers 1964496611 # num instructions consuming a value
system.cpu.iew.wb_consumers 1964496615 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back
@ -415,23 +415,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 785035213 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 785035301 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 291749690 37.16% 37.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 195656651 24.92% 62.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 62029976 7.90% 69.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 291749780 37.16% 37.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 195656650 24.92% 62.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 62029975 7.90% 69.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25075018 3.19% 84.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25075017 3.19% 84.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10844976 1.38% 91.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10844977 1.38% 91.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 785035213 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 785035301 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -444,10 +444,10 @@ system.cpu.commit.int_insts 1528317559 # Nu
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2749272836 # The number of ROB reads
system.cpu.rob.rob_reads 2749272924 # The number of ROB reads
system.cpu.rob.rob_writes 4138465929 # The number of ROB writes
system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13883850 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 13883762 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
@ -461,50 +461,50 @@ system.cpu.fp_regfile_reads 5173 # nu
system.cpu.fp_regfile_writes 5 # number of floating regfile writes
system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads
system.cpu.icache.replacements 5393 # number of replacements
system.cpu.icache.tagsinuse 1034.711161 # Cycle average of tags in use
system.cpu.icache.total_refs 173255659 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1034.711169 # Cycle average of tags in use
system.cpu.icache.total_refs 173255660 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 24803.959771 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 24803.959914 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1034.711161 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1034.711169 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 173271213 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173271213 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173271213 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173271213 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173271213 # number of overall hits
system.cpu.icache.overall_hits::total 173271213 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 173271214 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173271214 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173271214 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173271214 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173271214 # number of overall hits
system.cpu.icache.overall_hits::total 173271214 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses
system.cpu.icache.overall_misses::total 224243 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1407047499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1407047499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1407047499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1407047499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1407047499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1407047499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 173495456 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173495456 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173495456 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173495456 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173495456 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173495456 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1406797999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1406797999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1406797999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1406797999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1406797999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1406797999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 173495457 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173495457 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173495457 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173495457 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173495457 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173495457 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6274.655169 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6274.655169 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6274.655169 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6274.655169 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6273.542536 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6273.542536 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6273.542536 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6273.542536 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
@ -525,142 +525,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 221942
system.cpu.icache.demand_mshr_misses::total 221942 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 221942 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 221942 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897816999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 897816999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897816999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 897816999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897816999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 897816999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897728499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 897728499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897728499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 897728499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897728499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 897728499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001279 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001279 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for overall accesses
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4044.878838 # average overall mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.286024 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.286024 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2529684 # number of replacements
system.cpu.dcache.tagsinuse 4087.842112 # Cycle average of tags in use
system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.842112 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits
system.cpu.dcache.overall_hits::total 404771823 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses
system.cpu.dcache.overall_misses::total 3896832 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112721500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 50112721500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443408500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 24443408500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 74556130000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 74556130000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 74556130000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 74556130000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17316.051222 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17316.051222 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.477478 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.477478 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19132.497885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19132.497885 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks
system.cpu.dcache.writebacks::total 2331225 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924834500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924834500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273976000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273976000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198810500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 49198810500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198810500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 49198810500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.158497 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.158497 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.506223 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.506223 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

42
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
executable=/gem5/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

6
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 19:45:28
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 00:06:54
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

396
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.068267 # Nu
sim_ticks 68267465500 # Number of ticks simulated
final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 160764 # Simulator instruction rate (inst/s)
host_op_rate 205527 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40194170 # Simulator tick rate (ticks/s)
host_mem_usage 285344 # Number of bytes of host memory used
host_seconds 1698.44 # Real time elapsed on the host
host_inst_rate 47859 # Simulator instruction rate (inst/s)
host_op_rate 61184 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11965597 # Simulator tick rate (ticks/s)
host_mem_usage 240720 # Number of bytes of host memory used
host_seconds 5705.31 # Real time elapsed on the host
sim_insts 273048375 # Number of instructions simulated
sim_ops 349076099 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 68267282000 # Total gap between requests
system.physmem.totGap 68267283000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -184,7 +184,7 @@ system.physmem.readRowHits 6392 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 9355527.20 # Average gap between requests
system.physmem.avgGap 9355527.34 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -239,23 +239,23 @@ system.cpu.BPredUnit.BTBHits 16735646 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed
system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total)
@ -267,11 +267,11 @@ system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing
@ -283,19 +283,19 @@ system.cpu.rename.SquashCycles 5039795 # Nu
system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running
system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename
system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer
@ -310,11 +310,11 @@ system.cpu.iq.iqSquashedInstsIssued 1224653 # Nu
system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle
@ -326,7 +326,7 @@ system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available
@ -399,7 +399,7 @@ system.cpu.iq.FU_type_0::total 373948163 # Ty
system.cpu.iq.rate 2.738846 # Inst issue rate
system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads
@ -422,7 +422,7 @@ system.cpu.iew.iewSquashCycles 5039795 # Nu
system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions
@ -484,7 +484,7 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 500559121 # The number of ROB reads
system.cpu.rob.rob_writes 772890927 # The number of ROB writes
system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273048375 # Number of Instructions Simulated
system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated
@ -513,36 +513,36 @@ system.cpu.icache.demand_hits::cpu.inst 37470862 # nu
system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits
system.cpu.icache.overall_hits::total 37470862 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses
system.cpu.icache.overall_misses::total 17049 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses
system.cpu.icache.overall_misses::total 17050 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
@ -551,12 +551,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses
@ -582,140 +582,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1414 # number of replacements
system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
system.cpu.dcache.overall_misses::total 25149 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
system.cpu.dcache.writebacks::total 1040 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2774.541574 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011220 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.084672 # Average percentage of cache occupancy
@ -746,16 +620,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 3042 #
system.cpu.l2cache.overall_misses::cpu.data 4307 # number of overall misses
system.cpu.l2cache.overall_misses::total 7349 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 148332000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74801500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 223133500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74802000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 223134000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128955500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 128955500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 148332000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 203757000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 352089000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 203757500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 352089500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 148332000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 203757000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 352089000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 203757500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 352089500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15795 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 17606 # number of ReadReq accesses(hits+misses)
@ -781,16 +655,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192593
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931445 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.359910 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -853,5 +727,131 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1414 # number of replacements
system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use
system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
system.cpu.dcache.overall_misses::total 25149 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
system.cpu.dcache.writebacks::total 1040 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

42
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
executable=/gem5/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864

6
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 20:00:53
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 00:23:14
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

462
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.624868 # Nu
sim_ticks 624867585500 # Number of ticks simulated
final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 118271 # Simulator instruction rate (inst/s)
host_op_rate 161069 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53384157 # Simulator tick rate (ticks/s)
host_mem_usage 298364 # Number of bytes of host memory used
host_seconds 11705.11 # Real time elapsed on the host
host_inst_rate 53257 # Simulator instruction rate (inst/s)
host_op_rate 72528 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 24038469 # Simulator tick rate (ticks/s)
host_mem_usage 255596 # Number of bytes of host memory used
host_seconds 25994.48 # Real time elapsed on the host
sim_insts 1384379060 # Number of instructions simulated
sim_ops 1885333812 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 4108 # Tr
system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 624867513500 # Total gap between requests
system.physmem.totGap 624867514500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests
system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests
system.physmem.totBusLat 1899312000 # Total cycles spent in databus access
system.physmem.totBankLat 12874638000 # Total cycles spent in bank access
system.physmem.avgQLat 6984.13 # Average queueing delay per request
system.physmem.avgBankLat 27114.32 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 38098.45 # Average memory access latency
system.physmem.avgMemAccLat 38098.44 # Average memory access latency
system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s
@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 227490785 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed
system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total)
@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing
@ -290,18 +290,18 @@ system.cpu.rename.SquashCycles 127217578 # Nu
system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename
system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer
@ -316,11 +316,11 @@ system.cpu.iq.iqSquashedInstsIssued 13311855 # Nu
system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle
@ -332,7 +332,7 @@ system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available
@ -405,7 +405,7 @@ system.cpu.iq.FU_type_0::total 2436370950 # Ty
system.cpu.iq.rate 1.949510 # Inst issue rate
system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads
@ -428,7 +428,7 @@ system.cpu.iew.iewSquashCycles 127217578 # Nu
system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions
@ -490,7 +490,7 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 3801294955 # The number of ROB reads
system.cpu.rob.rob_writes 5735909866 # The number of ROB writes
system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384379060 # Number of Instructions Simulated
system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated
@ -519,36 +519,36 @@ system.cpu.icache.demand_hits::cpu.inst 333794637 # nu
system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits
system.cpu.icache.overall_hits::total 333794637 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses
system.cpu.icache.overall_misses::total 30836 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses
system.cpu.icache.overall_misses::total 30837 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked
@ -557,163 +557,37 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2272 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2272 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2272 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2272 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2272 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2272 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379117998 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 379117998 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379117998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 379117998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379117998 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 379117998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1532987 # number of replacements
system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
system.cpu.dcache.writebacks::total 96322 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks.
@ -755,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 474998 # nu
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system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles
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@ -794,17 +668,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.304229 #
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency
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@ -838,18 +712,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431
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@ -864,18 +738,144 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322
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system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
system.cpu.dcache.writebacks::total 96322 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

42
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/gem5/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864

6
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 20:20:38
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 00:36:17
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

480
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.026292 # Nu
sim_ticks 26292466000 # Number of ticks simulated
final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 139577 # Simulator instruction rate (inst/s)
host_op_rate 198063 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51742306 # Simulator tick rate (ticks/s)
host_mem_usage 305460 # Number of bytes of host memory used
host_seconds 508.14 # Real time elapsed on the host
host_inst_rate 43892 # Simulator instruction rate (inst/s)
host_op_rate 62284 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16271073 # Simulator tick rate (ticks/s)
host_mem_usage 263196 # Number of bytes of host memory used
host_seconds 1615.90 # Real time elapsed on the host
sim_insts 70925094 # Number of instructions simulated
sim_ops 100644341 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 5127 # Tr
system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 26292446500 # Total gap between requests
system.physmem.totGap 26292447500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests
system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests
system.physmem.totBusLat 515096000 # Total cycles spent in databus access
system.physmem.totBankLat 1373176000 # Total cycles spent in bank access
system.physmem.avgQLat 37803.91 # Average queueing delay per request
system.physmem.avgQLat 37803.93 # Average queueing delay per request
system.physmem.avgBankLat 10663.46 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 52467.37 # Average memory access latency
system.physmem.avgMemAccLat 52467.38 # Average memory access latency
system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s
@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 7769778 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total)
@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing
@ -289,20 +289,20 @@ system.cpu.decode.SquashedInsts 360894 # Nu
system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running
system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename
system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer
@ -317,11 +317,11 @@ system.cpu.iq.iqSquashedInstsIssued 269260 # Nu
system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle
@ -333,7 +333,7 @@ system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available
@ -406,7 +406,7 @@ system.cpu.iq.FU_type_0::total 107204361 # Ty
system.cpu.iq.rate 2.038690 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads
@ -429,7 +429,7 @@ system.cpu.iew.iewSquashCycles 1617500 # Nu
system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions
@ -459,11 +459,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle
@ -475,7 +475,7 @@ system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70930646 # Number of instructions committed
system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -488,10 +488,10 @@ system.cpu.commit.int_insts 91486751 # Nu
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 149890854 # The number of ROB reads
system.cpu.rob.rob_reads 149890856 # The number of ROB reads
system.cpu.rob.rob_writes 224611140 # The number of ROB writes
system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70925094 # Number of Instructions Simulated
system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated
@ -506,12 +506,12 @@ system.cpu.fp_regfile_writes 582 # nu
system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads
system.cpu.misc_regfile_writes 38826 # number of misc regfile writes
system.cpu.icache.replacements 30543 # number of replacements
system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use
system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits
@ -520,36 +520,36 @@ system.cpu.icache.demand_hits::cpu.inst 11635567 # nu
system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits
system.cpu.icache.overall_hits::total 11635567 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses
system.cpu.icache.overall_misses::total 36657 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses
system.cpu.icache.overall_misses::total 36658 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked
@ -558,172 +558,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 158306 # number of replacements
system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
system.cpu.dcache.writebacks::total 129052 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 95650 # number of replacements
system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use
system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks.
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system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor
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@ -756,19 +630,19 @@ system.cpu.l2cache.demand_misses::total 128851 # nu
system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses
system.cpu.l2cache.overall_misses::total 128851 # number of overall misses
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system.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles
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@ -797,19 +671,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.661538 #
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
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@ -842,19 +716,19 @@ system.cpu.l2cache.demand_mshr_misses::total 128777
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@ -868,19 +742,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
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system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

42
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
executable=/gem5/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864

8
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 20:33:15
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 00:51:58
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 506342716000 because target called exit()
Exiting @ tick 506577346000 because target called exit()

1309
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

42
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
executable=/gem5/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864

6
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 20:48:26
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 5 2013 01:10:37
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

446
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.074245 # Nu
sim_ticks 74245032000 # Number of ticks simulated
final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131550 # Simulator instruction rate (inst/s)
host_op_rate 144033 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56674428 # Simulator tick rate (ticks/s)
host_mem_usage 280244 # Number of bytes of host memory used
host_seconds 1310.03 # Real time elapsed on the host
host_inst_rate 44193 # Simulator instruction rate (inst/s)
host_op_rate 48386 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19039219 # Simulator tick rate (ticks/s)
host_mem_usage 236076 # Number of bytes of host memory used
host_seconds 3899.58 # Real time elapsed on the host
sim_insts 172333441 # Number of instructions simulated
sim_ops 188686923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 74245012500 # Total gap between requests
system.physmem.totGap 74245013500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 12366785 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests
system.physmem.totQLat 12368785 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests
system.physmem.totBusLat 15172000 # Total cycles spent in databus access
system.physmem.totBankLat 58828000 # Total cycles spent in bank access
system.physmem.avgQLat 3260.42 # Average queueing delay per request
system.physmem.avgQLat 3260.95 # Average queueing delay per request
system.physmem.avgBankLat 15509.62 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22770.05 # Average memory access latency
system.physmem.avgMemAccLat 22770.57 # Average memory access latency
system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s
@ -184,7 +184,7 @@ system.physmem.readRowHits 3295 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19574218.96 # Average gap between requests
system.physmem.avgGap 19574219.22 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -239,24 +239,24 @@ system.cpu.BPredUnit.BTBHits 43068728 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed
system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total)
@ -268,11 +268,11 @@ system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing
@ -284,19 +284,19 @@ system.cpu.rename.SquashCycles 20843724 # Nu
system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running
system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename
system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer
@ -311,11 +311,11 @@ system.cpu.iq.iqSquashedInstsIssued 795533 # Nu
system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle
@ -327,7 +327,7 @@ system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available
@ -400,7 +400,7 @@ system.cpu.iq.FU_type_0::total 249531465 # Ty
system.cpu.iq.rate 1.680459 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads
@ -423,7 +423,7 @@ system.cpu.iew.iewSquashCycles 20843724 # Nu
system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions
@ -485,7 +485,7 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 449048801 # The number of ROB reads
system.cpu.rob.rob_writes 679713725 # The number of ROB writes
system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172333441 # Number of Instructions Simulated
system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated
@ -500,12 +500,12 @@ system.cpu.fp_regfile_writes 2497505 # nu
system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads
system.cpu.misc_regfile_writes 832204 # number of misc regfile writes
system.cpu.icache.replacements 2508 # number of replacements
system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use
system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits
@ -514,36 +514,36 @@ system.cpu.icache.demand_hits::cpu.inst 36854521 # nu
system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits
system.cpu.icache.overall_hits::total 36854521 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses
system.cpu.icache.overall_misses::total 5339 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses
system.cpu.icache.overall_misses::total 5340 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
@ -552,12 +552,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses
@ -583,141 +583,15 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 57 # number of replacements
system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
system.cpu.dcache.overall_misses::total 9552 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
system.cpu.dcache.writebacks::total 18 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy
@ -749,16 +623,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2051 #
system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses
system.cpu.l2cache.overall_misses::total 3807 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses)
@ -788,16 +662,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298
system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -828,19 +702,19 @@ system.cpu.l2cache.demand_mshr_misses::total 3793
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses
@ -854,19 +728,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 57 # number of replacements
system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use
system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
system.cpu.dcache.overall_misses::total 9552 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
system.cpu.dcache.writebacks::total 18 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

28
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -433,21 +430,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -464,6 +456,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
@ -483,21 +478,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -524,7 +514,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864

10
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -1,14 +1,10 @@
Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18
gem5 started Dec 30 2012 00:48:42
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jan 4 2013 21:20:54
gem5 started Jan 4 2013 23:04:52
gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

400
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.082648 # Nu
sim_ticks 82648140000 # Number of ticks simulated
final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 58118 # Simulator instruction rate (inst/s)
host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36369167 # Simulator tick rate (ticks/s)
host_mem_usage 286740 # Number of bytes of host memory used
host_seconds 2272.48 # Real time elapsed on the host
host_inst_rate 31465 # Simulator instruction rate (inst/s)
host_op_rate 52738 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19690094 # Simulator tick rate (ticks/s)
host_mem_usage 268216 # Number of bytes of host memory used
host_seconds 4197.45 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 82648108000 # Total gap between requests
system.physmem.totGap 82648109000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 16873322 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests
system.physmem.totQLat 16873822 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests
system.physmem.totBusLat 21392000 # Total cycles spent in databus access
system.physmem.totBankLat 84182000 # Total cycles spent in bank access
system.physmem.avgQLat 3155.07 # Average queueing delay per request
system.physmem.avgQLat 3155.16 # Average queueing delay per request
system.physmem.avgBankLat 15740.84 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22895.91 # Average memory access latency
system.physmem.avgMemAccLat 22896.00 # Average memory access latency
system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
@ -184,7 +184,7 @@ system.physmem.readRowHits 4742 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 15454021.69 # Average gap between requests
system.physmem.avgGap 15454021.88 # Average gap between requests
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 165296281 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -197,18 +197,18 @@ system.cpu.BPredUnit.BTBHits 13098591 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed
system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total)
@ -454,12 +454,12 @@ system.cpu.fp_regfile_writes 2230055 # nu
system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.icache.replacements 4732 # number of replacements
system.cpu.icache.tagsinuse 1624.168421 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use
system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1624.168421 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits
@ -468,36 +468,36 @@ system.cpu.icache.demand_hits::cpu.inst 24437101 # nu
system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits
system.cpu.icache.overall_hits::total 24437101 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 8951 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 8951 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 8951 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 8951 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 8951 # number of overall misses
system.cpu.icache.overall_misses::total 8951 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259393998 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 259393998 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 259393998 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 259393998 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 259393998 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 259393998 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24446052 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24446052 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24446052 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24446052 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24446052 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24446052 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses
system.cpu.icache.overall_misses::total 8952 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28979.331695 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28979.331695 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28979.331695 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28979.331695 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked
@ -506,154 +506,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2096 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2096 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2096 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2096 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2096 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2096 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198301998 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 198301998 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198301998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 198301998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198301998 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 198301998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.081400 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.081400 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 55 # number of replacements
system.cpu.dcache.tagsinuse 1411.367255 # Cycle average of tags in use
system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1411.367255 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
system.cpu.dcache.overall_misses::total 2513 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 37144500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 113997500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 113997500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 113997500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 113997500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.912769 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.912769 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45363.111819 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45363.111819 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
system.cpu.dcache.writebacks::total 14 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
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@ -755,18 +647,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5348
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

239
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
View file

@ -10,20 +10,21 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1
clock=1000
dtb_filename=
early_kernel_symbols=false
enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
memories=system.physmem system.realview.nvmem
midr_regval=890224640
mem_ranges=0:134217727
memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
clock=1
clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
@ -64,16 +65,15 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts itb tracer
children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -82,6 +82,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -92,6 +93,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
@ -104,23 +106,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@ -134,7 +131,7 @@ walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -144,23 +141,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@ -169,6 +161,23 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=ArmInterrupts
[system.cpu0.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu0.itb]
type=ArmTLB
children=walker
@ -177,7 +186,7 @@ walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -187,11 +196,10 @@ type=ExeTracer
[system.cpu1]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts itb tracer
children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -200,6 +208,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -210,6 +219,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu1.tracer
width=1
@ -222,23 +232,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@ -252,7 +257,7 @@ walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
@ -262,23 +267,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@ -287,6 +287,23 @@ mem_side=system.toL2Bus.slave[4]
[system.cpu1.interrupts]
type=ArmInterrupts
[system.cpu1.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu1.itb]
type=ArmTLB
children=walker
@ -295,7 +312,7 @@ walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
@ -319,57 +336,47 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
addr_ranges=0:268435455
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50000
is_top_level=false
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50000
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[1]
mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=10000
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=92
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=10000
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=16
trace_addr=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@ -381,11 +388,11 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clock=1
clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
@ -401,15 +408,28 @@ warn_access=warn
pio=system.membus.default
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1
type=SimpleDRAM
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
lines_per_rowbuffer=64
mem_sched_policy=fcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[2]
@ -424,7 +444,7 @@ system=system
[system.realview.a9scu]
type=A9SCU
clock=1
clock=1000
pio_addr=520093696
pio_latency=100000
system=system
@ -433,7 +453,7 @@ pio=system.membus.master[5]
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
@ -480,7 +500,7 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clock=1
clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
@ -498,11 +518,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@ -511,7 +532,7 @@ pio=system.iobus.master[4]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
@ -520,7 +541,7 @@ pio=system.iobus.master[9]
[system.realview.flash_fake]
type=IsaFake
clock=1
clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
@ -537,7 +558,7 @@ pio=system.iobus.master[24]
[system.realview.gic]
type=Gic
clock=1
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
@ -551,7 +572,7 @@ pio=system.membus.master[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
@ -561,7 +582,7 @@ pio=system.iobus.master[16]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
@ -571,7 +592,7 @@ pio=system.iobus.master[17]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
@ -581,7 +602,7 @@ pio=system.iobus.master[18]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
clock=1
clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
@ -595,7 +616,7 @@ pio=system.iobus.master[5]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
clock=1
clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
@ -608,7 +629,7 @@ pio=system.iobus.master[6]
[system.realview.l2x0_fake]
type=IsaFake
clock=1
clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
@ -637,7 +658,7 @@ pio=system.membus.master[6]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
@ -647,7 +668,7 @@ pio=system.iobus.master[22]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
clock=1
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@ -659,7 +680,7 @@ port=system.membus.master[1]
[system.realview.realview_io]
type=RealViewCtrl
clock=1
clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
@ -671,7 +692,7 @@ pio=system.iobus.master[1]
[system.realview.rtc]
type=PL031
amba_id=3412017
clock=1
clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
@ -684,7 +705,7 @@ pio=system.iobus.master[23]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
@ -694,7 +715,7 @@ pio=system.iobus.master[20]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
@ -704,7 +725,7 @@ pio=system.iobus.master[13]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
@ -714,7 +735,7 @@ pio=system.iobus.master[14]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
@ -724,7 +745,7 @@ pio=system.iobus.master[19]
[system.realview.timer0]
type=Sp804
amba_id=1316868
clock=1
clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@ -738,7 +759,7 @@ pio=system.iobus.master[2]
[system.realview.timer1]
type=Sp804
amba_id=1316868
clock=1
clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@ -751,7 +772,7 @@ pio=system.iobus.master[3]
[system.realview.uart]
type=Pl011
clock=1
clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
@ -766,7 +787,7 @@ pio=system.iobus.master[0]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
@ -776,7 +797,7 @@ pio=system.iobus.master[10]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
@ -786,7 +807,7 @@ pio=system.iobus.master[11]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
@ -796,7 +817,7 @@ pio=system.iobus.master[12]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
@ -813,7 +834,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
clock=500
header_cycles=1
use_default_range=false
width=8

1
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
View file

@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00
gem5 started Sep 21 2012 11:19:07
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:29:32
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 912096763500 because m5_exit instruction encountered

136
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
View file

@ -4,22 +4,40 @@ sim_seconds 0.912097 # Nu
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1752000 # Simulator instruction rate (inst/s)
host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 25930494646 # Simulator tick rate (ticks/s)
host_mem_usage 382232 # Number of bytes of host memory used
host_seconds 35.17 # Real time elapsed on the host
host_inst_rate 599236 # Simulator instruction rate (inst/s)
host_op_rate 771515 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 8869004975 # Simulator tick rate (ticks/s)
host_mem_usage 384344 # Number of bytes of host memory used
host_seconds 102.84 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory
system.physmem.bytes_read::total 49638308 # Number of bytes read from this memory
system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
@ -31,11 +49,11 @@ system.physmem.num_reads::realview.clcd 4915200 # Nu
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5082797 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
@ -44,11 +62,11 @@ system.physmem.bw_read::realview.clcd 43111215 # To
system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 6835893 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 54422195 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s)
@ -61,11 +79,11 @@ system.physmem.bw_total::realview.clcd 43111215 # To
system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 6854532 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
@ -224,47 +242,29 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 70662 # number of replacements
system.l2c.tagsinuse 51560.217790 # Cycle average of tags in use
system.l2c.total_refs 1623342 # Total number of references to valid blocks.
system.l2c.sampled_refs 135814 # Sample count of references to valid blocks.
system.l2c.avg_refs 11.952685 # Average number of references to valid blocks.
system.l2c.replacements 70658 # number of replacements
system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
system.l2c.total_refs 1623339 # Total number of references to valid blocks.
system.l2c.sampled_refs 135810 # Sample count of references to valid blocks.
system.l2c.avg_refs 11.953015 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 39276.104351 # Average occupied blocks per requestor
system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4360.752038 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2483.307369 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.599306 # Average percentage of cache occupancy
system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.066540 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.037892 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.786746 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
@ -282,27 +282,27 @@ system.l2c.UpgradeReq_hits::total 1274 # nu
system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 58151 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 108363 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 233339 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
system.l2c.demand_hits::total 1317469 # number of demand (read+write) hits
system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
system.l2c.overall_hits::cpu0.data 233339 # number of overall hits
system.l2c.overall_hits::cpu0.data 233336 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
system.l2c.overall_hits::total 1317469 # number of overall hits
system.l2c.overall_hits::total 1317466 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
@ -317,25 +317,25 @@ system.l2c.UpgradeReq_misses::total 9236 # nu
system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 92461 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140833 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 98853 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses
system.l2c.demand_misses::total 163287 # number of demand (read+write) misses
system.l2c.demand_misses::total 163290 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
system.l2c.overall_misses::cpu0.data 98853 # number of overall misses
system.l2c.overall_misses::cpu0.data 98856 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
system.l2c.overall_misses::cpu1.data 53648 # number of overall misses
system.l2c.overall_misses::total 163287 # number of overall misses
system.l2c.overall_misses::total 163290 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
@ -388,25 +388,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.878782 # mi
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.613902 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.565150 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.297578 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.110273 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.297578 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.110273 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -490,15 +490,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe
system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed
system.cpu0.icache.replacements 428547 # number of replacements
system.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use
system.cpu0.icache.replacements 428546 # number of replacements
system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use
system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks.
system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits

239
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
View file

@ -10,20 +10,21 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1
clock=1000
dtb_filename=
early_kernel_symbols=false
enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
midr_regval=890224640
mem_ranges=0:134217727
memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
clock=1
clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
@ -64,16 +65,15 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb tracer
children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -81,6 +81,7 @@ dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -89,6 +90,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu0.tracer
workload=
@ -100,23 +102,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@ -130,7 +127,7 @@ walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@ -140,23 +137,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@ -165,6 +157,23 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=ArmInterrupts
[system.cpu0.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu0.itb]
type=ArmTLB
children=walker
@ -173,7 +182,7 @@ walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@ -183,11 +192,10 @@ type=ExeTracer
[system.cpu1]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb tracer
children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -195,6 +203,7 @@ dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -203,6 +212,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu1.tracer
workload=
@ -214,23 +224,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@ -244,7 +249,7 @@ walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
@ -254,23 +259,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@ -279,6 +279,23 @@ mem_side=system.toL2Bus.slave[4]
[system.cpu1.interrupts]
type=ArmInterrupts
[system.cpu1.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu1.itb]
type=ArmTLB
children=walker
@ -287,7 +304,7 @@ walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
@ -311,57 +328,47 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
addr_ranges=0:268435455
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50000
is_top_level=false
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50000
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[1]
mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=10000
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=92
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=10000
response_latency=20
size=4194304
subblock_size=0
system=system
tgts_per_mshr=16
trace_addr=0
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@ -373,11 +380,11 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clock=1
clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
@ -393,15 +400,28 @@ warn_access=warn
pio=system.membus.default
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1
type=SimpleDRAM
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
lines_per_rowbuffer=64
mem_sched_policy=fcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[2]
@ -416,7 +436,7 @@ system=system
[system.realview.a9scu]
type=A9SCU
clock=1
clock=1000
pio_addr=520093696
pio_latency=100000
system=system
@ -425,7 +445,7 @@ pio=system.membus.master[5]
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
@ -472,7 +492,7 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clock=1
clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
@ -490,11 +510,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@ -503,7 +524,7 @@ pio=system.iobus.master[4]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
@ -512,7 +533,7 @@ pio=system.iobus.master[9]
[system.realview.flash_fake]
type=IsaFake
clock=1
clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
@ -529,7 +550,7 @@ pio=system.iobus.master[24]
[system.realview.gic]
type=Gic
clock=1
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
@ -543,7 +564,7 @@ pio=system.membus.master[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
@ -553,7 +574,7 @@ pio=system.iobus.master[16]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
@ -563,7 +584,7 @@ pio=system.iobus.master[17]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
@ -573,7 +594,7 @@ pio=system.iobus.master[18]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
clock=1
clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
@ -587,7 +608,7 @@ pio=system.iobus.master[5]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
clock=1
clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
@ -600,7 +621,7 @@ pio=system.iobus.master[6]
[system.realview.l2x0_fake]
type=IsaFake
clock=1
clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
@ -629,7 +650,7 @@ pio=system.membus.master[6]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
@ -639,7 +660,7 @@ pio=system.iobus.master[22]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
clock=1
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@ -651,7 +672,7 @@ port=system.membus.master[1]
[system.realview.realview_io]
type=RealViewCtrl
clock=1
clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
@ -663,7 +684,7 @@ pio=system.iobus.master[1]
[system.realview.rtc]
type=PL031
amba_id=3412017
clock=1
clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
@ -676,7 +697,7 @@ pio=system.iobus.master[23]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
@ -686,7 +707,7 @@ pio=system.iobus.master[20]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
@ -696,7 +717,7 @@ pio=system.iobus.master[13]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
@ -706,7 +727,7 @@ pio=system.iobus.master[14]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
@ -716,7 +737,7 @@ pio=system.iobus.master[19]
[system.realview.timer0]
type=Sp804
amba_id=1316868
clock=1
clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@ -730,7 +751,7 @@ pio=system.iobus.master[2]
[system.realview.timer1]
type=Sp804
amba_id=1316868
clock=1
clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@ -743,7 +764,7 @@ pio=system.iobus.master[3]
[system.realview.uart]
type=Pl011
clock=1
clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
@ -758,7 +779,7 @@ pio=system.iobus.master[0]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
@ -768,7 +789,7 @@ pio=system.iobus.master[10]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
@ -778,7 +799,7 @@ pio=system.iobus.master[11]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
@ -788,7 +809,7 @@ pio=system.iobus.master[12]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
@ -805,7 +826,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
clock=500
header_cycles=1
use_default_range=false
width=8

1
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
View file

@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here

10
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00
gem5 started Sep 21 2012 11:19:18
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:31:36
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1207290627000 because m5_exit instruction encountered
Exiting @ tick 1182882156500 because m5_exit instruction encountered

1986
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

245
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
View file

@ -8,22 +8,23 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1
clock=1000
dtb_filename=
early_kernel_symbols=false
enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
midr_regval=890224640
mem_ranges=0:134217727
memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
clock=1
clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
@ -64,16 +65,15 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb tracer
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -81,6 +81,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -89,6 +90,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=
@ -100,27 +102,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.slave[1]
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
@ -130,41 +127,53 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
clock=1
clock=500
forward_snoops=true
hash_delay=1
hit_latency=1000
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=1000
response_latency=2
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.toL2Bus.slave[0]
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -173,10 +182,42 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clock=1
clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=4194304
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@ -197,56 +238,24 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
addr_ranges=0:268435455
addr_ranges=0:134217727
assoc=8
block_size=64
clock=1
clock=1000
forward_snoops=false
hash_delay=1
hit_latency=50000
is_top_level=false
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=50000
response_latency=50
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[1]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=1
forward_snoops=true
hash_delay=1
hit_latency=10000
is_top_level=false
max_miss_count=0
mshrs=92
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=10000
size=4194304
subblock_size=0
system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
@ -259,11 +268,11 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clock=1
clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
@ -279,15 +288,28 @@ warn_access=warn
pio=system.membus.default
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1
type=SimpleDRAM
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
lines_per_rowbuffer=64
mem_sched_policy=fcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[2]
@ -302,7 +324,7 @@ system=system
[system.realview.a9scu]
type=A9SCU
clock=1
clock=1000
pio_addr=520093696
pio_latency=100000
system=system
@ -311,7 +333,7 @@ pio=system.membus.master[5]
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
@ -358,7 +380,7 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clock=1
clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
@ -376,11 +398,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@ -389,7 +412,7 @@ pio=system.iobus.master[4]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
@ -398,7 +421,7 @@ pio=system.iobus.master[9]
[system.realview.flash_fake]
type=IsaFake
clock=1
clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
@ -415,7 +438,7 @@ pio=system.iobus.master[24]
[system.realview.gic]
type=Gic
clock=1
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
@ -429,7 +452,7 @@ pio=system.membus.master[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
@ -439,7 +462,7 @@ pio=system.iobus.master[16]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
@ -449,7 +472,7 @@ pio=system.iobus.master[17]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
@ -459,7 +482,7 @@ pio=system.iobus.master[18]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
clock=1
clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
@ -473,7 +496,7 @@ pio=system.iobus.master[5]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
clock=1
clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
@ -486,7 +509,7 @@ pio=system.iobus.master[6]
[system.realview.l2x0_fake]
type=IsaFake
clock=1
clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
@ -515,7 +538,7 @@ pio=system.membus.master[6]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
@ -525,7 +548,7 @@ pio=system.iobus.master[22]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
clock=1
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@ -537,7 +560,7 @@ port=system.membus.master[1]
[system.realview.realview_io]
type=RealViewCtrl
clock=1
clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
@ -549,7 +572,7 @@ pio=system.iobus.master[1]
[system.realview.rtc]
type=PL031
amba_id=3412017
clock=1
clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
@ -562,7 +585,7 @@ pio=system.iobus.master[23]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
@ -572,7 +595,7 @@ pio=system.iobus.master[20]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
@ -582,7 +605,7 @@ pio=system.iobus.master[13]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
@ -592,7 +615,7 @@ pio=system.iobus.master[14]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
@ -602,7 +625,7 @@ pio=system.iobus.master[19]
[system.realview.timer0]
type=Sp804
amba_id=1316868
clock=1
clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@ -616,7 +639,7 @@ pio=system.iobus.master[2]
[system.realview.timer1]
type=Sp804
amba_id=1316868
clock=1
clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@ -629,7 +652,7 @@ pio=system.iobus.master[3]
[system.realview.uart]
type=Pl011
clock=1
clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
@ -644,7 +667,7 @@ pio=system.iobus.master[0]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
@ -654,7 +677,7 @@ pio=system.iobus.master[10]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
@ -664,7 +687,7 @@ pio=system.iobus.master[11]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
@ -674,7 +697,7 @@ pio=system.iobus.master[12]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
clock=1
clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
@ -688,16 +711,6 @@ number=0
output=true
port=3456
[system.toL2Bus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.vncserver]
type=VncServer
frame_capture=false

1
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
View file

@ -11,7 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here

10
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00
gem5 started Sep 21 2012 11:19:18
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:31:27
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2629149747000 because m5_exit instruction encountered
Exiting @ tick 2603634694000 because m5_exit instruction encountered

964
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

314
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
View file

@ -1,17 +1,19 @@
[drivesys]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
boot_cpu_frequency=1
boot_cpu_frequency=250
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
clock=1000
console=/gem5/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=drivesys.physmem
num_work_ids=16
pal=/dist/m5/system/binaries/ts_osfpal
readfile=/tmp/gem5.ali/configs/boot/netperf-server.rcS
pal=/gem5/dist/binaries/ts_osfpal
readfile=/gem5/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
@ -26,22 +28,20 @@ system_port=drivesys.membus.slave[0]
[drivesys.bridge]
type=Bridge
clock=1000
delay=50000
nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
write_ack=false
master=drivesys.iobus.slave[0]
slave=drivesys.membus.master[0]
[drivesys.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer
children=dtb interrupts isa itb tracer
checker=Null
clock=1
clock=250
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -50,17 +50,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=drivesys.cpu.interrupts
isa=drivesys.cpu.isa
itb=drivesys.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=drivesys
tracer=drivesys.cpu.tracer
width=1
@ -75,6 +76,9 @@ size=64
[drivesys.cpu.interrupts]
type=AlphaInterrupts
[drivesys.cpu.isa]
type=AlphaISA
[drivesys.cpu.itb]
type=AlphaTLB
size=48
@ -99,7 +103,7 @@ table_size=65536
[drivesys.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[drivesys.disk2]
@ -119,7 +123,7 @@ table_size=65536
[drivesys.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[drivesys.intrctrl]
@ -128,12 +132,11 @@ sys=drivesys
[drivesys.iobridge]
type=Bridge
clock=1000
delay=50000
nack_delay=4000
ranges=0:8589934592
ranges=0:134217727
req_size=16
resp_size=16
write_ack=false
master=drivesys.membus.slave[3]
slave=drivesys.iobus.master[29]
@ -143,7 +146,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=true
width=64
width=8
default=drivesys.tsunami.pciconfig.pio
master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave
slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
@ -155,16 +158,17 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
default=drivesys.membus.badaddr_responder.pio
master=drivesys.bridge.slave drivesys.physmem.port[0]
master=drivesys.bridge.slave drivesys.physmem.port
slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
[drivesys.membus.badaddr_responder]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=0
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
@ -177,14 +181,28 @@ warn_access=
pio=drivesys.membus.default
[drivesys.physmem]
type=SimpleMemory
type=SimpleDRAM
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
lines_per_rowbuffer=64
mem_sched_policy=fcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=drivesys.membus.master[1]
@ -196,7 +214,7 @@ system=drivesys
[drivesys.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[drivesys.terminal]
@ -214,10 +232,11 @@ system=drivesys
[drivesys.tsunami.backdoor]
type=AlphaBackdoor
clock=1000
cpu=drivesys.cpu
disk=drivesys.simple_disk
pio_addr=8804682956800
pio_latency=1000
pio_latency=100000
platform=drivesys.tsunami
system=drivesys
terminal=drivesys.terminal
@ -225,8 +244,9 @@ pio=drivesys.iobus.master[24]
[drivesys.tsunami.cchip]
type=TsunamiCChip
clock=1000
pio_addr=8803072344064
pio_latency=1000
pio_latency=100000
system=drivesys
tsunami=drivesys.tsunami
pio=drivesys.iobus.master[0]
@ -271,7 +291,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
clock=0
clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
@ -282,12 +302,10 @@ dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:02
intr_delay=10000000
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=1000
pio_latency=30000
platform=drivesys.tsunami
rss=false
rx_delay=1000000
@ -305,9 +323,10 @@ pio=drivesys.iobus.master[27]
[drivesys.tsunami.fake_OROM]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8796093677568
pio_latency=1000
pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
@ -321,9 +340,10 @@ pio=drivesys.iobus.master[8]
[drivesys.tsunami.fake_ata0]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848432
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -337,9 +357,10 @@ pio=drivesys.iobus.master[19]
[drivesys.tsunami.fake_ata1]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848304
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -353,9 +374,10 @@ pio=drivesys.iobus.master[20]
[drivesys.tsunami.fake_pnp_addr]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848569
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -369,9 +391,10 @@ pio=drivesys.iobus.master[9]
[drivesys.tsunami.fake_pnp_read0]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848451
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -385,9 +408,10 @@ pio=drivesys.iobus.master[11]
[drivesys.tsunami.fake_pnp_read1]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848515
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -401,9 +425,10 @@ pio=drivesys.iobus.master[12]
[drivesys.tsunami.fake_pnp_read2]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848579
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -417,9 +442,10 @@ pio=drivesys.iobus.master[13]
[drivesys.tsunami.fake_pnp_read3]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848643
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -433,9 +459,10 @@ pio=drivesys.iobus.master[14]
[drivesys.tsunami.fake_pnp_read4]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848707
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -449,9 +476,10 @@ pio=drivesys.iobus.master[15]
[drivesys.tsunami.fake_pnp_read5]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848771
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -465,9 +493,10 @@ pio=drivesys.iobus.master[16]
[drivesys.tsunami.fake_pnp_read6]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848835
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -481,9 +510,10 @@ pio=drivesys.iobus.master[17]
[drivesys.tsunami.fake_pnp_read7]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848899
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -497,9 +527,10 @@ pio=drivesys.iobus.master[18]
[drivesys.tsunami.fake_pnp_write]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615850617
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -513,9 +544,10 @@ pio=drivesys.iobus.master[10]
[drivesys.tsunami.fake_ppc]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848891
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -529,9 +561,10 @@ pio=drivesys.iobus.master[7]
[drivesys.tsunami.fake_sm_chip]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848816
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -545,9 +578,10 @@ pio=drivesys.iobus.master[2]
[drivesys.tsunami.fake_uart1]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848696
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -561,9 +595,10 @@ pio=drivesys.iobus.master[3]
[drivesys.tsunami.fake_uart2]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848936
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -577,9 +612,10 @@ pio=drivesys.iobus.master[4]
[drivesys.tsunami.fake_uart3]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848680
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -593,9 +629,10 @@ pio=drivesys.iobus.master[5]
[drivesys.tsunami.fake_uart4]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848944
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -609,9 +646,10 @@ pio=drivesys.iobus.master[6]
[drivesys.tsunami.fb]
type=BadDevice
clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
pio_latency=100000
system=drivesys
pio=drivesys.iobus.master[21]
@ -655,16 +693,15 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clock=1000
config_latency=20000
ctrl_offset=0
disks=drivesys.disk0 drivesys.disk2
io_shift=0
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=1000
pio_latency=30000
platform=drivesys.tsunami
system=drivesys
config=drivesys.iobus.master[26]
@ -673,9 +710,10 @@ pio=drivesys.iobus.master[25]
[drivesys.tsunami.io]
type=TsunamiIO
clock=1000
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
pio_latency=100000
system=drivesys
time=Thu Jan 1 00:00:00 2009
tsunami=drivesys.tsunami
@ -684,8 +722,9 @@ pio=drivesys.iobus.master[22]
[drivesys.tsunami.pchip]
type=TsunamiPChip
clock=1000
pio_addr=8802535473152
pio_latency=1000
pio_latency=100000
system=drivesys
tsunami=drivesys.tsunami
pio=drivesys.iobus.master[1]
@ -693,7 +732,8 @@ pio=drivesys.iobus.master[1]
[drivesys.tsunami.pciconfig]
type=PciConfigAll
bus=0
pio_latency=1
clock=1000
pio_latency=30000
platform=drivesys.tsunami
size=16777216
system=drivesys
@ -701,8 +741,9 @@ pio=drivesys.iobus.default
[drivesys.tsunami.uart]
type=Uart8250
clock=1000
pio_addr=8804615848952
pio_latency=1000
pio_latency=100000
platform=drivesys.tsunami
system=drivesys
terminal=drivesys.terminal
@ -733,17 +774,19 @@ time_sync_spin_threshold=100000000
[testsys]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
boot_cpu_frequency=1
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
clock=1000
console=/gem5/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/gem5/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=testsys.physmem
num_work_ids=16
pal=/dist/m5/system/binaries/ts_osfpal
readfile=/tmp/gem5.ali/configs/boot/netperf-stream-client.rcS
pal=/gem5/dist/binaries/ts_osfpal
readfile=/gem5/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
@ -758,22 +801,20 @@ system_port=testsys.membus.slave[0]
[testsys.bridge]
type=Bridge
clock=1000
delay=50000
nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
write_ack=false
master=testsys.iobus.slave[0]
slave=testsys.membus.master[0]
[testsys.cpu]
type=AtomicSimpleCPU
children=dtb interrupts itb tracer
children=dtb interrupts isa itb tracer
checker=Null
clock=1
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -782,17 +823,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=testsys.cpu.interrupts
isa=testsys.cpu.isa
itb=testsys.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=testsys
tracer=testsys.cpu.tracer
width=1
@ -807,6 +849,9 @@ size=64
[testsys.cpu.interrupts]
type=AlphaInterrupts
[testsys.cpu.isa]
type=AlphaISA
[testsys.cpu.itb]
type=AlphaTLB
size=48
@ -831,7 +876,7 @@ table_size=65536
[testsys.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[testsys.disk2]
@ -851,7 +896,7 @@ table_size=65536
[testsys.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/gem5/dist/disks/linux-bigswap2.img
read_only=true
[testsys.intrctrl]
@ -860,12 +905,11 @@ sys=testsys
[testsys.iobridge]
type=Bridge
clock=1000
delay=50000
nack_delay=4000
ranges=0:8589934592
ranges=0:134217727
req_size=16
resp_size=16
write_ack=false
master=testsys.membus.slave[3]
slave=testsys.iobus.master[29]
@ -875,7 +919,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=true
width=64
width=8
default=testsys.tsunami.pciconfig.pio
master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave
slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
@ -887,16 +931,17 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
default=testsys.membus.badaddr_responder.pio
master=testsys.bridge.slave testsys.physmem.port[0]
master=testsys.bridge.slave testsys.physmem.port
slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
[testsys.membus.badaddr_responder]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=0
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
@ -909,14 +954,28 @@ warn_access=
pio=testsys.membus.default
[testsys.physmem]
type=SimpleMemory
type=SimpleDRAM
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
lines_per_rowbuffer=64
mem_sched_policy=fcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=4000
tCL=14000
tRCD=14000
tREFI=7800000
tRFC=300000
tRP=14000
tWTR=1000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=testsys.membus.master[1]
@ -928,7 +987,7 @@ system=testsys
[testsys.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/gem5/dist/disks/linux-latest.img
read_only=true
[testsys.terminal]
@ -946,10 +1005,11 @@ system=testsys
[testsys.tsunami.backdoor]
type=AlphaBackdoor
clock=1000
cpu=testsys.cpu
disk=testsys.simple_disk
pio_addr=8804682956800
pio_latency=1000
pio_latency=100000
platform=testsys.tsunami
system=testsys
terminal=testsys.terminal
@ -957,8 +1017,9 @@ pio=testsys.iobus.master[24]
[testsys.tsunami.cchip]
type=TsunamiCChip
clock=1000
pio_addr=8803072344064
pio_latency=1000
pio_latency=100000
system=testsys
tsunami=testsys.tsunami
pio=testsys.iobus.master[0]
@ -1003,7 +1064,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
clock=0
clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
@ -1014,12 +1075,10 @@ dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=1000
pio_latency=30000
platform=testsys.tsunami
rss=false
rx_delay=1000000
@ -1037,9 +1096,10 @@ pio=testsys.iobus.master[27]
[testsys.tsunami.fake_OROM]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8796093677568
pio_latency=1000
pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
@ -1053,9 +1113,10 @@ pio=testsys.iobus.master[8]
[testsys.tsunami.fake_ata0]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848432
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1069,9 +1130,10 @@ pio=testsys.iobus.master[19]
[testsys.tsunami.fake_ata1]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848304
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1085,9 +1147,10 @@ pio=testsys.iobus.master[20]
[testsys.tsunami.fake_pnp_addr]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848569
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1101,9 +1164,10 @@ pio=testsys.iobus.master[9]
[testsys.tsunami.fake_pnp_read0]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848451
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1117,9 +1181,10 @@ pio=testsys.iobus.master[11]
[testsys.tsunami.fake_pnp_read1]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848515
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1133,9 +1198,10 @@ pio=testsys.iobus.master[12]
[testsys.tsunami.fake_pnp_read2]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848579
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1149,9 +1215,10 @@ pio=testsys.iobus.master[13]
[testsys.tsunami.fake_pnp_read3]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848643
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1165,9 +1232,10 @@ pio=testsys.iobus.master[14]
[testsys.tsunami.fake_pnp_read4]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848707
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1181,9 +1249,10 @@ pio=testsys.iobus.master[15]
[testsys.tsunami.fake_pnp_read5]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848771
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1197,9 +1266,10 @@ pio=testsys.iobus.master[16]
[testsys.tsunami.fake_pnp_read6]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848835
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1213,9 +1283,10 @@ pio=testsys.iobus.master[17]
[testsys.tsunami.fake_pnp_read7]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848899
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1229,9 +1300,10 @@ pio=testsys.iobus.master[18]
[testsys.tsunami.fake_pnp_write]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615850617
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1245,9 +1317,10 @@ pio=testsys.iobus.master[10]
[testsys.tsunami.fake_ppc]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848891
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1261,9 +1334,10 @@ pio=testsys.iobus.master[7]
[testsys.tsunami.fake_sm_chip]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848816
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1277,9 +1351,10 @@ pio=testsys.iobus.master[2]
[testsys.tsunami.fake_uart1]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848696
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1293,9 +1368,10 @@ pio=testsys.iobus.master[3]
[testsys.tsunami.fake_uart2]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848936
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1309,9 +1385,10 @@ pio=testsys.iobus.master[4]
[testsys.tsunami.fake_uart3]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848680
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1325,9 +1402,10 @@ pio=testsys.iobus.master[5]
[testsys.tsunami.fake_uart4]
type=IsaFake
clock=1000
fake_mem=false
pio_addr=8804615848944
pio_latency=1000
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@ -1341,9 +1419,10 @@ pio=testsys.iobus.master[6]
[testsys.tsunami.fb]
type=BadDevice
clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
pio_latency=100000
system=testsys
pio=testsys.iobus.master[21]
@ -1387,16 +1466,15 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clock=1000
config_latency=20000
ctrl_offset=0
disks=testsys.disk0 testsys.disk2
io_shift=0
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=1000
pio_latency=30000
platform=testsys.tsunami
system=testsys
config=testsys.iobus.master[26]
@ -1405,9 +1483,10 @@ pio=testsys.iobus.master[25]
[testsys.tsunami.io]
type=TsunamiIO
clock=1000
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
pio_latency=100000
system=testsys
time=Thu Jan 1 00:00:00 2009
tsunami=testsys.tsunami
@ -1416,8 +1495,9 @@ pio=testsys.iobus.master[22]
[testsys.tsunami.pchip]
type=TsunamiPChip
clock=1000
pio_addr=8802535473152
pio_latency=1000
pio_latency=100000
system=testsys
tsunami=testsys.tsunami
pio=testsys.iobus.master[1]
@ -1425,7 +1505,8 @@ pio=testsys.iobus.master[1]
[testsys.tsunami.pciconfig]
type=PciConfigAll
bus=0
pio_latency=1
clock=1000
pio_latency=30000
platform=testsys.tsunami
size=16777216
system=testsys
@ -1433,8 +1514,9 @@ pio=testsys.iobus.default
[testsys.tsunami.uart]
type=Uart8250
clock=1000
pio_addr=8804615848952
pio_latency=1000
pio_latency=100000
platform=testsys.tsunami
system=testsys
terminal=testsys.terminal

12
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
View file

@ -1,14 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:20:01
gem5 executing on zizzer
gem5 compiled Jan 4 2013 21:09:21
gem5 started Jan 4 2013 21:17:35
gem5 executing on u200540
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /gem5/dist/binaries/vmlinux
0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /gem5/dist/binaries/vmlinux
0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 4300236804024 because checkpoint
Exiting @ tick 4321612280500 because checkpoint

756
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
View file

File diff suppressed because it is too large Load diff

64
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -126,11 +128,10 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.checker]
type=O3Checker
children=dtb itb tracer
children=dtb isa itb tracer
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@ -139,6 +140,7 @@ exitOnError=false
function_trace=false
function_trace_start=0
interrupts=Null
isa=system.cpu.checker.isa
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
@ -147,6 +149,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.checker.tracer
updateOnError=true
@ -166,6 +169,23 @@ num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.checker.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.checker.itb]
type=ArmTLB
children=walker
@ -189,21 +209,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -492,21 +507,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -515,6 +525,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -535,21 +562,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -576,7 +598,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 1 2012 15:18:10
gem5 started Nov 1 2012 22:40:56
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:26:41
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 13371000 because target called exit()
Exiting @ tick 13372000 because target called exit()

551
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
sim_ticks 13371000 # Number of ticks simulated
final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 13372000 # Number of ticks simulated
final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 32987 # Simulator instruction rate (inst/s)
host_op_rate 41149 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 95942804 # Simulator tick rate (ticks/s)
host_mem_usage 272856 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_inst_rate 16216 # Simulator instruction rate (inst/s)
host_op_rate 20228 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47166036 # Simulator tick rate (ticks/s)
host_mem_usage 230800 # Number of bytes of host memory used
host_seconds 0.28 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 13312500 # Total gap between requests
system.physmem.totGap 13314500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -172,9 +172,9 @@ system.physmem.avgQLat 6245.92 # Av
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 11.79 # Data bus utilization in percentage
@ -184,7 +184,7 @@ system.physmem.readRowHits 319 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33788.07 # Average gap between requests
system.physmem.avgGap 33793.15 # Average gap between requests
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
@ -273,7 +273,7 @@ system.cpu.itb.inst_accesses 0 # IT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.numCycles 26743 # number of cpu cycles simulated
system.cpu.numCycles 26745 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
@ -284,22 +284,21 @@ system.cpu.BPredUnit.BTBHits 707 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
@ -310,11 +309,11 @@ system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
@ -327,17 +326,17 @@ system.cpu.rename.IdleCycles 7146 # Nu
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
@ -352,13 +351,13 @@ system.cpu.iq.iqSquashedInstsIssued 116 # Nu
system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
@ -368,7 +367,7 @@ system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
@ -438,10 +437,10 @@ system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Ty
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
system.cpu.iq.rate 0.336088 # Inst issue rate
system.cpu.iq.rate 0.336063 # Inst issue rate
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
@ -464,7 +463,7 @@ system.cpu.iew.iewSquashCycles 963 # Nu
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
@ -482,13 +481,13 @@ system.cpu.iew.exec_nop 0 # nu
system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
system.cpu.iew.exec_branches 1446 # Number of branches executed
system.cpu.iew.exec_stores 1164 # Number of stores executed
system.cpu.iew.exec_rate 0.320233 # Inst execution rate
system.cpu.iew.exec_rate 0.320209 # Inst execution rate
system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3899 # num instructions producing a value
system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
@ -526,64 +525,64 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 22988 # The number of ROB reads
system.cpu.rob.rob_writes 23599 # The number of ROB writes
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
system.cpu.icache.overall_hits::total 1601 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 359 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
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system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
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system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
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system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
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system.cpu.icache.overall_misses::total 360 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
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system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
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system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
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system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
@ -592,46 +591,180 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
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system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
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system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
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system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
@ -654,16 +787,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
system.cpu.dcache.overall_misses::total 498 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
@ -686,16 +819,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.173580
system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
@ -722,14 +855,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
@ -738,148 +871,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
system.cpu.l2cache.overall_misses::total 399 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

42
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/arm/linux/hello
executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:20:14
gem5 started Oct 30 2012 18:52:17
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:17:24
gem5 started Jan 4 2013 23:26:30
gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 13371000 because target called exit()
Exiting @ tick 13372000 because target called exit()

551
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
sim_ticks 13371000 # Number of ticks simulated
final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 13372000 # Number of ticks simulated
final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 36978 # Simulator instruction rate (inst/s)
host_op_rate 46127 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 107546339 # Simulator tick rate (ticks/s)
host_mem_usage 272728 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_inst_rate 20879 # Simulator instruction rate (inst/s)
host_op_rate 26045 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 60729168 # Simulator tick rate (ticks/s)
host_mem_usage 230484 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 13312500 # Total gap between requests
system.physmem.totGap 13314500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -172,9 +172,9 @@ system.physmem.avgQLat 6245.92 # Av
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 11.79 # Data bus utilization in percentage
@ -184,7 +184,7 @@ system.physmem.readRowHits 319 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33788.07 # Average gap between requests
system.physmem.avgGap 33793.15 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -228,7 +228,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 26743 # number of cpu cycles simulated
system.cpu.numCycles 26745 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
@ -239,22 +239,21 @@ system.cpu.BPredUnit.BTBHits 707 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
@ -265,11 +264,11 @@ system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
@ -282,17 +281,17 @@ system.cpu.rename.IdleCycles 7146 # Nu
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
@ -307,13 +306,13 @@ system.cpu.iq.iqSquashedInstsIssued 116 # Nu
system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
@ -323,7 +322,7 @@ system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
@ -393,10 +392,10 @@ system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Ty
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
system.cpu.iq.rate 0.336088 # Inst issue rate
system.cpu.iq.rate 0.336063 # Inst issue rate
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
@ -419,7 +418,7 @@ system.cpu.iew.iewSquashCycles 963 # Nu
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
@ -437,13 +436,13 @@ system.cpu.iew.exec_nop 0 # nu
system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
system.cpu.iew.exec_branches 1446 # Number of branches executed
system.cpu.iew.exec_stores 1164 # Number of stores executed
system.cpu.iew.exec_rate 0.320233 # Inst execution rate
system.cpu.iew.exec_rate 0.320209 # Inst execution rate
system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3899 # num instructions producing a value
system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
@ -481,64 +480,64 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 22988 # The number of ROB reads
system.cpu.rob.rob_writes 23599 # The number of ROB writes
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
system.cpu.icache.overall_hits::total 1601 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
system.cpu.icache.overall_misses::total 359 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
system.cpu.icache.overall_misses::total 360 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
@ -547,46 +546,180 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
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system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
system.cpu.l2cache.overall_misses::total 399 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
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system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
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system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use
system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
@ -609,16 +742,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
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system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
@ -641,16 +774,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.173580
system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
@ -677,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
@ -693,148 +826,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
system.cpu.l2cache.overall_misses::total 399 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

22
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -116,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -132,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -426,21 +422,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -465,21 +456,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -506,7 +492,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello
executable=/gem5/dist/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864

6
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:08:52
gem5 started Oct 30 2012 13:57:41
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:13:46
gem5 started Jan 4 2013 21:58:53
gem5 executing on u200540
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

281
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
sim_ticks 16532500 # Number of ticks simulated
final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 48770 # Simulator instruction rate (inst/s)
host_op_rate 48763 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 156337427 # Simulator tick rate (ticks/s)
host_mem_usage 215260 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
host_inst_rate 25568 # Simulator instruction rate (inst/s)
host_op_rate 25564 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 81956278 # Simulator tick rate (ticks/s)
host_mem_usage 217336 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 16452500 # Total gap between requests
system.physmem.totGap 16453500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 2527972 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests
system.physmem.totQLat 2530972 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13086972 # Sum of mem lat for all requests
system.physmem.totBusLat 1904000 # Total cycles spent in databus access
system.physmem.totBankLat 8652000 # Total cycles spent in bank access
system.physmem.avgQLat 5310.87 # Average queueing delay per request
system.physmem.avgQLat 5317.17 # Average queueing delay per request
system.physmem.avgBankLat 18176.47 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 27487.34 # Average memory access latency
system.physmem.avgMemAccLat 27493.64 # Average memory access latency
system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s
@ -184,7 +184,7 @@ system.physmem.readRowHits 376 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 34564.08 # Average gap between requests
system.physmem.avgGap 34566.18 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -215,17 +215,16 @@ system.cpu.BPredUnit.BTBHits 517 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.CacheLines 1949 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total)
@ -471,50 +470,50 @@ system.cpu.fp_regfile_reads 3 # nu
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 147 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
system.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use
system.cpu.icache.tagsinuse 163.159030 # Cycle average of tags in use
system.cpu.icache.total_refs 1502 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 163.159030 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.079667 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.079667 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits
system.cpu.icache.overall_hits::total 1502 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses
system.cpu.icache.overall_misses::total 446 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency
system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses
system.cpu.icache.overall_misses::total 447 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21475500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 21475500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 21475500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 21475500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 21475500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 21475500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1949 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1949 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1949 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1949 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1949 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1949 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229348 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.229348 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.229348 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.229348 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.229348 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.229348 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48043.624161 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48043.624161 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48043.624161 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48043.624161 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@ -523,48 +522,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 109 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 109 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 109 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 109 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 109 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.173511 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.173511 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50161.242604 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50161.242604 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16956000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16956000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16956000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16956000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16956000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16956000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173422 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.173422 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.173422 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50165.680473 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50165.680473 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 223.784369 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 223.797313 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 165.662974 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 58.121395 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 165.672562 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 58.124752 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006829 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006830 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
@ -582,17 +581,17 @@ system.cpu.l2cache.demand_misses::total 476 # nu
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
system.cpu.l2cache.overall_misses::total 476 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16586500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5449500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 22036000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16588000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5450000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 22038000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16586500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 24738000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16586500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24738000 # number of overall miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16588000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8152000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 24740000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16588000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8152000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24740000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses)
@ -615,17 +614,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993737 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49511.940299 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60550 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51849.411765 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49516.417910 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60555.555556 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51854.117647 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52980.392157 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52980.392157 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51970.588235 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51970.588235 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51974.789916 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51974.789916 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -645,17 +644,17 @@ system.cpu.l2cache.demand_mshr_misses::total 476
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12363045 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4340573 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16703618 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12365045 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4341573 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16706618 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12363045 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6411627 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18774672 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12363045 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6411627 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18774672 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12365045 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6412627 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18777672 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12365045 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6412627 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18777672 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses
@ -667,27 +666,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36910.582090 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48239.700000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.689412 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 92.017211 # Cycle average of tags in use
system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 92.017211 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.022465 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.022465 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
@ -704,14 +703,14 @@ system.cpu.dcache.demand_misses::cpu.data 504 # n
system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses
system.cpu.dcache.overall_misses::total 504 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8905500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8905500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24508999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24508999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24508999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24508999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
@ -728,14 +727,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.172367
system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58976.821192 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58976.821192 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 48628.966270 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 48628.966270 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
@ -760,14 +759,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8297499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8297499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8297499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8297499 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
@ -776,14 +775,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222
system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61594.444444 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61594.444444 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

22
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -57,7 +58,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -117,6 +117,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -133,21 +134,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -427,21 +423,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -464,21 +455,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -505,7 +491,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello
executable=/gem5/dist/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864

6
tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:09:52
gem5 started Oct 30 2012 13:58:22
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:14:12
gem5 started Jan 4 2013 21:59:04
gem5 executing on u200540
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

297
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu
sim_ticks 14065500 # Number of ticks simulated
final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 60799 # Simulator instruction rate (inst/s)
host_op_rate 60790 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 147601989 # Simulator tick rate (ticks/s)
host_mem_usage 210652 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 28037 # Simulator instruction rate (inst/s)
host_op_rate 28032 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 68062430 # Simulator tick rate (ticks/s)
host_mem_usage 213288 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 13957000 # Total gap between requests
system.physmem.totGap 13958000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1923444 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11085444 # Sum of mem lat for all requests
system.physmem.totQLat 1923944 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11085944 # Sum of mem lat for all requests
system.physmem.totBusLat 1784000 # Total cycles spent in databus access
system.physmem.totBankLat 7378000 # Total cycles spent in bank access
system.physmem.avgQLat 4312.65 # Average queueing delay per request
system.physmem.avgQLat 4313.78 # Average queueing delay per request
system.physmem.avgBankLat 16542.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 24855.26 # Average memory access latency
system.physmem.avgMemAccLat 24856.38 # Average memory access latency
system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s
@ -184,7 +184,7 @@ system.physmem.readRowHits 369 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 31293.72 # Average gap between requests
system.physmem.avgGap 31295.96 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -215,16 +215,15 @@ system.cpu.BPredUnit.BTBHits 602 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7397 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 1812 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 306 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total)
@ -469,12 +468,12 @@ system.cpu.int_regfile_writes 7068 # nu
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 168.326699 # Cycle average of tags in use
system.cpu.icache.tagsinuse 168.326770 # Cycle average of tags in use
system.cpu.icache.total_refs 1375 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 168.326699 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 168.326770 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits
@ -483,36 +482,36 @@ system.cpu.icache.demand_hits::cpu.inst 1375 # nu
system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits
system.cpu.icache.overall_hits::total 1375 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
system.cpu.icache.overall_misses::total 437 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20187000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20187000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20187000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20187000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20187000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20187000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1812 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1812 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1812 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1812 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 1812 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.241170 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_avg_miss_latency::total 46194.508009 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 46194.508009 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 46194.508009 # average overall miss latency
system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 438 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 20259000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 20259000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::total 20259000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.241589 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.241589 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::total 46253.424658 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::total 46253.424658 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 46253.424658 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
@ -521,44 +520,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 52
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::total 87 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 16769000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16769000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16769000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16769000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16769000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193709 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.193709 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.193709 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47774.928775 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47774.928775 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16770000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16770000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16770000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 16770000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47777.777778 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47777.777778 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 198.645490 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 198.645596 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 167.286066 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 167.286173 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.359424 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005105 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy
@ -583,17 +582,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 2766000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
@ -616,17 +615,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
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@ -646,17 +645,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency::total 16537607 # number of overall MSHR miss cycles
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@ -668,17 +667,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42862 # average ReadReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42871.259259 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35966.323308 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46532.851064 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46532.851064 # average ReadExReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use
@ -705,14 +704,14 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
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system.cpu.dcache.demand_miss_latency::cpu.data 19350997 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19350997 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19350997 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19350997 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
@ -729,14 +728,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165714
system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.730769 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.730769 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42682.770393 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42682.770393 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 44481.602299 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 44481.602299 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50211.538462 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 50211.538462 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42685.791541 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42685.791541 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 44485.050575 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 44485.050575 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
@ -761,14 +760,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2814999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2814999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5860999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5860999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5860999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5860999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2815499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2815499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5861999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5861999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5861999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5861999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
@ -777,14 +776,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857
system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55381.818182 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55381.818182 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59893.595745 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59893.595745 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55390.909091 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55390.909091 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59904.234043 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59904.234043 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

28
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -433,21 +430,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -464,6 +456,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
@ -483,21 +478,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -524,7 +514,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/x86/linux/hello
executable=/gem5/dist/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18
gem5 started Dec 30 2012 01:12:54
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jan 4 2013 21:20:54
gem5 started Jan 4 2013 22:09:04
gem5 executing on u200540
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

408
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu
sim_ticks 15014000 # Number of ticks simulated
final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 27939 # Simulator instruction rate (inst/s)
host_op_rate 50607 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 77954156 # Simulator tick rate (ticks/s)
host_mem_usage 273052 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_inst_rate 15963 # Simulator instruction rate (inst/s)
host_op_rate 28915 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44538984 # Simulator tick rate (ticks/s)
host_mem_usage 232848 # Number of bytes of host memory used
host_seconds 0.34 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 14992500 # Total gap between requests
system.physmem.totGap 14993500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -184,7 +184,7 @@ system.physmem.readRowHits 352 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33316.67 # Average gap between requests
system.physmem.avgGap 33318.89 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 30029 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -197,18 +197,18 @@ system.cpu.BPredUnit.BTBHits 796 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.CacheLines 1881 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total)
@ -451,12 +451,12 @@ system.cpu.int_regfile_writes 17233 # nu
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.misc_regfile_reads 7157 # number of misc regfile reads
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use
system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use
system.cpu.icache.total_refs 1482 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits
@ -465,36 +465,36 @@ system.cpu.icache.demand_hits::cpu.inst 1482 # nu
system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits
system.cpu.icache.overall_hits::total 1482 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses
system.cpu.icache.overall_misses::total 398 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency
system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses
system.cpu.icache.overall_misses::total 399 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
@ -503,12 +503,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 44
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
@ -521,12 +521,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500
system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
@ -534,6 +534,131 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::cpu.data 33.036064 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 7804000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22950500 # number of overall miss cycles
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system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53683.098592 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336952 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17310134 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336952 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17310134 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.683168 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38184.556150 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency
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system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
@ -559,14 +684,14 @@ system.cpu.dcache.demand_misses::cpu.data 202 # n
system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
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system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
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system.cpu.dcache.demand_miss_latency::total 10557000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 10557000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
@ -583,14 +708,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081255
system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency
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@ -613,14 +738,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
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system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
@ -629,139 +754,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131
system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_misses::total 374 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
system.cpu.l2cache.overall_misses::total 450 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18957500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7803500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22950000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7803500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22950000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997333 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997783 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53676.056338 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 50688.502674 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 374 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336452 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14280524 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336452 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17309634 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336452 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17309634 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

28
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=262144
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@ -425,21 +422,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2
size=131072
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@ -448,6 +440,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb]
type=SparcTLB
size=64
@ -459,21 +454,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20
size=2097152
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@ -500,7 +490,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
executable=/gem5/dist/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 2 2012 11:45:16
gem5 started Nov 2 2012 11:45:40
gem5 executing on u200540-lin
gem5 compiled Jan 4 2013 21:16:54
gem5 started Jan 4 2013 21:59:36
gem5 executing on u200540
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -18,4 +18,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 23190500 because target called exit()
Exiting @ tick 23180500 because target called exit()

772
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000023 # Number of seconds simulated
sim_ticks 23190500 # Number of ticks simulated
final_tick 23190500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 23180500 # Number of ticks simulated
final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 24201 # Simulator instruction rate (inst/s)
host_op_rate 24200 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38875523 # Simulator tick rate (ticks/s)
host_mem_usage 222232 # Number of bytes of host memory used
host_seconds 0.60 # Real time elapsed on the host
host_inst_rate 21899 # Simulator instruction rate (inst/s)
host_op_rate 21897 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 35159544 # Simulator tick rate (ticks/s)
host_mem_usage 223288 # Number of bytes of host memory used
host_seconds 0.66 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu
system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 927276255 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 405683362 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1332959617 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 927276255 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 927276255 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 927276255 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 405683362 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1332959617 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 483 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 23130500 # Total gap between requests
system.physmem.totGap 23120500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -98,8 +98,8 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
@ -164,17 +164,17 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 2984483 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12938483 # Sum of mem lat for all requests
system.physmem.totQLat 3040483 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests
system.physmem.totBusLat 1932000 # Total cycles spent in databus access
system.physmem.totBankLat 8022000 # Total cycles spent in bank access
system.physmem.avgQLat 6179.05 # Average queueing delay per request
system.physmem.avgBankLat 16608.70 # Average bank access latency per request
system.physmem.totBankLat 8008000 # Total cycles spent in bank access
system.physmem.avgQLat 6295.00 # Average queueing delay per request
system.physmem.avgBankLat 16579.71 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26787.75 # Average memory access latency
system.physmem.avgRdBW 1332.96 # Average achieved read bandwidth in MB/s
system.physmem.avgMemAccLat 26874.71 # Average memory access latency
system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1332.96 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 8.33 # Data bus utilization in percentage
@ -184,59 +184,59 @@ system.physmem.readRowHits 394 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 47889.23 # Average gap between requests
system.physmem.avgGap 47868.53 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 46382 # number of cpu cycles simulated
system.cpu.numCycles 46362 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 6758 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 4516 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 6759 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 4517 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 4657 # Number of BTB lookups
system.cpu.BPredUnit.BTBLookups 4658 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 31427 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6758 # Number of branches that fetch encountered
system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9180 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3075 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 8320 # Number of cycles fetch has spent blocked
system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 5337 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 32520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.966390 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.158060 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 23340 71.77% 71.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4525 13.91% 85.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 464 1.43% 87.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 371 1.14% 88.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1896 5.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 32520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.145703 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.677569 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 9195 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8404 # Number of cycles decode is running
system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8405 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 29366 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13469 # Number of cycles rename is idle
system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8329 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8008 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename
@ -249,27 +249,27 @@ system.cpu.rename.CommittedMaps 13819 # Nu
system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2732 # count of insts added to the skid buffer
system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2330 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 22740 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21250 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 137 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8195 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5897 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 32520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.653444 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.275128 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 23284 71.60% 71.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3476 10.69% 82.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 913 2.81% 97.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle
@ -277,7 +277,7 @@ system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 32520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available
@ -313,69 +313,69 @@ system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 15763 74.18% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3339 15.71% 89.89% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2148 10.11% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 21250 # Type of FU issued
system.cpu.iq.rate 0.458152 # Inst issue rate
system.cpu.iq.FU_type_0::total 21285 # Type of FU issued
system.cpu.iq.rate 0.459104 # Inst issue rate
system.cpu.iq.fu_busy_cnt 153 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007200 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 75310 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 31611 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19572 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 21403 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 24529 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 387 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2330 # Number of dispatched store instructions
system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
@ -383,33 +383,33 @@ system.cpu.iew.memOrderViolationEvents 26 # Nu
system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20156 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3213 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1094 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1139 # number of nop insts executed
system.cpu.iew.exec_refs 5233 # number of memory reference insts executed
system.cpu.iew.exec_refs 5276 # number of memory reference insts executed
system.cpu.iew.exec_branches 4247 # Number of branches executed
system.cpu.iew.exec_stores 2020 # Number of stores executed
system.cpu.iew.exec_rate 0.434565 # Inst execution rate
system.cpu.iew.wb_sent 19807 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19572 # cumulative count of insts written-back
system.cpu.iew.exec_stores 2055 # Number of stores executed
system.cpu.iew.exec_rate 0.435853 # Inst execution rate
system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19647 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9210 # num instructions producing a value
system.cpu.iew.wb_consumers 11373 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.421974 # insts written-back per cycle
system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 9292 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 30632 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.494973 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.191764 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 23334 76.18% 76.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1377 4.50% 93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle
@ -419,7 +419,7 @@ system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 30632 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -432,66 +432,66 @@ system.cpu.commit.int_insts 12174 # Nu
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 54149 # The number of ROB reads
system.cpu.rob.rob_writes 50819 # The number of ROB writes
system.cpu.rob.rob_reads 54162 # The number of ROB reads
system.cpu.rob.rob_writes 50836 # The number of ROB writes
system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13862 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
system.cpu.cpi 3.212940 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.212940 # CPI: Total CPI of All Threads
system.cpu.ipc 0.311241 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.311241 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 32188 # number of integer regfile reads
system.cpu.int_regfile_writes 17920 # number of integer regfile writes
system.cpu.misc_regfile_reads 6865 # number of misc regfile reads
system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads
system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 32290 # number of integer regfile reads
system.cpu.int_regfile_writes 17967 # number of integer regfile writes
system.cpu.misc_regfile_reads 6967 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 191.561206 # Cycle average of tags in use
system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50461.538462 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50461.538462 # average overall mshr miss latency
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system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency
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system.cpu.l2cache.overall_miss_latency::total 24949000 # number of overall miss cycles
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system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency
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@ -558,40 +683,40 @@ system.cpu.dcache.demand_misses::cpu.data 539 # n
system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses
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system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
@ -616,155 +741,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
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system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency
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system.cpu.l2cache.tagsinuse 225.876311 # Cycle average of tags in use
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37107.190476 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38620.195000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40988.698795 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40988.698795 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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