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tests: Prune 00.gzip from the regressions

Browse source 
This patch prunes the 00.gzip regressions with the main motivation
being that it adds little (or no) coverage and requires a substantial
amount of run time.

A complete regression run, including compilation from a clean repo, is
almost 20% faster(!).
This commit is contained in:
Andreas Hansson 2013-06-27 05:49:49 -04:00
parent 3b92748937
commit f821c5472b
53 changed files with 0 additions and 11082 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

249
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -1,249 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
clock=500
cpu_id=0
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.isa]
type=AlphaISA
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[0]

6
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
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@ -1,6 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

44
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
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@ -1,44 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 26 2013 14:38:52
gem5 started Mar 26 2013 22:56:38
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 269668883500 because target called exit()

731
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,731 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.269772 # Number of seconds simulated
sim_ticks 269771922500 # Number of ticks simulated
final_tick 269771922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 152624 # Simulator instruction rate (inst/s)
host_op_rate 152624 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 68411173 # Simulator tick rate (ticks/s)
host_mem_usage 225196 # Number of bytes of host memory used
host_seconds 3943.39 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory
system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory
system.physmem.bytes_written::total 64896 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 199517 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6038405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6237921 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 199517 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 199517 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 240559 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 240559 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 240559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 199517 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6038405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6478480 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26294 # Total number of read requests seen
system.physmem.writeReqs 1014 # Total number of write requests seen
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1682816 # Total number of bytes read from memory
system.physmem.bytesWritten 64896 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1672 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1579 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1680 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1732 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1812 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1867 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1778 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1658 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1444 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1431 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1493 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1505 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 63 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 49 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 70 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 71 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 70 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 79 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 64 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 89 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 33 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 38 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 48 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 269771850500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 26294 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1014 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 17534 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 6823 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1475 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 445 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 8692 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 200.548550 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.216882 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 827.235747 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 7745 89.10% 89.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 118 1.36% 90.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 74 0.85% 91.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 56 0.64% 91.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 40 0.46% 92.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 23 0.26% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 20 0.23% 92.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 390 4.49% 97.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 4 0.05% 97.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 9 0.10% 97.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 7 0.08% 97.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 6 0.07% 97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 2 0.02% 97.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 4 0.05% 97.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 7 0.08% 97.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 4 0.05% 97.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 3 0.03% 97.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 2 0.02% 97.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 1 0.01% 97.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 9 0.10% 98.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 4 0.05% 98.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 3 0.03% 98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 3 0.03% 98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 4 0.05% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 3 0.03% 98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 2 0.02% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 2 0.02% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 2 0.02% 98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 4 0.05% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 2 0.02% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 2 0.02% 98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 2 0.02% 98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 3 0.03% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 1 0.01% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 3 0.03% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 2 0.02% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 1 0.01% 98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 2 0.02% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 1 0.01% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 1 0.01% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 2 0.02% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 4 0.05% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 2 0.02% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 1 0.01% 99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681 44 0.51% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 9 0.10% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 5 0.06% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 11 0.13% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8577 2 0.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 8692 # Bytes accessed per row activation
system.physmem.totQLat 332225750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 999160750 # Sum of mem lat for all requests
system.physmem.totBusLat 131400000 # Total cycles spent in databus access
system.physmem.totBankLat 535535000 # Total cycles spent in bank access
system.physmem.avgQLat 12641.77 # Average queueing delay per request
system.physmem.avgBankLat 20378.04 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 38019.82 # Average memory access latency
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.19 # Average write queue length over time
system.physmem.readRowHits 18015 # Number of row buffer hits during reads
system.physmem.writeRowHits 585 # Number of row buffer hits during writes
system.physmem.readRowHitRate 68.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 57.69 # Row buffer hit rate for writes
system.physmem.avgGap 9878857.86 # Average gap between requests
system.membus.throughput 6478480 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4966 # Transaction distribution
system.membus.trans_dist::ReadResp 4966 # Transaction distribution
system.membus.trans_dist::Writeback 1014 # Transaction distribution
system.membus.trans_dist::ReadExReq 21328 # Transaction distribution
system.membus.trans_dist::ReadExResp 21328 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 53602 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 53602 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1747712 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1747712 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1747712 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 40219500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 248608250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.branchPred.lookups 86401392 # Number of BP lookups
system.cpu.branchPred.condPredicted 81471121 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 45048026 # Number of BTB lookups
system.cpu.branchPred.BTBHits 34648141 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 76.913783 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114525360 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114527991 # DTB read accesses
system.cpu.dtb.write_hits 39455215 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39457517 # DTB write accesses
system.cpu.dtb.data_hits 153980575 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 153985508 # DTB accesses
system.cpu.itb.fetch_hits 24966979 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 24967001 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 539543846 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 37213743 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49187649 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541069671 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1004924517 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 255160482 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 154930401 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412134922 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 535782792 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 294264 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51002909 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 488540937 # Number of cycles cpu stages are processed.
system.cpu.activity 90.547032 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
system.cpu.comNops 36304520 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 349039879 # Number of Integer instructions committed
system.cpu.comFloats 24 # Number of Floating Point instructions committed
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
system.cpu.cpi 0.896465 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.896465 # CPI: Total CPI of All Threads
system.cpu.ipc 1.115492 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.115492 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 200810173 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338733673 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.781491 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 229113520 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310430326 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 57.535700 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 197979216 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341564630 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.306186 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 428164340 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111379506 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.643272 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 192742225 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 346801621 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.276819 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 729.672642 # Cycle average of tags in use
system.cpu.icache.total_refs 24965940 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29199.929825 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 729.672642 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.356285 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.356285 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 24965940 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24965940 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 24965940 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 24965940 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24965940 # number of overall hits
system.cpu.icache.overall_hits::total 24965940 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses
system.cpu.icache.overall_misses::total 1039 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 73110500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 73110500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 73110500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 73110500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 73110500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 73110500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24966979 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24966979 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24966979 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24966979 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24966979 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24966979 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70366.217517 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70366.217517 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70366.217517 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70366.217517 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 267 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 133.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 184 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 184 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 184 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 184 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60213000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 60213000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60213000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 60213000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60213000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 60213000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70424.561404 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70424.561404 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 211885535 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 202062 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 202062 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 254188 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 254188 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1710 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1349387 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54720 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 57160768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 57160768 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 883455500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1282500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 683092999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
system.cpu.l2cache.replacements 1042 # number of replacements
system.cpu.l2cache.tagsinuse 22873.227488 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21678.205650 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 718.794355 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 476.227482 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.661566 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021936 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.014533 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.698036 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232860 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232860 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 429942 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 429942 # number of overall hits
system.cpu.l2cache.overall_hits::total 429956 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4125 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4966 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21328 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21328 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25453 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26294 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59208000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 554748000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 613956000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1528945500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1528945500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 59208000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2083693500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2142901500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 59208000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2083693500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2142901500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70401.902497 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 134484.363636 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 123631.896899 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71687.242123 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71687.242123 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81497.737126 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81497.737126 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1014 # number of writebacks
system.cpu.l2cache.writebacks::total 1014 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4125 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4966 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21328 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21328 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25453 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26294 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48784500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 502370250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 551154750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1264256500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1264256500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48784500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1766626750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1815411250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48784500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1766626750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1815411250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58007.728894 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 121786.727273 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 110985.652437 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59276.842648 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59276.842648 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4093.048176 # Cycle average of tags in use
system.cpu.dcache.total_refs 151792699 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 333.320961 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 382930000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4093.048176 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999279 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114127941 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114127941 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 37664758 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 37664758 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 151792699 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 151792699 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 151792699 # number of overall hits
system.cpu.dcache.overall_hits::total 151792699 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 386101 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 386101 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1786563 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1786563 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2172664 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2172664 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2172664 # number of overall misses
system.cpu.dcache.overall_misses::total 2172664 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6056986500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6056986500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25183645000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 25183645000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 31240631500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 31240631500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31240631500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31240631500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003372 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003372 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045285 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.045285 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.014111 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.014111 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.014111 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.014111 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15687.570092 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15687.570092 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14096.141586 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14096.141586 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14378.952061 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14378.952061 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 376840 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 954 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 17814 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.154148 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 95.400000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 184869 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 184869 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1532400 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1532400 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1717269 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1717269 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1717269 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1717269 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2727636001 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2727636001 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4113048000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4113048000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6840684001 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6840684001 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6840684001 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6840684001 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13554.683157 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13554.683157 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16182.717390 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16182.717390 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

549
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,549 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.isa]
type=AlphaISA
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[0]

6
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,6 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

44
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -1,44 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 26 2013 14:38:52
gem5 started Mar 26 2013 22:56:39
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 133696809500 because target called exit()

949
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,949 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.133885 # Number of seconds simulated
sim_ticks 133884967500 # Number of ticks simulated
final_tick 133884967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 162173 # Simulator instruction rate (inst/s)
host_op_rate 162173 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38391719 # Simulator tick rate (ticks/s)
host_mem_usage 228276 # Number of bytes of host memory used
host_seconds 3487.34 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 61056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory
system.physmem.bytes_read::total 1697216 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 66944 # Number of bytes written to this memory
system.physmem.bytes_written::total 66944 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 954 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26519 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1046 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 456033 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12220640 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12676673 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 456033 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 456033 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 500011 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 500011 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 500011 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 456033 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12220640 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13176685 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26519 # Total number of read requests seen
system.physmem.writeReqs 1046 # Total number of write requests seen
system.physmem.cpureqs 27565 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1697216 # Total number of bytes read from memory
system.physmem.bytesWritten 66944 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1697216 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 66944 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1674 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1678 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1699 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1739 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1730 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1813 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1871 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1787 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1661 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1675 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1459 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1440 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1505 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1515 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 64 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 61 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 71 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 72 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 73 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 80 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 65 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 90 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 34 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 44 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 52 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 133884902000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 26519 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1046 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 11989 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 9624 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 4320 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 566 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 8244 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 213.286754 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 86.643190 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 848.319386 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 6744 81.80% 81.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 612 7.42% 89.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 105 1.27% 90.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 71 0.86% 91.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 43 0.52% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 25 0.30% 92.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 16 0.19% 92.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 389 4.72% 97.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 10 0.12% 97.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 9 0.11% 97.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 3 0.04% 97.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 3 0.04% 97.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 5 0.06% 97.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 8 0.10% 97.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 9 0.11% 97.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 7 0.08% 97.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 5 0.06% 97.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 3 0.04% 97.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 7 0.08% 97.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 6 0.07% 98.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 4 0.05% 98.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 1 0.01% 98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 3 0.04% 98.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 4 0.05% 98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 1 0.01% 98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 3 0.04% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 1 0.01% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 1 0.01% 98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 2 0.02% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 1 0.01% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 2 0.02% 98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 1 0.01% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 1 0.01% 98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 3 0.04% 98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 1 0.01% 98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 1 0.01% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 1 0.01% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 1 0.01% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 2 0.02% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 1 0.01% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 6 0.07% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553 2 0.02% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681 43 0.52% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 11 0.13% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 4 0.05% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 3 0.04% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 13 0.16% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 8244 # Bytes accessed per row activation
system.physmem.totQLat 457304500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1107883250 # Sum of mem lat for all requests
system.physmem.totBusLat 132520000 # Total cycles spent in databus access
system.physmem.totBankLat 518058750 # Total cycles spent in bank access
system.physmem.avgQLat 17254.17 # Average queueing delay per request
system.physmem.avgBankLat 19546.44 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 41800.61 # Average memory access latency
system.physmem.avgRdBW 12.68 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 12.68 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.10 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 7.87 # Average write queue length over time
system.physmem.readRowHits 18718 # Number of row buffer hits during reads
system.physmem.writeRowHits 577 # Number of row buffer hits during writes
system.physmem.readRowHitRate 70.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 55.16 # Row buffer hit rate for writes
system.physmem.avgGap 4857061.56 # Average gap between requests
system.membus.throughput 13176685 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 5255 # Transaction distribution
system.membus.trans_dist::ReadResp 5255 # Transaction distribution
system.membus.trans_dist::Writeback 1046 # Transaction distribution
system.membus.trans_dist::ReadExReq 21264 # Transaction distribution
system.membus.trans_dist::ReadExResp 21264 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 54084 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 54084 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1764160 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1764160 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1764160 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 40437500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 246430250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.branchPred.lookups 76481142 # Number of BP lookups
system.cpu.branchPred.condPredicted 70905485 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2712830 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 43152568 # Number of BTB lookups
system.cpu.branchPred.BTBHits 41951176 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 97.215943 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1604071 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 122621956 # DTB read hits
system.cpu.dtb.read_misses 28776 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 122650732 # DTB read accesses
system.cpu.dtb.write_hits 40755113 # DTB write hits
system.cpu.dtb.write_misses 25625 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 40780738 # DTB write accesses
system.cpu.dtb.data_hits 163377069 # DTB hits
system.cpu.dtb.data_misses 54401 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 163431470 # DTB accesses
system.cpu.itb.fetch_hits 65530786 # ITB hits
system.cpu.itb.fetch_misses 41 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 65530827 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 267769936 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 67189108 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 699431830 # Number of instructions fetch has processed
system.cpu.fetch.Branches 76481142 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 43555247 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 117843991 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 11666830 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 73504935 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1313 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 65530786 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 931341 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 267451900 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.615169 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.444449 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 149607909 55.94% 55.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10348918 3.87% 59.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 11847203 4.43% 64.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10573344 3.95% 68.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7008253 2.62% 70.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2869794 1.07% 71.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3587132 1.34% 73.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3111076 1.16% 74.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 68498271 25.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 267451900 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.285623 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.612063 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 84322843 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 57802490 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 102700565 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 13714405 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 8911597 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3873381 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 948 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 691440481 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3137 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 8911597 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 92312573 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12823003 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1534 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 103090752 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 50312441 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 681258889 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 435 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 38630282 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5470230 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 520856634 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 897283230 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 897280730 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2500 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 57001745 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 66 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 72 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 112491401 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 126996487 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 42388542 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 14811954 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 10030949 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 621209385 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 604684391 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 299599 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 55017699 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 29989465 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 267451900 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.260909 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.823825 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 52525807 19.64% 19.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 56031435 20.95% 40.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 53465406 19.99% 60.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 36379699 13.60% 74.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 31195818 11.66% 85.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 23840953 8.91% 94.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 10047725 3.76% 98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3411796 1.28% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 553261 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 267451900 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2753778 71.24% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 45 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 726781 18.80% 90.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 385136 9.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 439140797 72.62% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 7079 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 124346650 20.56% 93.19% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 41189817 6.81% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 604684391 # Type of FU issued
system.cpu.iq.rate 2.258224 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3865740 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006393 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1480982314 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 676230303 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 596557394 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3707 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2213 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1724 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 608548258 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1873 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 12279987 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 12482445 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 36037 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 5437 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2937221 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 6392 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 65545 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 8911597 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1457895 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 191973 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 664097895 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1705444 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 126996487 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 42388542 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 144321 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7199 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 5437 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1338458 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1807769 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3146227 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 599553495 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 122650887 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 5130896 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 42888454 # number of nop insts executed
system.cpu.iew.exec_refs 163450221 # number of memory reference insts executed
system.cpu.iew.exec_branches 66634078 # Number of branches executed
system.cpu.iew.exec_stores 40799334 # Number of stores executed
system.cpu.iew.exec_rate 2.239062 # Inst execution rate
system.cpu.iew.wb_sent 597495724 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 596559118 # cumulative count of insts written-back
system.cpu.iew.wb_producers 415919830 # num instructions producing a value
system.cpu.iew.wb_consumers 530239470 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.227879 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.784400 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 62116663 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2711961 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 258540303 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.327904 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.691623 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 79687582 30.82% 30.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 72573675 28.07% 58.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 25533783 9.88% 68.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9229698 3.57% 72.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 10307338 3.99% 76.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 20995746 8.12% 84.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 6840090 2.65% 87.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3701122 1.43% 88.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 29671269 11.48% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 258540303 # Number of insts commited each cycle
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 153965363 # Number of memory references committed
system.cpu.commit.loads 114514042 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 62547159 # Number of branches committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
system.cpu.commit.bw_lim_events 29671269 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 892778271 # The number of ROB reads
system.cpu.rob.rob_writes 1336872912 # The number of ROB writes
system.cpu.timesIdled 34547 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 318036 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.473466 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.473466 # CPI: Total CPI of All Threads
system.cpu.ipc 2.112083 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.112083 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 845093769 # number of integer regfile reads
system.cpu.int_regfile_writes 490581182 # number of integer regfile writes
system.cpu.fp_regfile_reads 382 # number of floating regfile reads
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 435443419 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 211400 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 211400 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 444967 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 254560 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 254560 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1944 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1374943 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1376887 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62208 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58237120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 58299328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 58299328 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 900430500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1458499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 697482499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.cpu.icache.replacements 40 # number of replacements
system.cpu.icache.tagsinuse 824.576664 # Cycle average of tags in use
system.cpu.icache.total_refs 65529394 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 67417.072016 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 824.576664 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.402625 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.402625 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 65529394 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 65529394 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 65529394 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 65529394 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 65529394 # number of overall hits
system.cpu.icache.overall_hits::total 65529394 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1391 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1391 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1391 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1391 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1391 # number of overall misses
system.cpu.icache.overall_misses::total 1391 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 90149500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 90149500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 90149500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 90149500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 90149500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 90149500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 65530785 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 65530785 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 65530785 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 65530785 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 65530785 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 65530785 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64809.130122 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 64809.130122 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 64809.130122 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 64809.130122 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 58.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 419 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 419 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 419 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 419 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 419 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 419 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 972 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 66407501 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 66407501 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 66407501 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 66407501 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 66407501 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 66407501 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68320.474280 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68320.474280 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68320.474280 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 68320.474280 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68320.474280 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68320.474280 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1077 # number of replacements
system.cpu.l2cache.tagsinuse 22914.008377 # Cycle average of tags in use
system.cpu.l2cache.total_refs 547130 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23515 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.267276 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21467.928297 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 816.924139 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 629.155942 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.655149 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.024931 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019200 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.699280 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 206127 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 206145 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 444967 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 444967 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 233296 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 233296 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 439423 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 439441 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 439423 # number of overall hits
system.cpu.l2cache.overall_hits::total 439441 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 954 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4301 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5255 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21264 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21264 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 954 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25565 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26519 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 954 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25565 # number of overall misses
system.cpu.l2cache.overall_misses::total 26519 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 65247500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 431865500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 497113000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1763135500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1763135500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 65247500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2195001000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2260248500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 65247500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2195001000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2260248500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 972 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 210428 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 211400 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 444967 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 444967 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254560 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254560 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 972 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 464988 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 465960 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 972 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 464988 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 465960 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.981481 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020439 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024858 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083532 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083532 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981481 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.054980 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.056913 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981481 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.054980 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.056913 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68393.605870 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100410.485934 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 94598.097050 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82916.455041 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82916.455041 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68393.605870 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85859.612752 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 85231.287002 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68393.605870 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85859.612752 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 85231.287002 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1046 # number of writebacks
system.cpu.l2cache.writebacks::total 1046 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 954 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4301 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5255 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21264 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21264 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 954 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25565 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26519 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 954 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25565 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26519 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53402000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 379654500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 433056500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1501204750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1501204750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53402000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1880859250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1934261250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53402000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1880859250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1934261250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020439 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024858 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083532 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083532 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054980 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.056913 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054980 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.056913 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55976.939203 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 88271.215996 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 82408.468126 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70598.417513 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70598.417513 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55976.939203 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73571.650694 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72938.694898 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55976.939203 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73571.650694 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72938.694898 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 460892 # number of replacements
system.cpu.dcache.tagsinuse 4090.586607 # Cycle average of tags in use
system.cpu.dcache.total_refs 146918843 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 464988 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 315.962655 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 315391000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4090.586607 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998678 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998678 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 109270363 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 109270363 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 37648463 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 37648463 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 146918826 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 146918826 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 146918826 # number of overall hits
system.cpu.dcache.overall_hits::total 146918826 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1007750 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1007750 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1802858 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1802858 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2810608 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2810608 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2810608 # number of overall misses
system.cpu.dcache.overall_misses::total 2810608 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15255049500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 15255049500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27585273680 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 27585273680 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 42840323180 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 42840323180 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 42840323180 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 42840323180 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 110278113 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 110278113 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 149729434 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 149729434 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 149729434 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 149729434 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009138 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.009138 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.045698 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.227273 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.227273 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.018771 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.018771 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018771 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018771 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15137.732076 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15137.732076 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15300.857683 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 15300.857683 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9700 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9700 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15242.368619 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15242.368619 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15242.368619 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15242.368619 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 382457 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1107 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 20340 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.803196 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 92.250000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 444967 # number of writebacks
system.cpu.dcache.writebacks::total 444967 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 797322 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 797322 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548298 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1548298 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2345620 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2345620 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2345620 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2345620 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210428 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 210428 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254560 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254560 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 464988 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 464988 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 464988 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 464988 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2709117501 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2709117501 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357981491 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357981491 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7067098992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7067098992 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7067098992 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7067098992 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.320437 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.320437 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17119.663305 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17119.663305 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

124
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -1,124 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.isa]
type=AlphaISA
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

7
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,7 +0,0 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

44
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,44 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 13:29:14
gem5 started Jan 23 2013 13:29:25
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 300930958000 because target called exit()

95
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,95 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.300931 # Number of seconds simulated
sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3984763 # Simulator instruction rate (inst/s)
host_op_rate 3984763 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1992397518 # Simulator tick rate (ticks/s)
host_mem_usage 217612 # Number of bytes of host memory used
host_seconds 151.04 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory
system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory
system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory
system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory
system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 9755262308 # Throughput (bytes/s)
system.membus.data_through_bus 2935660432 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.itb.fetch_hits 601861897 # ITB hits
system.cpu.itb.fetch_misses 20 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 601861917 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 601856964 # Number of instructions committed
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
system.cpu.num_int_insts 563959696 # number of integer instructions
system.cpu.num_fp_insts 1520 # number of float instructions
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 601861917 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

196
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -1,196 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
[system.cpu.isa]
type=AlphaISA
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

6
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,6 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here

44
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -1,44 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 13:29:14
gem5 started Jan 23 2013 14:50:54
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 762403375000 because target called exit()

445
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,445 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.762403 # Number of seconds simulated
sim_ticks 762403375000 # Number of ticks simulated
final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1417339 # Simulator instruction rate (inst/s)
host_op_rate 1417339 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1795416637 # Simulator tick rate (ticks/s)
host_mem_usage 225056 # Number of bytes of host memory used
host_seconds 424.64 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1628864 # Number of bytes read from this memory
system.physmem.bytes_read::total 1678976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 64384 # Number of bytes written to this memory
system.physmem.bytes_written::total 64384 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25451 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26234 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1006 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1006 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2136486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2202215 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 84449 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 84449 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 84449 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 2286664 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4910 # Transaction distribution
system.membus.trans_dist::ReadResp 4910 # Transaction distribution
system.membus.trans_dist::Writeback 1006 # Transaction distribution
system.membus.trans_dist::ReadExReq 21324 # Transaction distribution
system.membus.trans_dist::ReadExResp 21324 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 53474 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 53474 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1743360 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1743360 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1743360 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 35288000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 236106000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.itb.fetch_hits 601861898 # ITB hits
system.cpu.itb.fetch_misses 20 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 601861918 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 1524806750 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 601856964 # Number of instructions committed
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
system.cpu.num_int_insts 563959696 # number of integer instructions
system.cpu.num_fp_insts 1520 # number of float instructions
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1524806750 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 673.381157 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 673.381157 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.328799 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.328799 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 74969406 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 202027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 202027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 254163 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 254163 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1590 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1349267 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 57156928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 57156928 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 883425500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1192500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 683092500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

581
tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -1,581 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

43
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,43 +0,0 @@
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 26 2013 15:15:23
gem5 started Mar 27 2013 01:22:50
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 164562530500 because target called exit()

966
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,966 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.164717 # Number of seconds simulated
sim_ticks 164716794500 # Number of ticks simulated
final_tick 164716794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131424 # Simulator instruction rate (inst/s)
host_op_rate 138873 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37975042 # Simulator tick rate (ticks/s)
host_mem_usage 246336 # Number of bytes of host memory used
host_seconds 4337.50 # Real time elapsed on the host
sim_insts 570051585 # Number of instructions simulated
sim_ops 602359791 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1701568 # Number of bytes read from this memory
system.physmem.bytes_read::total 1748800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 47232 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 47232 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory
system.physmem.bytes_written::total 162368 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 738 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26587 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27325 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 286747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 10330264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10617011 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 286747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 286747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 985740 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 985740 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 985740 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 286747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 10330264 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11602751 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 27326 # Total number of read requests seen
system.physmem.writeReqs 2537 # Total number of write requests seen
system.physmem.cpureqs 29863 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1748800 # Total number of bytes read from memory
system.physmem.bytesWritten 162368 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1748800 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1621 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1642 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1816 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1757 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1715 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1788 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1779 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1795 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1657 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1653 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1640 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1650 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1673 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1647 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 156 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 166 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 164 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 163 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 163 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 154 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 158 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 164716777500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 27326 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 2537 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 15477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2877 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8554 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 414 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 9336 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 204.188518 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 86.332799 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 802.540236 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 7834 83.91% 83.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 317 3.40% 87.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 190 2.04% 89.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 83 0.89% 90.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 60 0.64% 90.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 70 0.75% 91.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 60 0.64% 92.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 493 5.28% 97.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 6 0.06% 97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 7 0.07% 97.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 3 0.03% 97.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 4 0.04% 97.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 3 0.03% 97.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 4 0.04% 97.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 5 0.05% 97.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 7 0.07% 97.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 5 0.05% 98.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 4 0.04% 98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 6 0.06% 98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 1 0.01% 98.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 2 0.02% 98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 7 0.07% 98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 2 0.02% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 2 0.02% 98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 4 0.04% 98.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 1 0.01% 98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 1 0.01% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 1 0.01% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 5 0.05% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 1 0.01% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 3 0.03% 98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 4 0.04% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 2 0.02% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 1 0.01% 98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 6 0.06% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 7 0.07% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 2 0.02% 98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 4 0.04% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 2 0.02% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 2 0.02% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 4 0.04% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 3 0.03% 99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 1 0.01% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 6 0.06% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 4 0.04% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065 3 0.03% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 1 0.01% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 60 0.64% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 9336 # Bytes accessed per row activation
system.physmem.totQLat 724618250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1428985750 # Sum of mem lat for all requests
system.physmem.totBusLat 136630000 # Total cycles spent in databus access
system.physmem.totBankLat 567737500 # Total cycles spent in bank access
system.physmem.avgQLat 26517.54 # Average queueing delay per request
system.physmem.avgBankLat 20776.46 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 52294.00 # Average memory access latency
system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.09 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 5.04 # Average write queue length over time
system.physmem.readRowHits 18612 # Number of row buffer hits during reads
system.physmem.writeRowHits 1908 # Number of row buffer hits during writes
system.physmem.readRowHitRate 68.11 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes
system.physmem.avgGap 5515747.83 # Average gap between requests
system.membus.throughput 11602751 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 5535 # Transaction distribution
system.membus.trans_dist::ReadResp 5534 # Transaction distribution
system.membus.trans_dist::Writeback 2537 # Transaction distribution
system.membus.trans_dist::ReadExReq 21791 # Transaction distribution
system.membus.trans_dist::ReadExResp 21791 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 57188 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 57188 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1911168 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1911168 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1911168 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 59882500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 257832500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.branchPred.lookups 85149850 # Number of BP lookups
system.cpu.branchPred.condPredicted 79935034 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2341119 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 47171100 # Number of BTB lookups
system.cpu.branchPred.BTBHits 46877755 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.378126 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1426315 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1039 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 329433590 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 68491080 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 666869934 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85149850 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 48304070 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 129626718 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 13098656 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 119406737 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 278 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 67075214 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 755042 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 328254094 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.164915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.193789 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 198627609 60.51% 60.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 20909439 6.37% 66.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 4965485 1.51% 68.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 14345312 4.37% 72.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8888539 2.71% 75.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9448384 2.88% 78.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4398392 1.34% 79.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 5788124 1.76% 81.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 60882810 18.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 328254094 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.258473 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.024292 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 92927462 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96288420 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 107921370 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 20389102 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10727740 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4734116 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 1608 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 703272688 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 6032 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 10727740 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 107129786 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 14463787 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 40672 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 114031737 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 81860372 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 694842750 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 59365311 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 20352093 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 658 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 721318867 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3230668466 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3230668338 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 93901494 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1663 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1606 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 170675033 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 172203367 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 80466872 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 21668199 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 28984539 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 680005400 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2870 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 645602000 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1370838 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 77464153 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 193377702 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 328254094 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.966775 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.724168 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 68222380 20.78% 20.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 85248644 25.97% 46.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 76005248 23.15% 69.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 40782290 12.42% 82.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 28865696 8.79% 91.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 14929305 4.55% 95.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5554109 1.69% 97.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6609349 2.01% 99.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2037073 0.62% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 328254094 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 217031 5.77% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2685741 71.41% 77.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 858362 22.82% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 403375767 62.48% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6562 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 165561645 25.64% 88.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 76658023 11.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 645602000 # Type of FU issued
system.cpu.iq.rate 1.959733 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3761134 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005826 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1624590030 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 757484567 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 637551440 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 649363114 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 30365020 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 23250774 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 122077 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12388 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 10245859 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 12881 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 36063 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 10727740 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 829837 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 90327 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 680011324 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 689748 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 172203367 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 80466872 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1542 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 33020 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 14329 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12388 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1357418 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1460538 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2817956 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 641515531 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 163488286 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4086469 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 3054 # number of nop insts executed
system.cpu.iew.exec_refs 239371647 # number of memory reference insts executed
system.cpu.iew.exec_branches 74671273 # Number of branches executed
system.cpu.iew.exec_stores 75883361 # Number of stores executed
system.cpu.iew.exec_rate 1.947329 # Inst execution rate
system.cpu.iew.wb_sent 638961836 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 637551456 # cumulative count of insts written-back
system.cpu.iew.wb_producers 418605320 # num instructions producing a value
system.cpu.iew.wb_consumers 649951687 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.935296 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.644056 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 77660016 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2339596 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 317526354 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.897039 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.237311 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 93315961 29.39% 29.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 104358414 32.87% 62.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 42989043 13.54% 75.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8780083 2.77% 78.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25952112 8.17% 86.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 12911096 4.07% 90.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7631938 2.40% 93.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1174119 0.37% 93.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 20413588 6.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 317526354 # Number of insts commited each cycle
system.cpu.commit.committedInsts 570051636 # Number of instructions committed
system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 219173606 # Number of memory references committed
system.cpu.commit.loads 148952593 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
system.cpu.commit.branches 70892524 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533522631 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
system.cpu.commit.bw_lim_events 20413588 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 977132012 # The number of ROB reads
system.cpu.rob.rob_writes 1370799549 # The number of ROB writes
system.cpu.timesIdled 46711 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1179496 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 570051585 # Number of Instructions Simulated
system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated
system.cpu.cpi 0.577901 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.577901 # CPI: Total CPI of All Threads
system.cpu.ipc 1.730399 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.730399 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3204308856 # number of integer regfile reads
system.cpu.int_regfile_writes 663036750 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 234764578 # number of misc regfile reads
system.cpu.misc_regfile_writes 2656 # number of misc regfile writes
system.cpu.toL2Bus.throughput 336903691 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 198317 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 198316 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 421602 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 247171 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 247171 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1633 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1310945 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1312578 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 52224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55441408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 55493632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 55493632 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 855147500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1225999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 667010989 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
system.cpu.icache.replacements 51 # number of replacements
system.cpu.icache.tagsinuse 691.196113 # Cycle average of tags in use
system.cpu.icache.total_refs 67074062 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 816 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 82198.605392 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 691.196113 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.337498 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.337498 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 67074062 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 67074062 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 67074062 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 67074062 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 67074062 # number of overall hits
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system.cpu.icache.overall_mshr_miss_latency::total 53391000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_miss_latency::total 49346829380 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 131860086 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 131860086 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 201277617 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 201277617 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 201277617 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 201277617 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048671 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.048671 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017088 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017088 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.018484 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.018484 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018484 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018484 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14974.125749 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14974.125749 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13090.634752 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 13090.634752 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.217391 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.217391 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13263.675804 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13263.675804 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 148047 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 158 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5424 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.294801 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 39.500000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 421602 # number of writebacks
system.cpu.dcache.writebacks::total 421602 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144306 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 144306 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3131471 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3131471 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 23 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 23 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3275777 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3275777 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3275777 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3275777 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197501 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 197501 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247171 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247171 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 444672 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 444672 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 444672 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 444672 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2858072011 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2858072011 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4363789439 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4363789439 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7221861450 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7221861450 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7221861450 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7221861450 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14471.177417 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14471.177417 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17654.941069 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17654.941069 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

156
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
View file

@ -1,156 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

43
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
View file

@ -1,43 +0,0 @@
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simout
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 19:43:25
gem5 started Jan 23 2013 19:49:37
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 301191365000 because target called exit()

105
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,105 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.301191 # Number of seconds simulated
sim_ticks 301191365000 # Number of ticks simulated
final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1664644 # Simulator instruction rate (inst/s)
host_op_rate 1758990 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 879528148 # Simulator tick rate (ticks/s)
host_mem_usage 233480 # Number of bytes of host memory used
host_seconds 342.45 # Real time elapsed on the host
sim_insts 570051636 # Number of instructions simulated
sim_ops 602359842 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 399862020 # Number of bytes read from this memory
system.physmem.bytes_read::total 2680160120 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2280298100 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2280298100 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory
system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 570074525 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147793178 # Number of read requests responded to by this memory
system.physmem.num_reads::total 717867703 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory
system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7570927872 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1327601208 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8898529080 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7570927872 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7570927872 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 784748962 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 784748962 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 9683278042 # Throughput (bytes/s)
system.membus.data_through_bus 2916519731 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 602382731 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 570051636 # Number of instructions committed
system.cpu.committedOps 602359842 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1995305 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522631 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2770242967 # number of times the integer registers were read
system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 219173606 # number of memory refs
system.cpu.num_load_insts 148952593 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 602382731 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

228
tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -1,228 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

43
tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -1,43 +0,0 @@
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 19:43:25
gem5 started Jan 23 2013 19:54:17
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 793670137000 because target called exit()

463
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,463 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.793670 # Number of seconds simulated
sim_ticks 793670137000 # Number of ticks simulated
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 583678 # Simulator instruction rate (inst/s)
host_op_rate 616385 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 814802699 # Simulator tick rate (ticks/s)
host_mem_usage 241980 # Number of bytes of host memory used
host_seconds 974.06 # Real time elapsed on the host
sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1675072 # Number of bytes read from this memory
system.physmem.bytes_read::total 1713664 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 38592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 38592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 159552 # Number of bytes written to this memory
system.physmem.bytes_written::total 159552 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 603 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26173 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26776 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2493 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2493 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 48625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2110539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2159164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 48625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 48625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 201031 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 201031 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 201031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 2360195 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4941 # Transaction distribution
system.membus.trans_dist::ReadResp 4941 # Transaction distribution
system.membus.trans_dist::Writeback 2493 # Transaction distribution
system.membus.trans_dist::ReadExReq 21835 # Transaction distribution
system.membus.trans_dist::ReadExResp 21835 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 56045 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 56045 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1873216 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1873216 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1873216 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 49213000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 240984000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1587340274 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 568539335 # Number of instructions committed
system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1995305 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522631 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read
system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 219173606 # number of memory refs
system.cpu.num_load_insts 148952593 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1587340274 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.tagsinuse 577.773656 # Cycle average of tags in use
system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 577.773656 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits
system.cpu.icache.overall_hits::total 570073883 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
system.cpu.icache.overall_misses::total 643 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 33685000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 33685000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 33685000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 33685000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 33685000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 33685000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52387.247278 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52387.247278 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52387.247278 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52387.247278 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32399000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32399000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32399000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32399000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32399000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32399000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50387.247278 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50387.247278 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2512 # number of replacements
system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23599 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.483537 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20978.651717 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 539.196236 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 506.927350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.640218 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.016455 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.015470 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.672143 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 40 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 185478 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 185518 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 418626 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 418626 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 225913 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 225913 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 40 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 411391 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 411431 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 40 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 411391 # number of overall hits
system.cpu.l2cache.overall_hits::total 411431 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 603 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4338 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4941 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21835 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21835 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 603 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26173 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26776 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 603 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26173 # number of overall misses
system.cpu.l2cache.overall_misses::total 26776 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31356000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 226076000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 257432000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1135420000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1135420000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 31356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1361496000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1392852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 31356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1361496000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1392852000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 418626 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 418626 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.937792 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022854 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.025943 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088134 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.088134 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.937792 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.061104 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.937792 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.061104 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52115.260489 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52101.194090 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52018.673439 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52018.673439 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2493 # number of writebacks
system.cpu.l2cache.writebacks::total 2493 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 603 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4338 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4941 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21835 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21835 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 603 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26173 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26776 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 603 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26173 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26776 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 174020000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198140000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 873400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 873400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1047420000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1071540000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1047420000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1071540000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022854 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025943 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088134 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088134 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061104 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061104 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40115.260489 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40101.194090 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
system.cpu.dcache.writebacks::total 418626 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 69093329 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 190459 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 190459 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 418626 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 247748 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 247748 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1286 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1293754 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1295040 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 41152 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 54796160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 54837312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 54837312 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 847042500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 964500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 656346000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

549
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -1,549 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

43
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,43 +0,0 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 26 2013 15:04:14
gem5 started Mar 26 2013 23:39:12
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 387290918500 because target called exit()

921
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,921 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.387399 # Number of seconds simulated
sim_ticks 387398892000 # Number of ticks simulated
final_tick 387398892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 157866 # Simulator instruction rate (inst/s)
host_op_rate 158364 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 43646663 # Simulator tick rate (ticks/s)
host_mem_usage 236680 # Number of bytes of host memory used
host_seconds 8875.80 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 76288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1678592 # Number of bytes read from this memory
system.physmem.bytes_read::total 1754880 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 76288 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 76288 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162048 # Number of bytes written to this memory
system.physmem.bytes_written::total 162048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1192 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26228 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27420 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2532 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2532 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 196924 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4332981 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4529905 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 196924 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 196924 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 418298 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 418298 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 418298 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 196924 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4332981 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4948202 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 27421 # Total number of read requests seen
system.physmem.writeReqs 2532 # Total number of write requests seen
system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1754880 # Total number of bytes read from memory
system.physmem.bytesWritten 162048 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1754880 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 162048 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1884 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1775 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1871 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1665 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1646 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1602 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1689 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1531 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1534 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1701 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1777 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1778 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1794 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1801 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 168 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 163 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 167 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 156 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 152 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 149 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 148 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 150 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 163 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 163 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 162 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 387398864000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 27421 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 2532 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 9983 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 11822 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5095 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 520 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 9394 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 203.806685 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 84.980950 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 820.153394 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 8091 86.13% 86.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 139 1.48% 87.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 97 1.03% 88.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 115 1.22% 89.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 131 1.39% 91.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 46 0.49% 91.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 57 0.61% 92.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 495 5.27% 97.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 5 0.05% 97.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 8 0.09% 97.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 8 0.09% 97.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 6 0.06% 97.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 6 0.06% 97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 3 0.03% 98.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 3 0.03% 98.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 5 0.05% 98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 1 0.01% 98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 1 0.01% 98.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 7 0.07% 98.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 3 0.03% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 3 0.03% 98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 2 0.02% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 3 0.03% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 1 0.01% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 3 0.03% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 3 0.03% 98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 3 0.03% 98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 3 0.03% 98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 2 0.02% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 1 0.01% 98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 2 0.02% 98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 1 0.01% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 1 0.01% 98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 2 0.02% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 2 0.02% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 1 0.01% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 1 0.01% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 3 0.03% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 2 0.02% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 1 0.01% 99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 2 0.02% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 1 0.01% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 2 0.02% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337 2 0.02% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 2 0.02% 99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 1 0.01% 99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 3 0.03% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 4 0.04% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425 2 0.02% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 1 0.01% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 3 0.03% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 3 0.03% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 63 0.67% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 9394 # Bytes accessed per row activation
system.physmem.totQLat 539470500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1246251750 # Sum of mem lat for all requests
system.physmem.totBusLat 137105000 # Total cycles spent in databus access
system.physmem.totBankLat 569676250 # Total cycles spent in bank access
system.physmem.avgQLat 19673.63 # Average queueing delay per request
system.physmem.avgBankLat 20775.18 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 45448.81 # Average memory access latency
system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 16.43 # Average write queue length over time
system.physmem.readRowHits 18651 # Number of row buffer hits during reads
system.physmem.writeRowHits 1906 # Number of row buffer hits during writes
system.physmem.readRowHitRate 68.02 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.28 # Row buffer hit rate for writes
system.physmem.avgGap 12933558.04 # Average gap between requests
system.membus.throughput 4948202 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 5633 # Transaction distribution
system.membus.trans_dist::ReadResp 5632 # Transaction distribution
system.membus.trans_dist::Writeback 2532 # Transaction distribution
system.membus.trans_dist::ReadExReq 21788 # Transaction distribution
system.membus.trans_dist::ReadExResp 21788 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 57373 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 57373 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1916928 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1916928 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1916928 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 57596000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 256936750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.branchPred.lookups 97761890 # Number of BP lookups
system.cpu.branchPred.condPredicted 88051950 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 3615398 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 65795011 # Number of BTB lookups
system.cpu.branchPred.BTBHits 65493795 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.542190 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1333 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 774797785 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 164870049 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1642248421 # Number of instructions fetch has processed
system.cpu.fetch.Branches 97761890 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 65495128 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 329214190 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 20840770 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 263425370 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2796 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 161945451 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 735894 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 774503521 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.126508 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.146615 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 445289331 57.49% 57.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 74062894 9.56% 67.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 37897346 4.89% 71.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 9078563 1.17% 73.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 28105911 3.63% 76.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 18772818 2.42% 79.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 11485706 1.48% 80.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3794812 0.49% 81.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 146016140 18.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 774503521 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.126177 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.119583 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 216045393 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 214430589 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 284206110 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 42830421 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 16991008 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 1636611354 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 16991008 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 239885098 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 36871695 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 52473274 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 302059993 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 126222453 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1625714374 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 30924746 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 73227733 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 3172404 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1356421780 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2746534895 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2712238159 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 34296736 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 111651341 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2642938 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2663443 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 271529341 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 436963345 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 179743092 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 254343956 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 83161988 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1512506564 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2608276 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1459339733 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 53312 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 109205745 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 130222811 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 364605 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 774503521 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.884226 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.431683 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 145873373 18.83% 18.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 184398139 23.81% 42.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 209824996 27.09% 69.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 131195131 16.94% 86.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 70728709 9.13% 95.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 20383962 2.63% 98.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8004266 1.03% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3913593 0.51% 99.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 181352 0.02% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 774503521 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 114122 6.75% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 97466 5.77% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1164668 68.90% 81.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 314034 18.58% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 866437474 59.37% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2644764 0.18% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 419138356 28.72% 88.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 171119139 11.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1459339733 # Type of FU issued
system.cpu.iq.rate 1.883510 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1690290 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3677004243 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1615280670 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1443165364 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 17922346 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9279147 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 8546420 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1451856157 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 9173866 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 215403822 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 34450502 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 58568 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 246048 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 12894950 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 138899 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 16991008 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 3096733 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 244441 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1608794631 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 4137633 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 436963345 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 179743092 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2525201 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 147095 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1875 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 246048 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2270642 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1473051 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3743693 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1454012420 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 416588335 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 5327313 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 93679791 # number of nop insts executed
system.cpu.iew.exec_refs 587032224 # number of memory reference insts executed
system.cpu.iew.exec_branches 89032109 # Number of branches executed
system.cpu.iew.exec_stores 170443889 # Number of stores executed
system.cpu.iew.exec_rate 1.876635 # Inst execution rate
system.cpu.iew.wb_sent 1452595352 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1451711784 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1153369073 # num instructions producing a value
system.cpu.iew.wb_consumers 1204594740 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.873665 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.957475 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 119176384 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3615398 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 757512513 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.966335 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.509470 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 240122511 31.70% 31.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 275742858 36.40% 68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 42578645 5.62% 73.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 54721179 7.22% 80.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19701382 2.60% 83.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13286584 1.75% 85.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 30581396 4.04% 89.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10490891 1.38% 90.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 70287067 9.28% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 757512513 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 569360985 # Number of memory references committed
system.cpu.commit.loads 402512843 # Number of loads committed
system.cpu.commit.membars 51356 # Number of memory barriers committed
system.cpu.commit.branches 86248928 # Number of branches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
system.cpu.commit.bw_lim_events 70287067 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2295860242 # The number of ROB reads
system.cpu.rob.rob_writes 3234413109 # The number of ROB writes
system.cpu.timesIdled 27770 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 294264 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
system.cpu.cpi 0.552957 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.552957 # CPI: Total CPI of All Threads
system.cpu.ipc 1.808458 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.808458 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1979095871 # number of integer regfile reads
system.cpu.int_regfile_writes 1275125772 # number of integer regfile writes
system.cpu.fp_regfile_reads 16962854 # number of floating regfile reads
system.cpu.fp_regfile_writes 10491602 # number of floating regfile writes
system.cpu.misc_regfile_reads 592684666 # number of misc regfile reads
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
system.cpu.toL2Bus.throughput 150116939 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 202209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 202208 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 444002 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2671 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1370676 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1373347 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 85440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58069696 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 58155136 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 58155136 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 898339500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2002500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 695005500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.icache.replacements 199 # number of replacements
system.cpu.icache.tagsinuse 1032.766528 # Cycle average of tags in use
system.cpu.icache.total_refs 161943463 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1335 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 121305.964794 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1032.766528 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.504281 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.504281 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 161943463 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 161943463 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 161943463 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 161943463 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 161943463 # number of overall hits
system.cpu.icache.overall_hits::total 161943463 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1988 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1988 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1988 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1988 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1988 # number of overall misses
system.cpu.icache.overall_misses::total 1988 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115233000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 115233000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 115233000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 115233000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 115233000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 115233000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 161945451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 161945451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 161945451 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 161945451 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 161945451 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 161945451 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57964.285714 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 57964.285714 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 57964.285714 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 57964.285714 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 57964.285714 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 57964.285714 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 652 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 652 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 652 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 652 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 652 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1336 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1336 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1336 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1336 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1336 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1336 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 82779000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 82779000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 82779000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 82779000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 82779000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 82779000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61960.329341 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61960.329341 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61960.329341 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 61960.329341 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61960.329341 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61960.329341 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2555 # number of replacements
system.cpu.l2cache.tagsinuse 22446.824248 # Cycle average of tags in use
system.cpu.l2cache.total_refs 550534 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24268 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.685594 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20740.710911 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1057.791119 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 648.322219 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.632956 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.032281 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019785 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.685023 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 143 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 196433 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 196576 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 444002 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 444002 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 240676 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 240676 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 143 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 437109 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 437252 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 143 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 437109 # number of overall hits
system.cpu.l2cache.overall_hits::total 437252 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1193 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4440 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5633 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21788 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21788 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1193 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26228 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 27421 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1193 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26228 # number of overall misses
system.cpu.l2cache.overall_misses::total 27421 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 80005000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 475615000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 555620000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1881812500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1881812500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 80005000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2357427500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2437432500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 80005000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2357427500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2437432500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1336 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 200873 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202209 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 444002 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 444002 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 262464 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 262464 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1336 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 463337 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 464673 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1336 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 463337 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 464673 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.892964 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022104 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.027857 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083013 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083013 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.892964 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.056607 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.059011 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.892964 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.056607 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.059011 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67062.028500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 107120.495495 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 98636.605716 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86369.217000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86369.217000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67062.028500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89882.091658 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 88889.263703 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67062.028500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89882.091658 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 88889.263703 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2532 # number of writebacks
system.cpu.l2cache.writebacks::total 2532 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1193 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4440 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5633 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21788 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21788 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1193 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26228 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27421 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1193 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26228 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27421 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65201250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 420951000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 486152250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1612083500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1612083500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65201250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2033034500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 2098235750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65201250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2033034500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 2098235750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.892964 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022104 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027857 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083013 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083013 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.892964 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056607 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059011 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.892964 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056607 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059011 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54653.185247 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 94808.783784 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 86304.322741 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73989.512576 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73989.512576 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54653.185247 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77513.897362 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76519.300901 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54653.185247 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77513.897362 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76519.300901 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 459241 # number of replacements
system.cpu.dcache.tagsinuse 4093.680719 # Cycle average of tags in use
system.cpu.dcache.total_refs 365075170 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 463337 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 787.925786 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 357850000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4093.680719 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999434 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999434 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 200118468 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 200118468 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 164955383 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 164955383 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 365073851 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 365073851 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 365073851 # number of overall hits
system.cpu.dcache.overall_hits::total 365073851 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 907674 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 907674 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1891433 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1891433 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 2799107 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2799107 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2799107 # number of overall misses
system.cpu.dcache.overall_misses::total 2799107 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14763566000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 14763566000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 33756143071 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 33756143071 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 142000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 142000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 48519709071 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 48519709071 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 48519709071 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 48519709071 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 201026142 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 201026142 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 367872958 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 367872958 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 367872958 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 367872958 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004515 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004515 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.007609 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.007609 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007609 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007609 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16265.273656 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16265.273656 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17846.861650 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17846.861650 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20285.714286 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 20285.714286 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17333.995832 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17333.995832 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 694627 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 38063 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.249402 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 46 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 444002 # number of writebacks
system.cpu.dcache.writebacks::total 444002 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 706801 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 706801 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628976 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1628976 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2335777 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2335777 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2335777 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2335777 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200873 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 200873 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262457 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 262457 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 463330 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 463330 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 463330 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 463330 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643681500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643681500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4650895000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4650895000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 128000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 128000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7294576500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7294576500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7294576500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7294576500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13160.959910 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13160.959910 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17720.598041 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17720.598041 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 18285.714286 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 18285.714286 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

124
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -1,124 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

3
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
View file

@ -1,3 +0,0 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

43
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -1,43 +0,0 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 15:49:24
gem5 started Jan 23 2013 16:12:25
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 744764112500 because target called exit()

65
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,65 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.744764 # Number of seconds simulated
sim_ticks 744764112500 # Number of ticks simulated
final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3917871 # Simulator instruction rate (inst/s)
host_op_rate 3929519 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1964765726 # Simulator tick rate (ticks/s)
host_mem_usage 224984 # Number of bytes of host memory used
host_seconds 379.06 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1385817592 # Number of bytes read from this memory
system.physmem.bytes_read::total 7326269584 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5940451992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5940451992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory
system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1485112998 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 402512843 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1887625841 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory
system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory
system.physmem.num_other::total 1326 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1860747005 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9837033580 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 825324492 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 825324492 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 10662372316 # Throughput (bytes/s)
system.membus.data_through_bus 7940952255 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528226 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108088 # Number of instructions committed
system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481286 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343145 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365766 # number of memory refs
system.cpu.num_load_insts 402515345 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1489528226 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

196
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -1,196 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

43
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -1,43 +0,0 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2013 15:49:24
gem5 started Jan 23 2013 15:49:34
gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2061066313000 because target called exit()

433
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,433 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.061066 # Number of seconds simulated
sim_ticks 2061066313000 # Number of ticks simulated
final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 684045 # Simulator instruction rate (inst/s)
host_op_rate 686079 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 949333559 # Simulator tick rate (ticks/s)
host_mem_usage 233488 # Number of bytes of host memory used
host_seconds 2171.07 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1672512 # Number of bytes read from this memory
system.physmem.bytes_read::total 1737728 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 161152 # Number of bytes written to this memory
system.physmem.bytes_written::total 161152 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26133 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27152 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2518 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2518 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 31642 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 811479 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 843121 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 31642 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 31642 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 78189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 78189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 78189 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 921310 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 5293 # Transaction distribution
system.membus.trans_dist::ReadResp 5293 # Transaction distribution
system.membus.trans_dist::Writeback 2518 # Transaction distribution
system.membus.trans_dist::ReadExReq 21859 # Transaction distribution
system.membus.trans_dist::ReadExResp 21859 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 56822 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 56822 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1898880 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1898880 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1898880 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 49814000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 244368000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4122132626 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108088 # Number of instructions committed
system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481286 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343144 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365766 # number of memory refs
system.cpu.num_load_insts 402515345 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4122132626 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.tagsinuse 906.468716 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 906.468716 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1485111892 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1485111892 # number of overall hits
system.cpu.icache.overall_hits::total 1485111892 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
system.cpu.icache.overall_misses::total 1107 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 57199000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 57199000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 57199000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 57199000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 57199000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 57199000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1485112999 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1485112999 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1485112999 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51670.280036 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51670.280036 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51670.280036 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51670.280036 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54985000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 54985000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54985000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 54985000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54985000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 54985000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49670.280036 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49670.280036 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2539 # number of replacements
system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use
system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23989 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.292926 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20839.325928 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 913.017348 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 501.206640 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.635966 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.027863 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 435341 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 435341 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.368297 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2518 # number of writebacks
system.cpu.l2cache.writebacks::total 2518 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency::total 1086090000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084159 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059763 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.813543 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.889288 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
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system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
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system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
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system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
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system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
system.cpu.dcache.writebacks::total 435341 # number of writebacks
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system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 27625902 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 194593 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 194593 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 435341 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 259735 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 259735 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2214 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1341783 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1343997 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 70848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56867968 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 56938816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 56938816 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 880175500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 679831500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

573
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -1,573 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=openmap
banks_per_rank=8
channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

45
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,45 +0,0 @@
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 26 2013 15:13:59
gem5 started Mar 27 2013 00:17:33
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 607388314000 because target called exit()

892
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,892 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.602519 # Number of seconds simulated
sim_ticks 602519213000 # Number of ticks simulated
final_tick 602519213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 94132 # Simulator instruction rate (inst/s)
host_op_rate 173444 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64448799 # Simulator tick rate (ticks/s)
host_mem_usage 251596 # Number of bytes of host memory used
host_seconds 9348.80 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 57152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory
system.physmem.bytes_read::total 1750464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 57152 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 57152 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 893 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27351 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 94855 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2810387 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2905242 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 94855 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 94855 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 269057 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 269057 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 269057 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 94855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2810387 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3174299 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 27351 # Total number of read requests seen
system.physmem.writeReqs 2533 # Total number of write requests seen
system.physmem.cpureqs 29884 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1750464 # Total number of bytes read from memory
system.physmem.bytesWritten 162112 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1750464 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1686 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1661 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1729 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1834 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1605 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1565 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1603 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1748 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1766 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1802 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1763 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1767 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1734 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1727 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1630 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 168 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 147 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 150 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 602519006000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 27351 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 2533 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 26975 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 303 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 9709 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 196.647235 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 83.287733 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 790.384353 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 8486 87.40% 87.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 125 1.29% 88.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 100 1.03% 89.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 90 0.93% 90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 83 0.85% 91.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 70 0.72% 92.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 47 0.48% 92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 479 4.93% 97.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 8 0.08% 97.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 3 0.03% 97.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 4 0.04% 97.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 2 0.02% 97.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 5 0.05% 97.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 2 0.02% 97.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 8 0.08% 97.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 3 0.03% 98.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 9 0.09% 98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 2 0.02% 98.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 4 0.04% 98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 4 0.04% 98.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 3 0.03% 98.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 1 0.01% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 1 0.01% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 5 0.05% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 7 0.07% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 4 0.04% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 4 0.04% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 9 0.09% 98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 13 0.13% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 1 0.01% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 1 0.01% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.01% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 3 0.03% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 1 0.01% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 5 0.05% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 4 0.04% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 5 0.05% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 1 0.01% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 1 0.01% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 1 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 1 0.01% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 2 0.02% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 1 0.01% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 4 0.04% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 2 0.02% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425 1 0.01% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 60 0.62% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 9709 # Bytes accessed per row activation
system.physmem.totQLat 62966000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 815954750 # Sum of mem lat for all requests
system.physmem.totBusLat 136755000 # Total cycles spent in databus access
system.physmem.totBankLat 616233750 # Total cycles spent in bank access
system.physmem.avgQLat 2302.15 # Average queueing delay per request
system.physmem.avgBankLat 22530.57 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29832.72 # Average memory access latency
system.physmem.avgRdBW 2.91 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.91 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 7.81 # Average write queue length over time
system.physmem.readRowHits 18284 # Number of row buffer hits during reads
system.physmem.writeRowHits 1888 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.54 # Row buffer hit rate for writes
system.physmem.avgGap 20161926.32 # Average gap between requests
system.membus.throughput 3174299 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 5448 # Transaction distribution
system.membus.trans_dist::ReadResp 5448 # Transaction distribution
system.membus.trans_dist::Writeback 2533 # Transaction distribution
system.membus.trans_dist::ReadExReq 21903 # Transaction distribution
system.membus.trans_dist::ReadExResp 21903 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 57235 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 57235 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 57235 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 57235 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1912576 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 1912576 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1912576 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 54010000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 256633000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.branchPred.lookups 156229699 # Number of BP lookups
system.cpu.branchPred.condPredicted 156229699 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 25700090 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 80130735 # Number of BTB lookups
system.cpu.branchPred.BTBHits 79954590 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.780178 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 2760708 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 5575 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1205038430 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 175276442 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1436709759 # Number of instructions fetch has processed
system.cpu.fetch.Branches 156229699 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 82715298 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 393071073 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83888584 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 578277772 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 906 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 184712777 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11835246 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1204659879 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.045547 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.246119 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 818506882 67.95% 67.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 26870857 2.23% 70.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 12535228 1.04% 71.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 20195142 1.68% 72.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26380482 2.19% 75.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 18063889 1.50% 76.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 31357703 2.60% 79.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 38322925 3.18% 82.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 212426771 17.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1204659879 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.129647 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.192252 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 284492310 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 500755512 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 268717714 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 92660799 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 58033544 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2310812595 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 58033544 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 333444734 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 124733131 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3847 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 298470128 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 389974495 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2217748571 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 12521 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 243097280 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 121807098 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2582807342 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5647663149 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5647656949 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6200 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 695912082 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 105 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 105 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 737293343 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 525275195 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 216586351 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 339249104 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 144696192 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1968455796 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 343 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1773948225 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 152074 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 346640912 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 707550278 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 294 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1204659879 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.472572 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.418644 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 354366536 29.42% 29.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 362605011 30.10% 59.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234071294 19.43% 78.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 140518579 11.66% 90.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 60300441 5.01% 95.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 39440661 3.27% 98.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 10869049 0.90% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1880938 0.16% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 607370 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1204659879 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 405736 14.35% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2202072 77.90% 92.25% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 219007 7.75% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 46812378 2.64% 2.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1058677272 59.68% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 18975 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 392 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 476256932 26.85% 89.17% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192182276 10.83% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1773948225 # Type of FU issued
system.cpu.iq.rate 1.472109 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2826815 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001594 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4755534756 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2315271702 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1716628380 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1729962441 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 210357388 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 106233073 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 38741 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 180751 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 28400293 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2345 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 48 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 58033544 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1572366 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 106573 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1968456139 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 63007739 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 525275195 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 216586351 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 49655 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2783 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 180751 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1386811 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 24440636 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 25827447 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1757502391 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 472605363 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 16445834 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 664057082 # number of memory reference insts executed
system.cpu.iew.exec_branches 110136743 # Number of branches executed
system.cpu.iew.exec_stores 191451719 # Number of stores executed
system.cpu.iew.exec_rate 1.458462 # Inst execution rate
system.cpu.iew.wb_sent 1717351615 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1716628496 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1259714523 # num instructions producing a value
system.cpu.iew.wb_consumers 1819339484 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.424543 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.692402 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 346963425 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 25700222 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1146626335 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.414143 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.834829 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 413585484 36.07% 36.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 412792006 36.00% 72.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 87637452 7.64% 79.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 122098814 10.65% 90.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 23946599 2.09% 92.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 25447448 2.22% 94.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 16362955 1.43% 96.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 12115407 1.06% 97.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 32640170 2.85% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1146626335 # Number of insts commited each cycle
system.cpu.commit.committedInsts 880025277 # Number of instructions committed
system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228180 # Number of memory references committed
system.cpu.commit.loads 419042122 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 107161574 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions.
system.cpu.commit.function_calls 1061692 # Number of function calls committed.
system.cpu.commit.bw_lim_events 32640170 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3082443517 # The number of ROB reads
system.cpu.rob.rob_writes 3994969913 # The number of ROB writes
system.cpu.timesIdled 60378 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 378551 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
system.cpu.cpi 1.369323 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.369323 # CPI: Total CPI of All Threads
system.cpu.ipc 0.730288 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.730288 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3534639638 # number of integer regfile reads
system.cpu.int_regfile_writes 1966129317 # number of integer regfile writes
system.cpu.fp_regfile_reads 116 # number of floating regfile reads
system.cpu.misc_regfile_reads 905981948 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 93457946 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 204658 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 204658 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 428893 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 246296 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 246296 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1854 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1328951 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1330805 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59200 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56250752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 56309952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 56309952 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 868818500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1393500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 675040498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.icache.replacements 41 # number of replacements
system.cpu.icache.tagsinuse 797.090296 # Cycle average of tags in use
system.cpu.icache.total_refs 184711350 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 199687.945946 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 797.090296 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.389204 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.389204 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 184711350 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 184711350 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 184711350 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 184711350 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 184711350 # number of overall hits
system.cpu.icache.overall_hits::total 184711350 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1427 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1427 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1427 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1427 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1427 # number of overall misses
system.cpu.icache.overall_misses::total 1427 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 89875000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 89875000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 89875000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 89875000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 89875000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 89875000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 184712777 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 184712777 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 184712777 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 184712777 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 184712777 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 184712777 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000008 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000008 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000008 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000008 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000008 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000008 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62981.779958 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 62981.779958 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 62981.779958 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 62981.779958 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 295 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 73.750000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 498 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 498 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 498 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 498 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 498 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 498 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 929 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 929 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 929 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 929 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 929 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62714500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 62714500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62714500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 62714500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62714500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 62714500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67507.534984 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67507.534984 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67507.534984 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 67507.534984 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67507.534984 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 67507.534984 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2555 # number of replacements
system.cpu.l2cache.tagsinuse 22235.283270 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531263 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24186 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.965724 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20778.086187 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 782.941763 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 674.255320 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.634097 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.023893 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.020577 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.678567 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 199174 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 199206 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 428893 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 428893 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 224393 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 224393 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 423567 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 423599 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 423567 # number of overall hits
system.cpu.l2cache.overall_hits::total 423599 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 893 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4555 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5448 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21903 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21903 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 893 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26458 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 27351 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 893 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26458 # number of overall misses
system.cpu.l2cache.overall_misses::total 27351 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 61459500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 411619000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 473078500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1503938500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1503938500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 61459500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1915557500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1977017000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 61459500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1915557500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1977017000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 925 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 203729 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 204654 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 428893 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246296 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246296 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 925 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 450025 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 450950 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 925 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 450025 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 450950 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965405 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022358 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.026621 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088930 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.088930 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965405 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.058792 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060652 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965405 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.058792 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060652 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68823.628219 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 90366.410538 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 86835.260646 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68663.584897 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68663.584897 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68823.628219 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72399.935747 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72283.170634 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68823.628219 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72399.935747 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72283.170634 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks
system.cpu.l2cache.writebacks::total 2533 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 893 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4555 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5448 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21903 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21903 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 893 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26458 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27351 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 893 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26458 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27351 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50370750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 353707250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 404078000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1234253000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1234253000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50370750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1587960250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1638331000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50370750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1587960250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1638331000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965405 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022358 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026621 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088930 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088930 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965405 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058792 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060652 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965405 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058792 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060652 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56406.215006 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77652.524698 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74169.970631 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56350.865178 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56350.865178 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.215006 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60018.151410 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59900.223027 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.215006 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60018.151410 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59900.223027 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 445929 # number of replacements
system.cpu.dcache.tagsinuse 4092.296880 # Cycle average of tags in use
system.cpu.dcache.total_refs 449973128 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 450025 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 999.884735 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 960887000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4092.296880 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999096 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999096 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 262033427 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 262033427 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187939697 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187939697 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 449973124 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 449973124 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 449973124 # number of overall hits
system.cpu.dcache.overall_hits::total 449973124 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 211198 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 211198 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 246361 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 246361 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 457559 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 457559 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 457559 # number of overall misses
system.cpu.dcache.overall_misses::total 457559 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3104170500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3104170500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4487459000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4487459000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7591629500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7591629500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7591629500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7591629500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 262244625 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 262244625 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 450430683 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 450430683 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 450430683 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 450430683 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000805 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000805 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.001016 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.001016 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001016 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001016 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14697.916173 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14697.916173 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18214.973149 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 18214.973149 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16591.586003 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16591.586003 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.702703 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 428893 # number of writebacks
system.cpu.dcache.writebacks::total 428893 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7460 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7460 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 70 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 70 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7530 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7530 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7530 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7530 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203738 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 203738 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246291 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 246291 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 450029 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 450029 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 450029 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 450029 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2608561002 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2608561002 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3994205500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3994205500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6602766502 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6602766502 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6602766502 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6602766502 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000777 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000777 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000999 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000999 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12803.507456 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12803.507456 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16217.423698 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16217.423698 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

149
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
View file

@ -1,149 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

44
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -1,44 +0,0 @@
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:35
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 963992672000 because target called exit()

63
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,63 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
sim_ticks 963992672000 # Number of ticks simulated
final_tick 963992672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 988845 # Simulator instruction rate (inst/s)
host_op_rate 1822001 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1083195788 # Simulator tick rate (ticks/s)
host_mem_usage 286888 # Number of bytes of host memory used
host_seconds 889.95 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452911 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586471 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 864451002 # Number of bytes written to this memory
system.physmem.bytes_written::total 864451002 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558817 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 188186058 # Number of write requests responded to by this memory
system.physmem.num_writes::total 188186058 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9846686428 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11757959163 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9846686428 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9846686428 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 896740221 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 896740221 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 12654699384 # Throughput (bytes/s)
system.membus.data_through_bus 12199037473 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985345 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 2123381 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354440 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read
system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228180 # number of memory refs
system.cpu.num_load_insts 419042122 # Number of load instructions
system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1927985345 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

222
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -1,222 +0,0 @@
[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[0]

2
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
View file

@ -1,2 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

44
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -1,44 +0,0 @@
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 11 2013 13:21:48
gem5 started Mar 11 2013 13:30:24
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1800193398000 because target called exit()

414
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,414 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.800193 # Number of seconds simulated
sim_ticks 1800193398000 # Number of ticks simulated
final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 510604 # Simulator instruction rate (inst/s)
host_op_rate 940816 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1044499940 # Simulator tick rate (ticks/s)
host_mem_usage 295340 # Number of bytes of host memory used
host_seconds 1723.50 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 160704 # Number of bytes written to this memory
system.physmem.bytes_written::total 160704 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2511 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2511 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 934548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 89270 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 89270 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 89270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 1049487 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 5039 # Transaction distribution
system.membus.trans_dist::ReadResp 5039 # Transaction distribution
system.membus.trans_dist::Writeback 2511 # Transaction distribution
system.membus.trans_dist::ReadExReq 21970 # Transaction distribution
system.membus.trans_dist::ReadExResp 21970 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1889280 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3600386796 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 2123381 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354440 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read
system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228180 # number of memory refs
system.cpu.num_load_insts 419042122 # Number of load instructions
system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3600386796 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 660.197305 # Cycle average of tags in use
system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 660.197305 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1186515974 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1186515974 # number of overall hits
system.cpu.icache.overall_hits::total 1186515974 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
system.cpu.icache.overall_misses::total 722 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39712000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39712000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39712000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39712000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39712000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39712000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1186516696 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1186516696 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1186516696 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

33
tests/long/se/00.gzip/test.py
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@ -1,33 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Korey Sewell
m5.util.addToPath('../configs/common')
from cpu2000 import gzip_log
workload = gzip_log(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()