stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in the DMA port.
This commit is contained in:
Andreas Hansson
parent
69e82539fd
commit
a4329af937
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,54 +1,54 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.624688 # Number of seconds simulated
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sim_ticks 2624688000000 # Number of ticks simulated
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final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 2.624627 # Number of seconds simulated
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sim_ticks 2624627401000 # Number of ticks simulated
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final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 509092 # Simulator instruction rate (inst/s)
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host_op_rate 647812 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 22195691402 # Simulator tick rate (ticks/s)
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host_mem_usage 379628 # Number of bytes of host memory used
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host_seconds 118.25 # Real time elapsed on the host
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sim_insts 60201138 # Number of instructions simulated
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sim_ops 76605123 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
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host_inst_rate 463403 # Simulator instruction rate (inst/s)
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host_op_rate 589674 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 20203281292 # Simulator tick rate (ticks/s)
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host_mem_usage 381220 # Number of bytes of host memory used
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host_seconds 129.91 # Real time elapsed on the host
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sim_insts 60201162 # Number of instructions simulated
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sim_ops 76605148 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory
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system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory
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system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory
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system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
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system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory
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system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
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@ -69,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 14996726 # DTB read hits
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system.cpu.dtb.read_misses 7357 # DTB read misses
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system.cpu.dtb.write_hits 11231612 # DTB write hits
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system.cpu.dtb.read_hits 14996727 # DTB read hits
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system.cpu.dtb.read_misses 7361 # DTB read misses
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system.cpu.dtb.write_hits 11231610 # DTB write hits
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system.cpu.dtb.write_misses 2211 # DTB write misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 15004083 # DTB read accesses
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system.cpu.dtb.write_accesses 11233823 # DTB write accesses
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system.cpu.dtb.read_accesses 15004088 # DTB read accesses
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system.cpu.dtb.write_accesses 11233821 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 26228338 # DTB hits
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system.cpu.dtb.misses 9568 # DTB misses
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system.cpu.dtb.accesses 26237906 # DTB accesses
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system.cpu.itb.inst_hits 61495107 # ITB inst hits
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system.cpu.dtb.hits 26228337 # DTB hits
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system.cpu.dtb.misses 9572 # DTB misses
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system.cpu.dtb.accesses 26237909 # DTB accesses
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system.cpu.itb.inst_hits 61495131 # ITB inst hits
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system.cpu.itb.inst_misses 4471 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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@ -105,79 +105,79 @@ system.cpu.itb.domain_faults 0 # Nu
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 61499578 # ITB inst accesses
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system.cpu.itb.hits 61495107 # DTB hits
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system.cpu.itb.inst_accesses 61499602 # ITB inst accesses
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system.cpu.itb.hits 61495131 # DTB hits
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system.cpu.itb.misses 4471 # DTB misses
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system.cpu.itb.accesses 61499578 # DTB accesses
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system.cpu.numCycles 5249376000 # number of cpu cycles simulated
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system.cpu.itb.accesses 61499602 # DTB accesses
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system.cpu.numCycles 5249254802 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 60201138 # Number of instructions committed
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system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses
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system.cpu.committedInsts 60201162 # Number of instructions committed
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system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
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system.cpu.num_func_calls 2139913 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls
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system.cpu.num_int_insts 68872510 # number of integer instructions
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system.cpu.num_func_calls 2139915 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls
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system.cpu.num_int_insts 68872531 # number of integer instructions
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system.cpu.num_fp_insts 10269 # number of float instructions
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system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read
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system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written
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system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read
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system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
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system.cpu.num_mem_refs 27395681 # number of memory refs
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system.cpu.num_load_insts 15660705 # Number of load instructions
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system.cpu.num_store_insts 11734976 # Number of store instructions
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system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles
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system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles
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system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.871278 # Percentage of idle cycles
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system.cpu.num_mem_refs 27395680 # number of memory refs
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system.cpu.num_load_insts 15660706 # Number of load instructions
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system.cpu.num_store_insts 11734974 # Number of store instructions
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system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles
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system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles
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system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.871333 # Percentage of idle cycles
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
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system.cpu.icache.replacements 855878 # number of replacements
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system.cpu.icache.tagsinuse 510.920723 # Cycle average of tags in use
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system.cpu.icache.total_refs 60638717 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 856390 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 70.807362 # Average number of references to valid blocks.
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system.cpu.icache.replacements 855895 # number of replacements
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system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use
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system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 510.920723 # Average occupied blocks per requestor
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system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 60638717 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 60638717 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 60638717 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 60638717 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 60638717 # number of overall hits
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system.cpu.icache.overall_hits::total 60638717 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 856390 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 856390 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 856390 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses
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system.cpu.icache.overall_misses::total 856390 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits
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system.cpu.icache.overall_hits::total 60638724 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses
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system.cpu.icache.overall_misses::total 856407 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -186,18 +186,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856390 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 856390 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 856390 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -208,90 +208,90 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926
|
|||
system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 627203 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.replacements 627232 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 23170043 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 619214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 23170010 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 619246 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14169509500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14169509500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14169509500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13564965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13564965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10224291 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10224291 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses::cpu.data 23789256 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 23789256 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 23789256 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 23789256 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027180 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.027180 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024505 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046013 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046013 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.026030 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.026030 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.026030 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.026030 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.455941 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.455941 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35797.044068 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 35797.044068 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.573309 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.573309 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22881.874893 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22881.874893 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -300,54 +300,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 595968 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024501 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046025 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046025 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency
|
||||
system.cpu.dcache.writebacks::writebacks 595999 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 595999 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368699 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 368699 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250547 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 250547 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11397 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11397 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 619246 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 619246 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 619246 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 619246 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463269500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463269500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8467748000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8467748000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131961000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131961000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931017500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12931017500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931017500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12931017500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182084322500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182084322500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41323476000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41323476000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223407798500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 223407798500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027180 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027180 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046013 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046013 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.026030 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.026030 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.455941 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.455941 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33797.044068 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33797.044068 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.573309 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.573309 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
|
|
@ -355,141 +355,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
|
|||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 61913 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.replacements 61916 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 50867.720143 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1683066 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 127296 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 13.221672 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 2574019400000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 37864.952088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 6985.681192 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6013.199864 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.577773 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.091768 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.776184 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.091754 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.776180 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8772 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 844153 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 370237 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1226711 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 595999 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 595999 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 114435 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 114435 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 114469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 114469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8772 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 844153 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 484706 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1341180 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8772 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 844153 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 484706 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1341180 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 20481 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 20482 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 133179 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 133179 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 143034 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 153657 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 143038 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 153661 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 143034 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 153657 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 143038 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 153661 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 552086500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512764500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1065268500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1041000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 1041000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6925666500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6925666500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency
|
||||
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|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52003.663910 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -498,92 +498,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198742782500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025938 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537775 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537775 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
|
|
@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
|
|||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
|
|
|
|||
Loading…
Reference in a new issue