930 lines
108 KiB
Plaintext
930 lines
108 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.534173 # Number of seconds simulated
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sim_ticks 2534173219000 # Number of ticks simulated
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final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 83771 # Simulator instruction rate (inst/s)
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host_op_rate 107754 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3503174864 # Simulator tick rate (ticks/s)
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host_mem_usage 385312 # Number of bytes of host memory used
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host_seconds 723.39 # Real time elapsed on the host
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sim_insts 60599410 # Number of instructions simulated
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sim_ops 77948210 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory
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system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 51719750 # DTB read hits
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system.cpu.dtb.read_misses 77229 # DTB read misses
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system.cpu.dtb.write_hits 11809411 # DTB write hits
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system.cpu.dtb.write_misses 17373 # DTB write misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 4263 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 51796979 # DTB read accesses
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system.cpu.dtb.write_accesses 11826784 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 63529161 # DTB hits
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system.cpu.dtb.misses 94602 # DTB misses
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system.cpu.dtb.accesses 63623763 # DTB accesses
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system.cpu.itb.inst_hits 13045523 # ITB inst hits
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system.cpu.itb.inst_misses 12142 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 2586 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 13057665 # ITB inst accesses
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system.cpu.itb.hits 13045523 # DTB hits
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system.cpu.itb.misses 12142 # DTB misses
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system.cpu.itb.accesses 13057665 # DTB accesses
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system.cpu.numCycles 475815628 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing
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system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb
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system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps
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system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions
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system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed
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system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 110503842 70.97% 70.97% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 14006844 9.00% 79.97% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 7305691 4.69% 84.66% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 6085046 3.91% 88.57% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 57592 0.65% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued
|
|
system.cpu.iq.rate 0.265182 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 225103 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 11726228 # Number of branches executed
|
|
system.cpu.iew.exec_stores 12321727 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.258426 # Inst execution rate
|
|
system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 47710631 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 60749791 # Number of instructions committed
|
|
system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27515604 # Number of memory references committed
|
|
system.cpu.commit.loads 15716666 # Number of loads committed
|
|
system.cpu.commit.membars 413138 # Number of memory barriers committed
|
|
system.cpu.commit.branches 10023383 # Number of branches committed
|
|
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 69136784 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 996034 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 249407638 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 208557399 # The number of ROB writes
|
|
system.cpu.timesIdled 1773714 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 320111554 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 4592442776 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 60599410 # Number of Instructions Simulated
|
|
system.cpu.committedOps 77948210 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 60599410 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.851819 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.851819 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.127359 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.127359 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 556670718 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 89963165 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 8373 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2910 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 132949410 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 912934 # number of misc regfile writes
|
|
system.cpu.icache.replacements 989799 # number of replacements
|
|
system.cpu.icache.tagsinuse 511.593898 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 11967809 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 990311 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 12.084900 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 511.593898 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 11967809 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 11967809 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 11967809 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 11967809 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 11967809 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 11967809 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1073749 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1073749 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1073749 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1073749 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1073749 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1073749 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14109467991 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 14109467991 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 14109467991 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 14109467991 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 14109467991 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 14109467991 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 13041558 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 13041558 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 13041558 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 13041558 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 13041558 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 13041558 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082333 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.082333 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.082333 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.082333 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.082333 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.082333 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13140.378236 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13140.378236 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13140.378236 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13140.378236 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 4599 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 306 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 15.029412 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83395 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 83395 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 83395 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 83395 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 83395 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 83395 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990354 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 990354 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 990354 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 990354 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 990354 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 990354 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11451236993 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 11451236993 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11451236993 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 11451236993 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11451236993 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 11451236993 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075938 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.075938 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.075938 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.771487 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.771487 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 645297 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.991711 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 21788102 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 645809 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 33.737687 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.991711 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13926305 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13926305 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 7288115 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 7288115 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 284783 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 284783 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 21214420 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 21214420 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 21214420 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 21214420 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 727409 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 727409 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2962946 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2962946 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13565 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 13565 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3690355 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3690355 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3690355 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3690355 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441109500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9441109500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104189875245 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 104189875245 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180817000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 180817000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 318500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 318500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 113630984745 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 113630984745 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 113630984745 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 113630984745 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 14653714 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 14653714 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10251061 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10251061 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298348 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 298348 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285754 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 285754 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 24904775 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 24904775 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 24904775 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 24904775 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049640 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.049640 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289038 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.289038 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045467 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045467 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000052 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.148179 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.148179 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.148179 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.148179 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12979.093605 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 12979.093605 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35164.284211 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 35164.284211 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13329.671950 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13329.671950 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21233.333333 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21233.333333 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30791.342498 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30791.342498 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 25421 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 15604 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2521 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.083697 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 56.948905 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 609382 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 609382 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339956 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 339956 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713832 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2713832 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1350 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1350 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3053788 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3053788 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3053788 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3053788 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387453 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 387453 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249114 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 249114 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12215 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12215 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 636567 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 636567 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 636567 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 636567 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4759977000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4759977000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8542104919 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8542104919 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141597500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141597500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 288500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 288500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13302081919 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 13302081919 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13302081919 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 13302081919 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356244500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356244500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41726674069 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41726674069 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224082918569 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 224082918569 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026441 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026441 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024301 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024301 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040942 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040942 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000052 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025560 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025560 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12285.301701 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12285.301701 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.943235 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.943235 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11592.099877 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11592.099877 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19233.333333 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19233.333333 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 64413 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 51352.307141 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1928116 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 129809 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 14.853485 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 2498979146000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 36881.759655 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 43.531667 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 8178.474419 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6248.541162 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.562771 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000664 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.124794 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.095345 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.783574 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 82776 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11675 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 976745 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 388849 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1460045 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 609382 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 609382 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 113019 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 113019 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 82776 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 11675 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 976745 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 501868 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1573064 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 82776 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 11675 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 976745 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 501868 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1573064 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12352 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 10732 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 23140 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2931 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2931 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133209 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133209 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12352 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143941 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 55 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12352 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143941 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 156349 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2897000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 657788500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 564922998 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1225668498 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1151000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 1151000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7004343998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7004343998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2897000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 657788500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7569266996 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 8230012496 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2897000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 657788500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7569266996 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 8230012496 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 82831 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11676 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 989097 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 399581 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1483185 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 609382 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 609382 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2973 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2973 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 15 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 15 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246228 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 246228 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 82831 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 11676 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 989097 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 645809 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1729413 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 82831 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 11676 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 989097 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 645809 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1729413 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000664 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000086 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012488 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026858 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.015602 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985873 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985873 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.200000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540999 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.540999 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000664 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000086 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012488 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.222885 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.090406 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000664 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000086 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012488 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.222885 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.090406 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52672.727273 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53253.602655 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52639.116474 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52967.523682 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 392.698738 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 392.698738 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52581.612339 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52581.612339 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52672.727273 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53253.602655 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52585.899751 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52638.728076 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52672.727273 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53253.602655 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52585.899751 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52638.728076 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 59144 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 59144 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12344 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10670 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 23070 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2931 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2931 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133209 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133209 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12344 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143879 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 156279 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12344 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143879 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 156279 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2227000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 506657500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 431701998 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940634498 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117255500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117255500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5363194498 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5363194498 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2227000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 506657500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5794896496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6303828996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2227000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506657500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5794896496 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6303828996 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166679722000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166685014000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32284839499 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32284839499 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198964561499 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198969853499 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026703 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015554 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985873 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985873 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540999 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540999 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.090365 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.090365 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41044.839598 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40459.418744 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40773.060165 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40005.288298 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40005.288298 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40261.502586 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40261.502586 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|