1677 lines
193 KiB
Plaintext
1677 lines
193 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.603785 # Number of seconds simulated
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sim_ticks 2603784540500 # Number of ticks simulated
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final_tick 2603784540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 66983 # Simulator instruction rate (inst/s)
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host_op_rate 86203 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2766471262 # Simulator tick rate (ticks/s)
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host_mem_usage 391460 # Number of bytes of host memory used
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host_seconds 941.19 # Real time elapsed on the host
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sim_insts 63043892 # Number of instructions simulated
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sim_ops 81133946 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 398208 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4365108 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 424768 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 5242032 # Number of bytes read from this memory
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system.physmem.bytes_read::total 131542884 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 398208 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 424768 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 822976 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4259200 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7288336 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 6222 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 68277 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 6637 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 81933 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15301920 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66550 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 823834 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 46513268 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 152934 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1676447 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 516 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 163135 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 2013236 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 50519881 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 152934 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 163135 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 316069 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1635773 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6529 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 1156830 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2799132 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1635773 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 46513268 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 152934 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 1682976 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 516 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 163135 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 3170066 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53319012 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.replacements 72716 # number of replacements
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system.l2c.tagsinuse 53054.127627 # Cycle average of tags in use
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system.l2c.total_refs 1921007 # Total number of references to valid blocks.
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system.l2c.sampled_refs 137887 # Sample count of references to valid blocks.
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system.l2c.avg_refs 13.931748 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 37702.750245 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.dtb.walker 4.539457 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.itb.walker 0.000261 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.inst 4229.509835 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.data 2960.828509 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.dtb.walker 15.234392 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.inst 4027.989211 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.data 4113.275716 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.575298 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.inst 0.064537 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.data 0.045179 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.dtb.walker 0.000232 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.inst 0.061462 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.data 0.062764 # Average percentage of cache occupancy
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system.l2c.occ_percent::total 0.809542 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::cpu0.dtb.walker 35167 # number of ReadReq hits
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|
system.l2c.ReadReq_hits::cpu0.itb.walker 5217 # number of ReadReq hits
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|
system.l2c.ReadReq_hits::cpu0.inst 398405 # number of ReadReq hits
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|
system.l2c.ReadReq_hits::cpu0.data 165702 # number of ReadReq hits
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|
system.l2c.ReadReq_hits::cpu1.dtb.walker 54913 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 6451 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 614994 # number of ReadReq hits
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|
system.l2c.ReadReq_hits::cpu1.data 202172 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1483021 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 584447 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 584447 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1035 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 765 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 1800 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 171 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 381 # number of SCUpgradeReq hits
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|
system.l2c.ReadExReq_hits::cpu0.data 48064 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 58867 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 106931 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 35167 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 5217 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 398405 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 213766 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 54913 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 6451 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 614994 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 261039 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1589952 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 35167 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 5217 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 398405 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 213766 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 54913 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 6451 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 614994 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 261039 # number of overall hits
|
|
system.l2c.overall_hits::total 1589952 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 6098 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6350 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 6599 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 6280 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 25362 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 5678 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 4325 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 10003 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 781 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 592 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1373 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 63319 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 76915 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 140234 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 6098 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 69669 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 6599 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 83195 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 165596 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 6098 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 69669 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 6599 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 83195 # number of overall misses
|
|
system.l2c.overall_misses::total 165596 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 629000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 325278000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 333913000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1103000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 350966000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 330367497 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1342368497 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 20556482 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 27727000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 48283482 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1413500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7215998 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 8629498 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 3400238492 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 4067056495 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 7467294987 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 629000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 112000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 325278000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 3734151492 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 1103000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 350966000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 4397423992 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 8809663484 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 629000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 112000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 325278000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 3734151492 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 1103000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 350966000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 4397423992 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 8809663484 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 35179 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 5219 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 404503 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 172052 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 54934 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 6451 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 621593 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 208452 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1508383 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 584447 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 584447 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 6713 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 5090 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 11803 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 991 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 763 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1754 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 111383 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 135782 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 247165 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 35179 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 5219 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 404503 # number of demand (read+write) accesses
|
|
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|
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|
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
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|
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system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
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|
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system.l2c.fast_writes 0 # number of fast writes performed
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|
|
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|
|
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|
|
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|
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|
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|
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|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.245668 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010605 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.241609 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.094283 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000341 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000383 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015058 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.245668 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010605 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.241609 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.094283 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40415.399240 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40406.314468 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40738.817362 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40030.815252 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.056416 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40039.134560 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40039.048656 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.172297 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40033.496723 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41457.990366 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40504.355392 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40934.944357 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41363.480232 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40496.981989 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40904.983621 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41363.480232 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40496.981989 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40904.983621 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 9065848 # DTB read hits
|
|
system.cpu0.dtb.read_misses 36360 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5285915 # DTB write hits
|
|
system.cpu0.dtb.write_misses 6625 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 2165 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 342 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 9102208 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5292540 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 14351763 # DTB hits
|
|
system.cpu0.dtb.misses 42985 # DTB misses
|
|
system.cpu0.dtb.accesses 14394748 # DTB accesses
|
|
system.cpu0.itb.inst_hits 4413372 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 5476 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 4418848 # ITB inst accesses
|
|
system.cpu0.itb.hits 4413372 # DTB hits
|
|
system.cpu0.itb.misses 5476 # DTB misses
|
|
system.cpu0.itb.accesses 4418848 # DTB accesses
|
|
system.cpu0.numCycles 70012496 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.BPredUnit.lookups 6217398 # Number of BP lookups
|
|
system.cpu0.BPredUnit.condPredicted 4733750 # Number of conditional branches predicted
|
|
system.cpu0.BPredUnit.condIncorrect 327130 # Number of conditional branches incorrect
|
|
system.cpu0.BPredUnit.BTBLookups 4014715 # Number of BTB lookups
|
|
system.cpu0.BPredUnit.BTBHits 3051469 # Number of BTB hits
|
|
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.BPredUnit.usedRAS 700588 # Number of times the RAS was used to get a target.
|
|
system.cpu0.BPredUnit.RASInCorrect 31775 # Number of incorrect RAS predictions.
|
|
system.cpu0.fetch.icacheStallCycles 12151517 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 33217564 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 6217398 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 3752057 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 7806548 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 1581421 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 67728 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.BlockedCycles 22157211 # Number of cycles fetch has spent blocked
|
|
system.cpu0.fetch.MiscStallCycles 5913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 54633 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 92488 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 4411708 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 171100 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 2593 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 43471985 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.986228 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.366083 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 35673429 82.06% 82.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 623255 1.43% 83.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 822107 1.89% 85.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 699884 1.61% 87.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 794381 1.83% 88.82% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 577438 1.33% 90.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 719535 1.66% 91.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 371399 0.85% 92.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 3190557 7.34% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 43471985 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.088804 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.474452 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 12679354 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 22114744 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 7023055 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 583785 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1071047 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 976895 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 65884 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 41430285 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 215511 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1071047 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 13270486 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 5876098 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 14061413 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 6963478 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 2229463 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 40231881 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 440788 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LSQFullEvents 1249784 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.FullRegisterEvents 63 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 40621534 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 181781749 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 181747462 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 34287 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 31667723 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 8953810 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 461246 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 417498 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 5499956 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 7912486 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 5888217 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1140849 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 1237786 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 37992607 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 949484 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 38225982 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 89034 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 6781394 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 14357702 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 260797 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 43471985 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.879325 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.495049 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 27798434 63.95% 63.95% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 6055917 13.93% 77.88% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3289826 7.57% 85.44% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2491193 5.73% 91.17% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 2118698 4.87% 96.05% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 969648 2.23% 98.28% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 500024 1.15% 99.43% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 192302 0.44% 99.87% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 55943 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 43471985 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 25214 2.35% 2.35% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 458 0.04% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 837969 78.03% 80.42% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 210208 19.58% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 22961950 60.07% 60.21% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 49879 0.13% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 12 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 9545903 24.97% 85.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 5615312 14.69% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 38225982 # Type of FU issued
|
|
system.cpu0.iq.rate 0.545988 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 1073849 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.028092 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 121121114 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 45731569 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 35283041 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 8365 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 4658 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3880 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 39243245 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 4372 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 321528 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1492825 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3508 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 13401 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 615446 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 2149535 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 5390 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1071047 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 4218607 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 98464 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 39061403 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 95550 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 7912486 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 5888217 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 616723 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 40108 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 2851 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 13401 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 172679 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 129654 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 302333 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 37800204 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 9383648 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 425778 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 119312 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 14941647 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 4991029 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 5557999 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.539907 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 37583639 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 35286921 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 18740450 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 35992151 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.504009 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.520682 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 6642216 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 688687 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 262418 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 42437322 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.753690 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.709171 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 30360862 71.54% 71.54% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 5984991 14.10% 85.65% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1981270 4.67% 90.31% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 1011467 2.38% 92.70% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 801137 1.89% 94.59% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 524678 1.24% 95.82% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 395620 0.93% 96.75% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 217374 0.51% 97.27% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1159923 2.73% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 42437322 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 24255943 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 31984592 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 11692432 # Number of memory references committed
|
|
system.cpu0.commit.loads 6419661 # Number of loads committed
|
|
system.cpu0.commit.membars 234476 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 4345348 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 28253924 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 499843 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 1159923 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 79019948 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 78326882 # The number of ROB writes
|
|
system.cpu0.timesIdled 363516 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 26540511 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 5137512787 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 24175201 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 31903850 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 24175201 # Number of Instructions Simulated
|
|
system.cpu0.cpi 2.896046 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 2.896046 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.345298 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.345298 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 176381452 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 35063385 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 3376 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 954 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 47472836 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 527620 # number of misc regfile writes
|
|
system.cpu0.icache.replacements 404634 # number of replacements
|
|
system.cpu0.icache.tagsinuse 511.577738 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 3973841 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 405146 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 9.808417 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 511.577738 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 3973841 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 3973841 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 3973841 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 3973841 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 3973841 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 3973841 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 437728 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 437728 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 437728 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 437728 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 437728 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 437728 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5954762997 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5954762997 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 5954762997 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 5954762997 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 5954762997 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 5954762997 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4411569 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 4411569 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 4411569 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 4411569 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 4411569 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 4411569 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099223 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.099223 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099223 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.099223 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099223 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.099223 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13603.797328 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13603.797328 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13603.797328 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13603.797328 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 2654 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.430556 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32567 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 32567 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 32567 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 32567 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 32567 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 32567 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405161 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 405161 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 405161 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 405161 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 405161 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 405161 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4858454497 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4858454497 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4858454497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4858454497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4858454497 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4858454497 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8271000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8271000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8271000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8271000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091841 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.091841 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.091841 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11991.416985 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 275305 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 476.472696 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 9563233 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 275817 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 34.672384 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 50121000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 476.472696 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.930611 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.930611 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 5934886 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 5934886 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3237835 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 3237835 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174610 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 174610 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171576 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 171576 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 9172721 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 9172721 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 9172721 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 9172721 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 390009 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 390009 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1580289 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1580289 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7755 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7755 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1970298 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1970298 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1970298 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1970298 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5381478000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5381478000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64293852363 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 64293852363 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88752000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 88752000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 73359500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 73359500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 69675330363 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 69675330363 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 69675330363 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 69675330363 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6324895 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 6324895 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818124 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 4818124 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183513 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 183513 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179331 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 179331 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 11143019 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 11143019 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 11143019 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 11143019 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061663 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.061663 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327988 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.327988 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048514 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048514 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043244 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043244 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176819 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.176819 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176819 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.176819 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13798.343115 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13798.343115 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40684.869896 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40684.869896 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.774570 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.774570 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9459.638943 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9459.638943 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35362.838699 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 35362.838699 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35362.838699 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 35362.838699 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 7486 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 3477 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 90 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.464029 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 38.633333 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 255914 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 255914 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200897 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 200897 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449259 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1449259 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 477 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 477 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650156 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1650156 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650156 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1650156 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189112 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 189112 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131030 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 131030 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8426 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8426 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7752 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7752 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 320142 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 320142 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 320142 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 320142 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2327531500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2327531500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4469430491 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4469430491 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67004000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67004000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 57855500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 57855500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6796961991 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 6796961991 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6796961991 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 6796961991 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432598000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432598000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1289898395 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1289898395 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14722496395 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14722496395 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029900 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027195 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027195 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045915 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045915 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043227 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043227 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028730 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028730 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12307.688037 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12307.688037 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34109.978562 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34109.978562 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7952.053169 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.053169 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7463.299794 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7463.299794 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 43411799 # DTB read hits
|
|
system.cpu1.dtb.read_misses 44882 # DTB read misses
|
|
system.cpu1.dtb.write_hits 7014123 # DTB write hits
|
|
system.cpu1.dtb.write_misses 11858 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2347 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 3336 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 317 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 43456681 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 7025981 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 50425922 # DTB hits
|
|
system.cpu1.dtb.misses 56740 # DTB misses
|
|
system.cpu1.dtb.accesses 50482662 # DTB accesses
|
|
system.cpu1.itb.inst_hits 9129638 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 6055 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1576 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 1653 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 9135693 # ITB inst accesses
|
|
system.cpu1.itb.hits 9129638 # DTB hits
|
|
system.cpu1.itb.misses 6055 # DTB misses
|
|
system.cpu1.itb.accesses 9135693 # DTB accesses
|
|
system.cpu1.numCycles 413048277 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.BPredUnit.lookups 9610060 # Number of BP lookups
|
|
system.cpu1.BPredUnit.condPredicted 7888453 # Number of conditional branches predicted
|
|
system.cpu1.BPredUnit.condIncorrect 467347 # Number of conditional branches incorrect
|
|
system.cpu1.BPredUnit.BTBLookups 6680212 # Number of BTB lookups
|
|
system.cpu1.BPredUnit.BTBHits 5602853 # Number of BTB hits
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.BPredUnit.usedRAS 834872 # Number of times the RAS was used to get a target.
|
|
system.cpu1.BPredUnit.RASInCorrect 50683 # Number of incorrect RAS predictions.
|
|
system.cpu1.fetch.icacheStallCycles 20902821 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 71155819 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 9610060 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 6437725 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 15200148 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 4519747 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 75962 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.BlockedCycles 79085155 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 48956 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 142448 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 9127576 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 837727 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 3443 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 118542872 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.725366 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.076680 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 103350754 87.18% 87.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 840912 0.71% 87.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 1013712 0.86% 88.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 2056350 1.73% 90.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 1628340 1.37% 91.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 605586 0.51% 92.37% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 2262195 1.91% 94.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 445115 0.38% 94.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 6339908 5.35% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 118542872 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.023266 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.172270 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 22607772 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 78712094 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 13698658 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 543937 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 2980411 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 1178240 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 102814 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 80488884 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 342985 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 2980411 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 24131061 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 32829819 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 41497762 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 12625753 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 4478066 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 74194515 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 19311 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 694411 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 3187694 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.FullRegisterEvents 34028 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 78612274 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 341980095 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 341920829 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 50181552 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 28430722 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 479709 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 419295 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 8182404 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 13956070 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 8535310 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 1073815 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 1496663 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 66987245 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 1207542 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 91662010 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 107326 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 18596353 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 52788554 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 287891 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 118542872 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.773239 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.509704 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 87045508 73.43% 73.43% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 8827320 7.45% 80.88% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 4565356 3.85% 84.73% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 3971386 3.35% 88.08% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 10748062 9.07% 97.14% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1958505 1.65% 98.80% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 1059536 0.89% 99.69% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 289761 0.24% 99.93% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 77438 0.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 118542872 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 27804 0.35% 0.35% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 991 0.01% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 7575099 95.91% 96.28% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 294066 3.72% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 39285679 42.86% 43.20% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 61425 0.07% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.27% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 44600762 48.66% 91.93% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 7398685 8.07% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 91662010 # Type of FU issued
|
|
system.cpu1.iq.rate 0.221916 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 7897960 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.086164 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 309913949 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 86800137 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 55536555 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 14796 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 99238492 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 7741 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 357612 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 3966417 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 4317 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 17649 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1516764 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 31964885 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 1028430 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 2980411 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 24884610 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 372296 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 68300564 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 134907 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 13956070 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 8535310 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 896808 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 67508 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 3396 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 17649 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 244559 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 171299 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 415858 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 88842251 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 43794323 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 2819759 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 105777 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 51113945 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 7256967 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 7319622 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.215089 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 87693649 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 55543356 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 30809625 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 54951337 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.134472 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.560671 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 18558974 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 919651 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 366370 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 115610884 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.426428 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.387814 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 98380656 85.10% 85.10% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 8456019 7.31% 92.41% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 2240447 1.94% 94.35% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 1287846 1.11% 95.46% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1284560 1.11% 96.57% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 584416 0.51% 97.08% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 1022455 0.88% 97.96% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 531646 0.46% 98.42% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1822839 1.58% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 115610884 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 38938330 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 49299735 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 17008199 # Number of memory references committed
|
|
system.cpu1.commit.loads 9989653 # Number of loads committed
|
|
system.cpu1.commit.membars 202304 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 6136573 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 43691789 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 556207 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 1822839 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 180532357 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 138785705 # The number of ROB writes
|
|
system.cpu1.timesIdled 1423841 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 294505405 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 4793867333 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 38868691 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 49230096 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 38868691 # Number of Instructions Simulated
|
|
system.cpu1.cpi 10.626761 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 10.626761 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.094102 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.094102 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 397649399 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 58356680 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 4927 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 90861332 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 429704 # number of misc regfile writes
|
|
system.cpu1.icache.replacements 621691 # number of replacements
|
|
system.cpu1.icache.tagsinuse 498.705536 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 8457096 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 622203 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 13.592181 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 498.705536 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.974034 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.974034 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 8457096 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 8457096 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 8457096 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 8457096 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 8457096 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 8457096 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 670427 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 670427 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 670427 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 670427 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 670427 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 670427 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8963788993 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 8963788993 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 8963788993 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 8963788993 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 8963788993 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 8963788993 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 9127523 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 9127523 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 9127523 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 9127523 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 9127523 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 9127523 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073451 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.073451 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073451 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.073451 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073451 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.073451 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13370.268490 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13370.268490 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13370.268490 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13370.268490 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.184211 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48189 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 48189 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 48189 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 48189 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 48189 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 48189 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622238 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 622238 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 622238 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 622238 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 622238 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 622238 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328903994 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328903994 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328903994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 7328903994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328903994 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 7328903994 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3208500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3208500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3208500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3208500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068172 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.068172 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.068172 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11778.297041 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 363699 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 487.062362 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 13149394 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 364069 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 36.117862 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 487.062362 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.951294 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.951294 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 8615849 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 8615849 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4289025 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 4289025 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104659 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 104659 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100738 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 100738 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 12904874 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 12904874 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 12904874 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 12904874 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 398775 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 398775 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 1559814 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 1559814 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14251 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 14251 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10935 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10935 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 1958589 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 1958589 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 1958589 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 1958589 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5911762000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 5911762000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56390406018 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 56390406018 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131021000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 131021000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 76240500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 76240500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 62302168018 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 62302168018 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 62302168018 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 62302168018 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9014624 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 9014624 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848839 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 5848839 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 118910 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 118910 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111673 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 111673 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 14863463 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 14863463 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 14863463 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 14863463 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044236 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.044236 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.266688 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.266688 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119847 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119847 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131772 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.131772 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131772 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.131772 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14824.805968 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14824.805968 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36152.006597 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 36152.006597 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9193.810961 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9193.810961 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6972.153635 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6972.153635 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 31809.720170 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 31809.720170 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 24015 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 11108 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 3240 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.412037 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 66.119048 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 328533 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 328533 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 166830 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 166830 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1397003 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 1397003 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1431 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1431 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563833 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 1563833 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563833 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 1563833 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231945 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 231945 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162811 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 162811 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12820 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12820 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10928 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10928 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 394756 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 394756 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 394756 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 394756 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2840785000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2840785000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5178833227 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5178833227 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89705500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89705500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54384500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54384500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8019618227 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 8019618227 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8019618227 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 8019618227 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169259240500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169259240500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40718348836 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40718348836 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209977589336 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209977589336 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025730 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025730 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027836 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027836 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107813 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107813 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097857 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097857 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026559 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026559 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12247.666473 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12247.666473 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31808.865660 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31808.865660 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6997.308892 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6997.308892 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4976.619693 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4976.619693 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1218779341193 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1218779341193 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 43799 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 53911 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|